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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1640036822604100001 Content-Type: text/plain; charset="utf-8" Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson --- linux-user/hppa/target_prctl.h | 2 +- target/hppa/cpu.h | 5 ++++- target/hppa/translate.c | 19 +++++++++++++++---- 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h index eb53b31ad5..5629ddbf39 100644 --- a/linux-user/hppa/target_prctl.h +++ b/linux-user/hppa/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 294fd7297f..45fd338b02 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -259,12 +259,14 @@ static inline target_ulong hppa_form_gva(CPUHPPAState= *env, uint64_t spc, return hppa_form_gva_psw(env->psw, spc, off); } =20 -/* Since PSW_{I,CB} will never need to be in tb->flags, reuse them. +/* + * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the * same value. */ #define TB_FLAG_SR_SAME PSW_I #define TB_FLAG_PRIV_SHIFT 8 +#define TB_FLAG_UNALIGN 0x400 =20 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *p= c, target_ulong *cs_base, @@ -279,6 +281,7 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *e= nv, target_ulong *pc, #ifdef CONFIG_USER_ONLY *pc =3D env->iaoq_f & -4; *cs_base =3D env->iaoq_b & -4; + flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; #else /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ flags |=3D env->psw & (PSW_W | PSW_C | PSW_D); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3b9744deb4..f555503024 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -272,8 +272,18 @@ typedef struct DisasContext { int mmu_idx; int privilege; bool psw_n_nonzero; + +#ifdef CONFIG_USER_ONLY + MemOp unalign; +#endif } DisasContext; =20 +#ifdef CONFIG_USER_ONLY +#define UNALIGN(C) (C)->unalign +#else +#define UNALIGN(C) 0 +#endif + /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ static int expand_sm_imm(DisasContext *ctx, int val) { @@ -1473,7 +1483,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 de= st, unsigned rb, =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); - tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1491,7 +1501,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 de= st, unsigned rb, =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); - tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1509,7 +1519,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 s= rc, unsigned rb, =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); - tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1527,7 +1537,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 s= rc, unsigned rb, =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); - tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -4102,6 +4112,7 @@ static void hppa_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->mmu_idx =3D MMU_USER_IDX; ctx->iaoq_f =3D ctx->base.pc_first | MMU_USER_IDX; ctx->iaoq_b =3D ctx->base.tb->cs_base | MMU_USER_IDX; + ctx->unalign =3D (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIG= N); #else ctx->privilege =3D (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; ctx->mmu_idx =3D (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_ID= X); --=20 2.25.1