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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1639976379; x=1642568380; bh=5HNAc9kbpo7/C7fkPG yRxz2tXdebnOcydGob30utdhM=; b=tsRyo+uGJXzT7WVW0xRMpwJ5eyAAu4SuCQ QsBJopzoxUoT3BzpWafMesP5rLVCaBFoI2rbqVC5TFFNaBxf2gg8ENsit0kGF4r5 2t+6O5TXi5oChfrs7OIQUkuyOIlCpbb4C0SkDR8RbE1DX111p+5qCAGTAihg1ufo Xr8nmhii9bab4yjDA928vX8o2NuabOFk78MUOu2Wdsv1WMGP6vhdLLqW81cafWan MT0DFRu4v+SAvD9F9eYCx9sIZ1DmGV+qtnpsrxfi/+AKpHG70h3KGWfbTc0NhLTy UMonhT6WaSLk1dothkKlve1QdDMD+VV7QipPqr39h3MTB0Tou2+A== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Frank Chang , Richard Henderson , Alistair Francis Subject: [PULL 34/88] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation Date: Mon, 20 Dec 2021 14:56:11 +1000 Message-Id: <20211220045705.62174-35-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211220045705.62174-1-alistair.francis@opensource.wdc.com> References: <20211220045705.62174-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=9816edf2f=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1639979587472100001 Content-Type: text/plain; charset="utf-8" From: Frank Chang Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into calculation for RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-27-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 27 ++++++++++++++++--------- target/riscv/cpu_helper.c | 16 ++++++++++++--- target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++++++- 3 files changed, 42 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 709b7c3abb..11a0f41b27 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -430,18 +430,27 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *e= nv) #endif =20 /* - * A simplification for VLMAX - * =3D (1 << LMUL) * VLEN / (8 * (1 << SEW)) - * =3D (VLEN << LMUL) / (8 << SEW) - * =3D (VLEN << LMUL) >> (SEW + 3) - * =3D VLEN >> (SEW + 3 - LMUL) + * Encode LMUL to lmul as follows: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + * + * then, we can calculate VLMAX =3D vlen >> (vsew + 3 - lmul) + * e.g. vlen =3D 256 bits, SEW =3D 16, LMUL =3D 1/8 + * =3D> VLMAX =3D vlen >> (1 + 3 - (-3)) + * =3D 256 >> 7 + * =3D 2 */ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) { - uint8_t sew, lmul; - - sew =3D FIELD_EX64(vtype, VTYPE, VSEW); - lmul =3D FIELD_EX64(vtype, VTYPE, VLMUL); + uint8_t sew =3D FIELD_EX64(vtype, VTYPE, VSEW); + int8_t lmul =3D sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); return cpu->cfg.vlen >> (sew + 3 - lmul); } =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1b31d0ad47..10f3baba53 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -75,12 +75,22 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ul= ong *pc, *cs_base =3D 0; =20 if (riscv_has_ext(env, RVV)) { + /* + * If env->vl equals to VLMAX, we can use generic vector operation + * expanders (GVEC) to accerlate the vector operations. + * However, as LMUL could be a fractional number. The maximum + * vector size can be operated might be less than 8 bytes, + * which is not supported by GVEC. So we set vl_eq_vlmax flag to t= rue + * only when maxsz >=3D 8 bytes. + */ uint32_t vlmax =3D vext_get_vlmax(env_archcpu(env), env->vtype); - bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl); + uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t maxsz =3D vlmax << sew; + bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) && + (maxsz >=3D 8); flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, FIELD_EX64(env->vtype, VTYPE, VILL)); - flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, - FIELD_EX64(env->vtype, VTYPE, VSEW)); + flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, sew); flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, FIELD_EX64(env->vtype, VTYPE, VLMUL)); flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index e12db9aae8..5c04ac90da 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1049,7 +1049,17 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true) /* *** Vector Integer Arithmetic Instructions */ -#define MAXSZ(s) (s->vlen >> (3 - s->lmul)) + +/* + * MAXSZ returns the maximum vector size can be operated in bytes, + * which is used in GVEC IR when vl_eq_vlmax flag is set to true + * to accerlate vector operation. + */ +static inline uint32_t MAXSZ(DisasContext *s) +{ + int scale =3D s->lmul - 3; + return scale < 0 ? s->vlen >> -scale : s->vlen << scale; +} =20 static bool opivv_check(DisasContext *s, arg_rmrr *a) { --=20 2.31.1