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[174.21.75.75]) by smtp.gmail.com with ESMTPSA id g19sm10645919pfc.145.2021.12.18.11.42.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Dec 2021 11:42:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=k1PmKhdxec5NltYpxawSaqCtC9T1nkGzqXVscI3MHeI=; b=xXx6a4fOnYGb5Lz51tADCrt+LDCUA2Mn2XN10LRN8kPGS1MZemQ+l0n9l2zFkrG6Vj 4c2/4lwXqXWuo2XZTZS06AUnJXiRSXxSs0a8TIC/Lv3en+Isnk0xHmIHvk1J13WwQKq7 TytLwE0zr05vghf7CY7J9Ko3O9ILK6wjqp+76OEq49S09gsMb25jBo6UhJaeU/GamVqE imRqSgEGPxkvCQdk9BZlZLQDCfs/FLwGtYAbUDLWinPzGc9rxW4KHwRxANzuDYQ5yZIy q3tEmEunltjhuZsrYiigEDsj4Qx3hFDnhfGLXhApQInOy2UBnPah7w4c6J4HWftU0jmo 2P5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=k1PmKhdxec5NltYpxawSaqCtC9T1nkGzqXVscI3MHeI=; b=iEaKmVBMs1P5bYu6UE9WLVuoe8TEbxffwqeI2IF4sajh4L20Ke1FM0eWxGO96sY4vS mG1tQS+zh5wqeL1BBYuZovh0XNp2e6RDozms5eWpvS2GsgDi4UmQJBskT1l9ZF+30jiE nciont4LrOw8yK8dqvYwB2igjxdH2/yiyDx3wIKwLdBOYjH4PrfCn0eJL5kekATobAtf qNMVBd18ffU91rxEoOS5YSg6af0kHYsRyWvI+Lu81y8uAYg4LxWgipqKhQqrTM+FzLuf gs2gk8KXS/Z7u+4yxzZ3TZSc4j7C6ZPdR9BaswMrKsF+UI8Xw5QVGPP/7SKLkKqyK0Wy DuBg== X-Gm-Message-State: AOAM530WCMi9KEdsd+a4upkIx57SAx4bJYAANVZ/l8FnQPS4sx8D2KvN 1lY/xW4wiTRCXSRyk6PG57UtOZCohKHnWg== X-Google-Smtp-Source: ABdhPJy+5ZniaFobziCJf8pTLr42Ap/qlw38ybpAGzJGGjNl0EHcKjQwjxpT9fNmdi81kAF3asZmtQ== X-Received: by 2002:a17:90a:9291:: with SMTP id n17mr10850981pjo.219.1639856579337; Sat, 18 Dec 2021 11:42:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 12/20] tcg/i386: Implement avx512 variable rotate Date: Sat, 18 Dec 2021 11:42:42 -0800 Message-Id: <20211218194250.247633-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211218194250.247633-1-richard.henderson@linaro.org> References: <20211218194250.247633-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1034 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1639857001336100002 Content-Type: text/plain; charset="utf-8" AVX512VL has VPROLVQ and VPRORVQ. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.c.inc | 25 ++++++++++++++++++++++++- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 38c09fd66c..841b1febab 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -197,7 +197,7 @@ extern bool have_movbe; #define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_roti_vec have_avx512vl #define TCG_TARGET_HAS_rots_vec 0 -#define TCG_TARGET_HAS_rotv_vec 0 +#define TCG_TARGET_HAS_rotv_vec have_avx512vl #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 1 #define TCG_TARGET_HAS_shv_vec have_avx2 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 5ab7c4c0fa..7fd6edb887 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -419,6 +419,10 @@ static bool tcg_target_const_match(int64_t val, TCGTyp= e type, int ct) #define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16) #define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW) #define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL) +#define OPC_VPROLVD (0x15 | P_EXT38 | P_DATA16 | P_EVEX) +#define OPC_VPROLVQ (0x15 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) +#define OPC_VPRORVD (0x14 | P_EXT38 | P_DATA16 | P_EVEX) +#define OPC_VPRORVQ (0x14 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) #define OPC_VPSLLVW (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) #define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16) #define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW) @@ -2746,6 +2750,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, static int const umax_insn[4] =3D { OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2 }; + static int const rotlv_insn[4] =3D { + OPC_UD2, OPC_UD2, OPC_VPROLVD, OPC_VPROLVQ + }; + static int const rotrv_insn[4] =3D { + OPC_UD2, OPC_UD2, OPC_VPRORVD, OPC_VPRORVQ + }; static int const shlv_insn[4] =3D { OPC_UD2, OPC_VPSLLVW, OPC_VPSLLVD, OPC_VPSLLVQ }; @@ -2829,6 +2839,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_sarv_vec: insn =3D sarv_insn[vece]; goto gen_simd; + case INDEX_op_rotlv_vec: + insn =3D rotlv_insn[vece]; + goto gen_simd; + case INDEX_op_rotrv_vec: + insn =3D rotrv_insn[vece]; + goto gen_simd; case INDEX_op_shls_vec: insn =3D shls_insn[vece]; goto gen_simd; @@ -3181,6 +3197,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: case INDEX_op_shls_vec: case INDEX_op_shrs_vec: case INDEX_op_sars_vec: @@ -3293,7 +3311,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) return 0; case INDEX_op_rotlv_vec: case INDEX_op_rotrv_vec: - return have_avx2 && vece >=3D MO_32 ? -1 : 0; + switch (vece) { + case MO_32: + case MO_64: + return have_avx512vl ? 1 : have_avx2 ? -1 : 0; + } + return 0; =20 case INDEX_op_mul_vec: if (vece =3D=3D MO_8) { --=20 2.25.1