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[83.50.185.174]) by smtp.gmail.com with ESMTPSA id f13sm12012953wmq.29.2021.12.18.07.10.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Dec 2021 07:10:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1639840262; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MxJO26xUVhJDGKKsrabAkJZAk9ARqJcAEf/XTPsKxI0=; b=gZvmtY6MdOcmjvReoJEfqeTllf0JO19tgkPH8VsSItKRgbiSwt3FSYPBAmpwxuWGf528zB p5o6BW5ryaTAp+88R4Vzqz9rVPqzC5iYPuD2NKJ2IwqJOB+WhEwhj11lcoc5F56/HyZZX0 t66MtXWzN5lf6V4LEMSXQ5DdFM6ZspY= X-MC-Unique: DOxX9_m2OPi1i38k3ZLjrw-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MxJO26xUVhJDGKKsrabAkJZAk9ARqJcAEf/XTPsKxI0=; b=xtaS4SW7leNnec2kpc1h814g86ZsFxFvHeoPwKVNznjSyWQ3lq7hgiM7u5PGa7KEZB qbOS2DpfdlwPOvKwjo10RbHmqFCHuqn35Qro+c71ylnw5PkzJjhTCkF85spq+ijl9Hn/ sUP4X5XdK7X/gLnjX5FCasIXUhWP/kKDs6bJyVpkIHovKZFNRuC9D4BvdrgwHA3XQU5i 1RHeT6O+Wr9OUMkJMA7915kMu4eAkhr+GDjrWP0xsHn+EAgZRYeeKHRK6K0MAq2eayLR P5htSAr3ZHX4dwdRmDz7rrvcLEqmvJDmr8ZcuAXhEhTCNrE6/OlhRvKi5irMPdOr3k4g K7Mw== X-Gm-Message-State: AOAM531gHC3szDz01nObcKeb5aPgJiMKxVZgC3966+55SSgGVwVEQGcc kLbslPBO/CIMwAxuaV3t8HxalUdBQ/6v06RfNP9tVLGws7r9ndWUxZER/t92vYTzfGrYNFZRYwb AHtL7GLvHKDtHZA== X-Received: by 2002:adf:d1ce:: with SMTP id b14mr6388169wrd.704.1639840259744; Sat, 18 Dec 2021 07:10:59 -0800 (PST) X-Google-Smtp-Source: ABdhPJx0rhoPm8iOAl3vcUsVgZF+dwupGSwaQxQN57e4AO14JQDryqY6TgeqBFmIuPY9XpgEGz/UGQ== X-Received: by 2002:adf:d1ce:: with SMTP id b14mr6388158wrd.704.1639840259593; Sat, 18 Dec 2021 07:10:59 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Fam Zheng , "Michael S. Tsirkin" , Sven Schnelle , qemu-block@nongnu.org, Li Qiang , Jason Wang , Stefan Weil , David Hildenbrand , Dmitry Fleytman , Peter Xu , Hannes Reinecke , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Qiuhao Li , Alexander Bulekov , Paolo Bonzini Subject: [PATCH 1/5] hw/scsi/megasas: Use uint32_t for reply queue head/tail values Date: Sat, 18 Dec 2021 16:10:49 +0100 Message-Id: <20211218151053.1545962-2-philmd@redhat.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211218151053.1545962-1-philmd@redhat.com> References: <20211218151053.1545962-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1639840264088100003 While the reply queue values fit in 16-bit, they are accessed as 32-bit: 661: s->reply_queue_head =3D ldl_le_pci_dma(pcid, s->producer_pa); 662: s->reply_queue_head %=3D MEGASAS_MAX_FRAMES; 663: s->reply_queue_tail =3D ldl_le_pci_dma(pcid, s->consumer_pa); 664: s->reply_queue_tail %=3D MEGASAS_MAX_FRAMES; Having: 41:#define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */ In order to update the ld/st*_pci_dma() API to pass the address of the value to access, it is simpler to have the head/tail declared as 32-bit values. Replace the uint16_t by uint32_t, wasting 4 bytes in the MegasasState structure. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Richard Henderson --- hw/scsi/megasas.c | 4 ++-- hw/scsi/trace-events | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c index 066f30e3f22..cf8adf39ca1 100644 --- a/hw/scsi/megasas.c +++ b/hw/scsi/megasas.c @@ -109,8 +109,8 @@ struct MegasasState { uint64_t reply_queue_pa; void *reply_queue; uint16_t reply_queue_len; - uint16_t reply_queue_head; - uint16_t reply_queue_tail; + uint32_t reply_queue_head; + uint32_t reply_queue_tail; uint64_t consumer_pa; uint64_t producer_pa; =20 diff --git a/hw/scsi/trace-events b/hw/scsi/trace-events index 92d5b40f892..ae8551f2797 100644 --- a/hw/scsi/trace-events +++ b/hw/scsi/trace-events @@ -42,18 +42,18 @@ mptsas_config_sas_phy(void *dev, int address, int port,= int phy_handle, int dev_ =20 # megasas.c megasas_init_firmware(uint64_t pa) "pa 0x%" PRIx64 " " -megasas_init_queue(uint64_t queue_pa, int queue_len, uint64_t head, uint64= _t tail, uint32_t flags) "queue at 0x%" PRIx64 " len %d head 0x%" PRIx64 " = tail 0x%" PRIx64 " flags 0x%x" +megasas_init_queue(uint64_t queue_pa, int queue_len, uint32_t head, uint32= _t tail, uint32_t flags) "queue at 0x%" PRIx64 " len %d head 0x%" PRIx32 " = tail 0x%" PRIx32 " flags 0x%x" megasas_initq_map_failed(int frame) "scmd %d: failed to map queue" megasas_initq_mapped(uint64_t pa) "queue already mapped at 0x%" PRIx64 megasas_initq_mismatch(int queue_len, int fw_cmds) "queue size %d max fw c= mds %d" megasas_qf_mapped(unsigned int index) "skip mapped frame 0x%x" megasas_qf_new(unsigned int index, uint64_t frame) "frame 0x%x addr 0x%" P= RIx64 megasas_qf_busy(unsigned long pa) "all frames busy for frame 0x%lx" -megasas_qf_enqueue(unsigned int index, unsigned int count, uint64_t contex= t, unsigned int head, unsigned int tail, int busy) "frame 0x%x count %d con= text 0x%" PRIx64 " head 0x%x tail 0x%x busy %d" -megasas_qf_update(unsigned int head, unsigned int tail, unsigned int busy)= "head 0x%x tail 0x%x busy %d" +megasas_qf_enqueue(unsigned int index, unsigned int count, uint64_t contex= t, uint32_t head, uint32_t tail, unsigned int busy) "frame 0x%x count %d co= ntext 0x%" PRIx64 " head 0x%" PRIx32 " tail 0x%" PRIx32 " busy %u" +megasas_qf_update(uint32_t head, uint32_t tail, unsigned int busy) "head 0= x%" PRIx32 " tail 0x%" PRIx32 " busy %u" megasas_qf_map_failed(int cmd, unsigned long frame) "scmd %d: frame %lu" megasas_qf_complete_noirq(uint64_t context) "context 0x%" PRIx64 " " -megasas_qf_complete(uint64_t context, unsigned int head, unsigned int tail= , int busy) "context 0x%" PRIx64 " head 0x%x tail 0x%x busy %d" +megasas_qf_complete(uint64_t context, uint32_t head, uint32_t tail, int bu= sy) "context 0x%" PRIx64 " head 0x%" PRIx32 " tail 0x%" PRIx32 " busy %u" megasas_frame_busy(uint64_t addr) "frame 0x%" PRIx64 " busy" megasas_unhandled_frame_cmd(int cmd, uint8_t frame_cmd) "scmd %d: MFI cmd = 0x%x" megasas_handle_scsi(const char *frame, int bus, int dev, int lun, void *sd= ev, unsigned long size) "%s dev %x/%x/%x sdev %p xfer %lu" --=20 2.33.1 From nobody Sun Feb 8 20:35:13 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 170.10.133.124 as permitted sender) client-ip=170.10.133.124; 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[83.50.185.174]) by smtp.gmail.com with ESMTPSA id h19sm10834055wmq.0.2021.12.18.07.11.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Dec 2021 07:11:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1639840269; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AGAlxPyEcsvzR3DZ2hxvZ+MjXjPRcaMiHyCHLICfCkI=; b=R7ECEwJlEyMCoeCS8DygZGiIrEzZ8bLdpSOar5gp9EaLS8Xt2VO+a3F4ipRbvLNPGxsGHB PlwxgE0p9Dfzj3rCeB6euSAsjV1rrLnWVmKG7BaqrBFOs/EhEoKocXueozHxGXZsf9ddek 9LDT+/vLeq2NRXRvSRF9aBYW+TMgj5c= X-MC-Unique: PGmQDydZOQWwiPqaCd_KQQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AGAlxPyEcsvzR3DZ2hxvZ+MjXjPRcaMiHyCHLICfCkI=; b=cqbZdGhMIunrfVtymNi6be+u9ys1Vyfz4Vf/ueTpYISPsaFS1nLvWeyBdUqB9rBlES /QcfkTHAMxzp36cUkqX1+bXjiBSTtORVhz+WjyM6AobkyLP7MwvTcCk1GTTNHOAwwhVB FLhA3sN36INuZvStVVKufHMR7x9qa2p6dEBI/LwaKzAbg9boRHc7mL6ZlVSJP3ph76kV bTmmhmDNG4EJOVnMScUQ+3ZYUq8ZYQoPhFxKKn+OvGNkg05H+/tYmTG57GWEFK2ac0km qwYt069I6dDjYLyWbxQ09httG7T3HX+++r4tAa4Hyrnm7jBemAmVtc3H1bWlVWV5hSHG 4t3g== X-Gm-Message-State: AOAM531daC5MqT68rmyV7bbIdjSFVBg/e1IOZRDlXexDTjVEC0Qf6S5i XHEMrQpQRDJ+Ge+o2F+e11scC/mgiYvtDk7N+oOcTbtFQusz+xVxbpO9p880m1Vw5WKyWxmxAHi qmwsSlLeNT9k0jg== X-Received: by 2002:a5d:42c8:: with SMTP id t8mr2553674wrr.369.1639840264695; Sat, 18 Dec 2021 07:11:04 -0800 (PST) X-Google-Smtp-Source: ABdhPJyVcbonj/g9x8/hXip0ziuZ5aoWdu2h5eM68JELiBXzA0r8rmWZVZNhbp3pFj24ZyM2UY5XZw== X-Received: by 2002:a5d:42c8:: with SMTP id t8mr2553646wrr.369.1639840264467; Sat, 18 Dec 2021 07:11:04 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Fam Zheng , "Michael S. Tsirkin" , Sven Schnelle , qemu-block@nongnu.org, Li Qiang , Jason Wang , Stefan Weil , David Hildenbrand , Dmitry Fleytman , Peter Xu , Hannes Reinecke , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Qiuhao Li , Alexander Bulekov , Paolo Bonzini Subject: [PATCH 2/5] dma: Let st*_pci_dma() take MemTxAttrs argument Date: Sat, 18 Dec 2021 16:10:50 +0100 Message-Id: <20211218151053.1545962-3-philmd@redhat.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211218151053.1545962-1-philmd@redhat.com> References: <20211218151053.1545962-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1639840271814100001 Let devices specify transaction attributes when calling st*_pci_dma(). Keep the default MEMTXATTRS_UNSPECIFIED in the few callers. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/pci/pci.h | 11 ++++++----- hw/audio/intel-hda.c | 10 ++++++---- hw/net/eepro100.c | 29 ++++++++++++++++++----------- hw/net/tulip.c | 18 ++++++++++-------- hw/scsi/megasas.c | 15 ++++++++++----- hw/scsi/vmw_pvscsi.c | 3 ++- 6 files changed, 52 insertions(+), 34 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 8c5f2ed5054..9f51ef2c3c2 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -859,11 +859,12 @@ static inline MemTxResult pci_dma_write(PCIDevice *de= v, dma_addr_t addr, MEMTXATTRS_UNSPECIFIED); \ return val; \ } \ - static inline void st##_s##_pci_dma(PCIDevice *dev, \ - dma_addr_t addr, uint##_bits##_t v= al) \ - { \ - st##_s##_dma(pci_get_address_space(dev), addr, val, \ - MEMTXATTRS_UNSPECIFIED); \ + static inline void st##_s##_pci_dma(PCIDevice *dev, \ + dma_addr_t addr, \ + uint##_bits##_t val, \ + MemTxAttrs attrs) \ + { \ + st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \ } =20 PCI_DMA_DEFINE_LDST(ub, b, 8); diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c index fb3d34a4a0c..3309ae0ea18 100644 --- a/hw/audio/intel-hda.c +++ b/hw/audio/intel-hda.c @@ -345,6 +345,7 @@ static void intel_hda_corb_run(IntelHDAState *d) =20 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32= _t response) { + const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; HDACodecBus *bus =3D HDA_BUS(dev->qdev.parent_bus); IntelHDAState *d =3D container_of(bus, IntelHDAState, codecs); hwaddr addr; @@ -367,8 +368,8 @@ static void intel_hda_response(HDACodecDevice *dev, boo= l solicited, uint32_t res ex =3D (solicited ? 0 : (1 << 4)) | dev->cad; wp =3D (d->rirb_wp + 1) & 0xff; addr =3D intel_hda_addr(d->rirb_lbase, d->rirb_ubase); - stl_le_pci_dma(&d->pci, addr + 8*wp, response); - stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex); + stl_le_pci_dma(&d->pci, addr + 8 * wp, response, attrs); + stl_le_pci_dma(&d->pci, addr + 8 * wp + 4, ex, attrs); d->rirb_wp =3D wp; =20 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", @@ -394,6 +395,7 @@ static void intel_hda_response(HDACodecDevice *dev, boo= l solicited, uint32_t res static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, uint8_t *buf, uint32_t len) { + const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; HDACodecBus *bus =3D HDA_BUS(dev->qdev.parent_bus); IntelHDAState *d =3D container_of(bus, IntelHDAState, codecs); hwaddr addr; @@ -428,7 +430,7 @@ static bool intel_hda_xfer(HDACodecDevice *dev, uint32_= t stnr, bool output, st->be, st->bp, st->bpl[st->be].len, copy); =20 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !out= put, - MEMTXATTRS_UNSPECIFIED); + attrs); st->lpib +=3D copy; st->bp +=3D copy; buf +=3D copy; @@ -451,7 +453,7 @@ static bool intel_hda_xfer(HDACodecDevice *dev, uint32_= t stnr, bool output, if (d->dp_lbase & 0x01) { s =3D st - d->st; addr =3D intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase); - stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib); + stl_le_pci_dma(&d->pci, addr + 8 * s, st->lpib, attrs); } dprint(d, 3, "dma: --\n"); =20 diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c index 16e95ef9cc9..83c4431b1ad 100644 --- a/hw/net/eepro100.c +++ b/hw/net/eepro100.c @@ -700,6 +700,8 @@ static void set_ru_state(EEPRO100State * s, ru_state_t = state) =20 static void dump_statistics(EEPRO100State * s) { + const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; + /* Dump statistical data. Most data is never changed by the emulation * and always 0, so we first just copy the whole block and then those * values which really matter. @@ -707,16 +709,18 @@ static void dump_statistics(EEPRO100State * s) */ pci_dma_write(&s->dev, s->statsaddr, &s->statistics, s->stats_size); stl_le_pci_dma(&s->dev, s->statsaddr + 0, - s->statistics.tx_good_frames); + s->statistics.tx_good_frames, attrs); stl_le_pci_dma(&s->dev, s->statsaddr + 36, - s->statistics.rx_good_frames); + s->statistics.rx_good_frames, attrs); stl_le_pci_dma(&s->dev, s->statsaddr + 48, - s->statistics.rx_resource_errors); + s->statistics.rx_resource_errors, attrs); stl_le_pci_dma(&s->dev, s->statsaddr + 60, - s->statistics.rx_short_frame_errors); + s->statistics.rx_short_frame_errors, attrs); #if 0 - stw_le_pci_dma(&s->dev, s->statsaddr + 76, s->statistics.xmt_tco_frame= s); - stw_le_pci_dma(&s->dev, s->statsaddr + 78, s->statistics.rcv_tco_frame= s); + stw_le_pci_dma(&s->dev, s->statsaddr + 76, + s->statistics.xmt_tco_frames, attrs); + stw_le_pci_dma(&s->dev, s->statsaddr + 78, + s->statistics.rcv_tco_frames, attrs); missing("CU dump statistical counters"); #endif } @@ -833,6 +837,7 @@ static void set_multicast_list(EEPRO100State *s) =20 static void action_command(EEPRO100State *s) { + const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; /* The loop below won't stop if it gets special handcrafted data. Therefore we limit the number of iterations. */ unsigned max_loop_count =3D 16; @@ -911,7 +916,7 @@ static void action_command(EEPRO100State *s) } /* Write new status. */ stw_le_pci_dma(&s->dev, s->cb_address, - s->tx.status | ok_status | STATUS_C); + s->tx.status | ok_status | STATUS_C, attrs); if (bit_i) { /* CU completed action. */ eepro100_cx_interrupt(s); @@ -937,6 +942,7 @@ static void action_command(EEPRO100State *s) =20 static void eepro100_cu_command(EEPRO100State * s, uint8_t val) { + const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; cu_state_t cu_state; switch (val) { case CU_NOP: @@ -986,7 +992,7 @@ static void eepro100_cu_command(EEPRO100State * s, uint= 8_t val) /* Dump statistical counters. */ TRACE(OTHER, logout("val=3D0x%02x (dump stats)\n", val)); dump_statistics(s); - stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa005); + stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa005, attr= s); break; case CU_CMD_BASE: /* Load CU base. */ @@ -997,7 +1003,7 @@ static void eepro100_cu_command(EEPRO100State * s, uin= t8_t val) /* Dump and reset statistical counters. */ TRACE(OTHER, logout("val=3D0x%02x (dump stats and reset)\n", val)); dump_statistics(s); - stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa007); + stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa007, attr= s); memset(&s->statistics, 0, sizeof(s->statistics)); break; case CU_SRESUME: @@ -1612,6 +1618,7 @@ static ssize_t nic_receive(NetClientState *nc, const = uint8_t * buf, size_t size) * - Magic packets should set bit 30 in power management driver regist= er. * - Interesting packets should set bit 29 in power management driver = register. */ + const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; EEPRO100State *s =3D qemu_get_nic_opaque(nc); uint16_t rfd_status =3D 0xa000; #if defined(CONFIG_PAD_RECEIVED_FRAMES) @@ -1726,9 +1733,9 @@ static ssize_t nic_receive(NetClientState *nc, const = uint8_t * buf, size_t size) TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u= \n", rfd_command, rx.link, rx.rx_buf_addr, rfd_size)); stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset + - offsetof(eepro100_rx_t, status), rfd_status); + offsetof(eepro100_rx_t, status), rfd_status, attrs); stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset + - offsetof(eepro100_rx_t, count), size); + offsetof(eepro100_rx_t, count), size, attrs); /* Early receive interrupt not supported. */ #if 0 eepro100_er_interrupt(s); diff --git a/hw/net/tulip.c b/hw/net/tulip.c index ca69f7ea5e1..1f2c79dd58b 100644 --- a/hw/net/tulip.c +++ b/hw/net/tulip.c @@ -86,16 +86,18 @@ static void tulip_desc_read(TULIPState *s, hwaddr p, static void tulip_desc_write(TULIPState *s, hwaddr p, struct tulip_descriptor *desc) { + const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; + if (s->csr[0] & CSR0_DBO) { - stl_be_pci_dma(&s->dev, p, desc->status); - stl_be_pci_dma(&s->dev, p + 4, desc->control); - stl_be_pci_dma(&s->dev, p + 8, desc->buf_addr1); - stl_be_pci_dma(&s->dev, p + 12, desc->buf_addr2); + stl_be_pci_dma(&s->dev, p, desc->status, attrs); + stl_be_pci_dma(&s->dev, p + 4, desc->control, attrs); + stl_be_pci_dma(&s->dev, p + 8, desc->buf_addr1, attrs); + stl_be_pci_dma(&s->dev, p + 12, desc->buf_addr2, attrs); } else { - stl_le_pci_dma(&s->dev, p, desc->status); - stl_le_pci_dma(&s->dev, p + 4, desc->control); - stl_le_pci_dma(&s->dev, p + 8, desc->buf_addr1); - stl_le_pci_dma(&s->dev, p + 12, desc->buf_addr2); + stl_le_pci_dma(&s->dev, p, desc->status, attrs); + stl_le_pci_dma(&s->dev, p + 4, desc->control, attrs); + stl_le_pci_dma(&s->dev, p + 8, desc->buf_addr1, attrs); + stl_le_pci_dma(&s->dev, p + 12, desc->buf_addr2, attrs); } } =20 diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c index cf8adf39ca1..bcf8de9aa19 100644 --- a/hw/scsi/megasas.c +++ b/hw/scsi/megasas.c @@ -168,14 +168,16 @@ static void megasas_frame_set_cmd_status(MegasasState= *s, unsigned long frame, uint8_t v) { PCIDevice *pci =3D &s->parent_obj; - stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, cmd_status)= , v); + stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, cmd_status), + v, MEMTXATTRS_UNSPECIFIED); } =20 static void megasas_frame_set_scsi_status(MegasasState *s, unsigned long frame, uint8_t v) { PCIDevice *pci =3D &s->parent_obj; - stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, scsi_status= ), v); + stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, scsi_status= ), + v, MEMTXATTRS_UNSPECIFIED); } =20 static inline const char *mfi_frame_desc(unsigned int cmd) @@ -530,6 +532,7 @@ static MegasasCmd *megasas_enqueue_frame(MegasasState *= s, =20 static void megasas_complete_frame(MegasasState *s, uint64_t context) { + const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; PCIDevice *pci_dev =3D PCI_DEVICE(s); int tail, queue_offset; =20 @@ -543,10 +546,12 @@ static void megasas_complete_frame(MegasasState *s, u= int64_t context) */ if (megasas_use_queue64(s)) { queue_offset =3D s->reply_queue_head * sizeof(uint64_t); - stq_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, cont= ext); + stq_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, + context, attrs); } else { queue_offset =3D s->reply_queue_head * sizeof(uint32_t); - stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, cont= ext); + stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, + context, attrs); } s->reply_queue_tail =3D ldl_le_pci_dma(pci_dev, s->consumer_pa); trace_megasas_qf_complete(context, s->reply_queue_head, @@ -560,7 +565,7 @@ static void megasas_complete_frame(MegasasState *s, uin= t64_t context) s->reply_queue_head =3D megasas_next_index(s, tail, s->fw_cmds); trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail, s->busy); - stl_le_pci_dma(pci_dev, s->producer_pa, s->reply_queue_head); + stl_le_pci_dma(pci_dev, s->producer_pa, s->reply_queue_head, attrs= ); /* Notify HBA */ if (msix_enabled(pci_dev)) { trace_megasas_msix_raise(0); diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index cd76bd67ab7..59c3e8ba048 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -55,7 +55,8 @@ (m)->rs_pa + offsetof(struct PVSCSIRingsState, field))) #define RS_SET_FIELD(m, field, val) \ (stl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \ - (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), va= l)) + (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), va= l, \ + MEMTXATTRS_UNSPECIFIED)) =20 struct PVSCSIClass { PCIDeviceClass parent_class; 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Tsirkin" , Sven Schnelle , qemu-block@nongnu.org, Li Qiang , Jason Wang , Stefan Weil , David Hildenbrand , Dmitry Fleytman , Peter Xu , Hannes Reinecke , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Qiuhao Li , Alexander Bulekov , Paolo Bonzini Subject: [PATCH 3/5] dma: Let ld*_pci_dma() take MemTxAttrs argument Date: Sat, 18 Dec 2021 16:10:51 +0100 Message-Id: <20211218151053.1545962-4-philmd@redhat.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211218151053.1545962-1-philmd@redhat.com> References: <20211218151053.1545962-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1639840276567100001 Let devices specify transaction attributes when calling ld*_pci_dma(). Keep the default MEMTXATTRS_UNSPECIFIED in the few callers. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/pci/pci.h | 6 +++--- hw/audio/intel-hda.c | 2 +- hw/net/eepro100.c | 19 +++++++++++++------ hw/net/tulip.c | 18 ++++++++++-------- hw/scsi/megasas.c | 16 ++++++++++------ hw/scsi/mptsas.c | 10 ++++++---- hw/scsi/vmw_pvscsi.c | 3 ++- hw/usb/hcd-xhci.c | 1 + 8 files changed, 46 insertions(+), 29 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 9f51ef2c3c2..7a46c1fa226 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -852,11 +852,11 @@ static inline MemTxResult pci_dma_write(PCIDevice *de= v, dma_addr_t addr, =20 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ - dma_addr_t addr) \ + dma_addr_t addr, \ + MemTxAttrs attrs) \ { \ uint##_bits##_t val; \ - ld##_l##_dma(pci_get_address_space(dev), addr, &val, \ - MEMTXATTRS_UNSPECIFIED); \ + ld##_l##_dma(pci_get_address_space(dev), addr, &val, attrs); \ return val; \ } \ static inline void st##_s##_pci_dma(PCIDevice *dev, \ diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c index 3309ae0ea18..e34b7ab0e92 100644 --- a/hw/audio/intel-hda.c +++ b/hw/audio/intel-hda.c @@ -335,7 +335,7 @@ static void intel_hda_corb_run(IntelHDAState *d) =20 rp =3D (d->corb_rp + 1) & 0xff; addr =3D intel_hda_addr(d->corb_lbase, d->corb_ubase); - verb =3D ldl_le_pci_dma(&d->pci, addr + 4*rp); + verb =3D ldl_le_pci_dma(&d->pci, addr + 4 * rp, MEMTXATTRS_UNSPECI= FIED); d->corb_rp =3D rp; =20 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __func__, rp, verb); diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c index 83c4431b1ad..eb82e9cb118 100644 --- a/hw/net/eepro100.c +++ b/hw/net/eepro100.c @@ -737,6 +737,7 @@ static void read_cb(EEPRO100State *s) =20 static void tx_command(EEPRO100State *s) { + const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; uint32_t tbd_array =3D s->tx.tbd_array_addr; uint16_t tcb_bytes =3D s->tx.tcb_bytes & 0x3fff; /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes.= */ @@ -772,11 +773,14 @@ static void tx_command(EEPRO100State *s) /* Extended Flexible TCB. */ for (; tbd_count < 2; tbd_count++) { uint32_t tx_buffer_address =3D ldl_le_pci_dma(&s->dev, - tbd_address); + tbd_address, + attrs); uint16_t tx_buffer_size =3D lduw_le_pci_dma(&s->dev, - tbd_address + 4); + tbd_address + 4, + attrs); uint16_t tx_buffer_el =3D lduw_le_pci_dma(&s->dev, - tbd_address + 6); + tbd_address + 6, + attrs); tbd_address +=3D 8; TRACE(RXTX, logout ("TBD (extended flexible mode): buffer address 0x%08x,= size 0x%04x\n", @@ -792,9 +796,12 @@ static void tx_command(EEPRO100State *s) } tbd_address =3D tbd_array; for (; tbd_count < s->tx.tbd_count; tbd_count++) { - uint32_t tx_buffer_address =3D ldl_le_pci_dma(&s->dev, tbd_add= ress); - uint16_t tx_buffer_size =3D lduw_le_pci_dma(&s->dev, tbd_addre= ss + 4); - uint16_t tx_buffer_el =3D lduw_le_pci_dma(&s->dev, tbd_address= + 6); + uint32_t tx_buffer_address =3D ldl_le_pci_dma(&s->dev, tbd_add= ress, + attrs); + uint16_t tx_buffer_size =3D lduw_le_pci_dma(&s->dev, tbd_addre= ss + 4, + attrs); + uint16_t tx_buffer_el =3D lduw_le_pci_dma(&s->dev, tbd_address= + 6, + attrs); tbd_address +=3D 8; TRACE(RXTX, logout ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\= n", diff --git a/hw/net/tulip.c b/hw/net/tulip.c index 1f2c79dd58b..c76e4868f73 100644 --- a/hw/net/tulip.c +++ b/hw/net/tulip.c @@ -70,16 +70,18 @@ static const VMStateDescription vmstate_pci_tulip =3D { static void tulip_desc_read(TULIPState *s, hwaddr p, struct tulip_descriptor *desc) { + const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; + if (s->csr[0] & CSR0_DBO) { - desc->status =3D ldl_be_pci_dma(&s->dev, p); - desc->control =3D ldl_be_pci_dma(&s->dev, p + 4); - desc->buf_addr1 =3D ldl_be_pci_dma(&s->dev, p + 8); - desc->buf_addr2 =3D ldl_be_pci_dma(&s->dev, p + 12); + desc->status =3D ldl_be_pci_dma(&s->dev, p, attrs); + desc->control =3D ldl_be_pci_dma(&s->dev, p + 4, attrs); + desc->buf_addr1 =3D ldl_be_pci_dma(&s->dev, p + 8, attrs); + desc->buf_addr2 =3D ldl_be_pci_dma(&s->dev, p + 12, attrs); } else { - desc->status =3D ldl_le_pci_dma(&s->dev, p); - desc->control =3D ldl_le_pci_dma(&s->dev, p + 4); - desc->buf_addr1 =3D ldl_le_pci_dma(&s->dev, p + 8); - desc->buf_addr2 =3D ldl_le_pci_dma(&s->dev, p + 12); + desc->status =3D ldl_le_pci_dma(&s->dev, p, attrs); + desc->control =3D ldl_le_pci_dma(&s->dev, p + 4, attrs); + desc->buf_addr1 =3D ldl_le_pci_dma(&s->dev, p + 8, attrs); + desc->buf_addr2 =3D ldl_le_pci_dma(&s->dev, p + 12, attrs); } } =20 diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c index bcf8de9aa19..d6b452f07ce 100644 --- a/hw/scsi/megasas.c +++ b/hw/scsi/megasas.c @@ -202,7 +202,9 @@ static uint64_t megasas_frame_get_context(MegasasState = *s, unsigned long frame) { PCIDevice *pci =3D &s->parent_obj; - return ldq_le_pci_dma(pci, frame + offsetof(struct mfi_frame_header, c= ontext)); + return ldq_le_pci_dma(pci, + frame + offsetof(struct mfi_frame_header, contex= t), + MEMTXATTRS_UNSPECIFIED); } =20 static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd) @@ -522,7 +524,8 @@ static MegasasCmd *megasas_enqueue_frame(MegasasState *= s, s->busy++; =20 if (s->consumer_pa) { - s->reply_queue_tail =3D ldl_le_pci_dma(pcid, s->consumer_pa); + s->reply_queue_tail =3D ldl_le_pci_dma(pcid, s->consumer_pa, + MEMTXATTRS_UNSPECIFIED); } trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context, s->reply_queue_head, s->reply_queue_tail, s->= busy); @@ -553,14 +556,14 @@ static void megasas_complete_frame(MegasasState *s, u= int64_t context) stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context, attrs); } - s->reply_queue_tail =3D ldl_le_pci_dma(pci_dev, s->consumer_pa); + s->reply_queue_tail =3D ldl_le_pci_dma(pci_dev, s->consumer_pa, at= trs); trace_megasas_qf_complete(context, s->reply_queue_head, s->reply_queue_tail, s->busy); } =20 if (megasas_intr_enabled(s)) { /* Update reply queue pointer */ - s->reply_queue_tail =3D ldl_le_pci_dma(pci_dev, s->consumer_pa); + s->reply_queue_tail =3D ldl_le_pci_dma(pci_dev, s->consumer_pa, at= trs); tail =3D s->reply_queue_head; s->reply_queue_head =3D megasas_next_index(s, tail, s->fw_cmds); trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail, @@ -625,6 +628,7 @@ static void megasas_abort_command(MegasasCmd *cmd) =20 static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd) { + const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; PCIDevice *pcid =3D PCI_DEVICE(s); uint32_t pa_hi, pa_lo; hwaddr iq_pa, initq_size =3D sizeof(struct mfi_init_qinfo); @@ -663,9 +667,9 @@ static int megasas_init_firmware(MegasasState *s, Megas= asCmd *cmd) pa_lo =3D le32_to_cpu(initq->pi_addr_lo); pa_hi =3D le32_to_cpu(initq->pi_addr_hi); s->producer_pa =3D ((uint64_t) pa_hi << 32) | pa_lo; - s->reply_queue_head =3D ldl_le_pci_dma(pcid, s->producer_pa); + s->reply_queue_head =3D ldl_le_pci_dma(pcid, s->producer_pa, attrs); s->reply_queue_head %=3D MEGASAS_MAX_FRAMES; - s->reply_queue_tail =3D ldl_le_pci_dma(pcid, s->consumer_pa); + s->reply_queue_tail =3D ldl_le_pci_dma(pcid, s->consumer_pa, attrs); s->reply_queue_tail %=3D MEGASAS_MAX_FRAMES; flags =3D le32_to_cpu(initq->flags); if (flags & MFI_QUEUE_FLAG_CONTEXT64) { diff --git a/hw/scsi/mptsas.c b/hw/scsi/mptsas.c index f6c77655443..ac9f4dfcd2a 100644 --- a/hw/scsi/mptsas.c +++ b/hw/scsi/mptsas.c @@ -172,14 +172,15 @@ static const int mpi_request_sizes[] =3D { static dma_addr_t mptsas_ld_sg_base(MPTSASState *s, uint32_t flags_and_len= gth, dma_addr_t *sgaddr) { + const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; PCIDevice *pci =3D (PCIDevice *) s; dma_addr_t addr; =20 if (flags_and_length & MPI_SGE_FLAGS_64_BIT_ADDRESSING) { - addr =3D ldq_le_pci_dma(pci, *sgaddr + 4); + addr =3D ldq_le_pci_dma(pci, *sgaddr + 4, attrs); *sgaddr +=3D 12; } else { - addr =3D ldl_le_pci_dma(pci, *sgaddr + 4); + addr =3D ldl_le_pci_dma(pci, *sgaddr + 4, attrs); *sgaddr +=3D 8; } return addr; @@ -203,7 +204,7 @@ static int mptsas_build_sgl(MPTSASState *s, MPTSASReque= st *req, hwaddr addr) dma_addr_t addr, len; uint32_t flags_and_length; =20 - flags_and_length =3D ldl_le_pci_dma(pci, sgaddr); + flags_and_length =3D ldl_le_pci_dma(pci, sgaddr, MEMTXATTRS_UNSPEC= IFIED); len =3D flags_and_length & MPI_SGE_LENGTH_MASK; if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK) !=3D MPI_SGE_FLAGS_SIMPLE_ELEMENT || @@ -234,7 +235,8 @@ static int mptsas_build_sgl(MPTSASState *s, MPTSASReque= st *req, hwaddr addr) break; } =20 - flags_and_length =3D ldl_le_pci_dma(pci, next_chain_addr); + flags_and_length =3D ldl_le_pci_dma(pci, next_chain_addr, + MEMTXATTRS_UNSPECIFIED); if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK) !=3D MPI_SGE_FLAGS_CHAIN_ELEMENT) { return MPI_IOCSTATUS_INVALID_SGL; diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index 59c3e8ba048..33e16f91116 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -52,7 +52,8 @@ =20 #define RS_GET_FIELD(m, field) \ (ldl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \ - (m)->rs_pa + offsetof(struct PVSCSIRingsState, field))) + (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), \ + MEMTXATTRS_UNSPECIFIED)) #define RS_SET_FIELD(m, field, val) \ (stl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \ (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), va= l, \ diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index da5a4072107..14bdb896768 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -3440,6 +3440,7 @@ static int usb_xhci_post_load(void *opaque, int versi= on_id) } ldq_le_dma(xhci->as, dcbaap + 8 * slotid, &addr, MEMTXATTRS_UNSPEC= IFIED); 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Tsirkin" , Sven Schnelle , qemu-block@nongnu.org, Li Qiang , Jason Wang , Stefan Weil , David Hildenbrand , Dmitry Fleytman , Peter Xu , Hannes Reinecke , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Qiuhao Li , Alexander Bulekov , Paolo Bonzini Subject: [PATCH 4/5] dma: Let st*_pci_dma() propagate MemTxResult Date: Sat, 18 Dec 2021 16:10:52 +0100 Message-Id: <20211218151053.1545962-5-philmd@redhat.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211218151053.1545962-1-philmd@redhat.com> References: <20211218151053.1545962-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1639840281471100001 st*_dma() returns a MemTxResult type. Do not discard it, return it to the caller. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/pci/pci.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 7a46c1fa226..c90cecc85c0 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -859,12 +859,12 @@ static inline MemTxResult pci_dma_write(PCIDevice *de= v, dma_addr_t addr, ld##_l##_dma(pci_get_address_space(dev), addr, &val, attrs); \ return val; \ } \ - static inline void st##_s##_pci_dma(PCIDevice *dev, \ - dma_addr_t addr, \ - uint##_bits##_t val, \ - MemTxAttrs attrs) \ + static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \ + dma_addr_t addr, \ + uint##_bits##_t val, \ + MemTxAttrs attrs) \ { \ - st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \ + return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs);= \ } =20 PCI_DMA_DEFINE_LDST(ub, b, 8); --=20 2.33.1 From nobody Sun Feb 8 20:35:13 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 170.10.129.124 as permitted sender) client-ip=170.10.129.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 170.10.129.124 as permitted sender) smtp.mailfrom=philmd@redhat.com; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1639840284; cv=none; d=zohomail.com; s=zohoarc; b=RwtDO6tBN2gRTFOntUBhV6+zu5kRIVlH9meOfurKA9f+DlElDqy+ol8N/+/eRs0IcqQdaT8FS5rBGWgwMD+M42P7G5LPO7zP7qzYebWcFWGIHyiGAZKAmgiTZtNnALvhQ4wcZArrlJZ4OEr3p6QIIGyso9Umj/E2XwwAt+HahAs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1639840284; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=ySVACGYui79gMf/JcZw7jEE6BTAc/TMij5gruVg6yNk=; b=mUfyN8WhMFsWo3zKm7CqpdPKR7UsBhKdQpYkr9GS1kDVf4xvodTgz+qDHnQZd4olpkIf1aXhXvBqVzciTmm9fZC5wcgMFTFSAPsjszOBA8hyzWvKf9YnFMVNrOJUXjUaMePaoDab8mm2qfEwZKfI67uz5iybik6ojAEV8Gn6FlU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 170.10.129.124 as permitted sender) smtp.mailfrom=philmd@redhat.com; dmarc=pass header.from= (p=none dis=none) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mx.zohomail.com with SMTPS id 1639840284853301.2415934660337; Sat, 18 Dec 2021 07:11:24 -0800 (PST) Received: from mail-wr1-f69.google.com (mail-wr1-f69.google.com [209.85.221.69]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-401-AaYRhCtxNM6S98FZdj8ERg-1; Sat, 18 Dec 2021 10:11:20 -0500 Received: by mail-wr1-f69.google.com with SMTP id r7-20020adfbb07000000b001a254645f13so1459807wrg.7 for ; Sat, 18 Dec 2021 07:11:20 -0800 (PST) Return-Path: Return-Path: Received: from x1w.. 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Tsirkin" , Sven Schnelle , qemu-block@nongnu.org, Li Qiang , Jason Wang , Stefan Weil , David Hildenbrand , Dmitry Fleytman , Peter Xu , Hannes Reinecke , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Qiuhao Li , Alexander Bulekov , Paolo Bonzini Subject: [PATCH 5/5] dma: Let ld*_pci_dma() propagate MemTxResult Date: Sat, 18 Dec 2021 16:10:53 +0100 Message-Id: <20211218151053.1545962-6-philmd@redhat.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211218151053.1545962-1-philmd@redhat.com> References: <20211218151053.1545962-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1639840286024100001 ld*_dma() returns a MemTxResult type. Do not discard it, return it to the caller. Update the few callers. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/pci/pci.h | 17 ++++++++--------- hw/audio/intel-hda.c | 2 +- hw/net/eepro100.c | 25 ++++++++++--------------- hw/net/tulip.c | 16 ++++++++-------- hw/scsi/megasas.c | 21 ++++++++++++--------- hw/scsi/mptsas.c | 16 +++++++++++----- hw/scsi/vmw_pvscsi.c | 16 ++++++++++------ 7 files changed, 60 insertions(+), 53 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index c90cecc85c0..5b36334a28a 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -850,15 +850,14 @@ static inline MemTxResult pci_dma_write(PCIDevice *de= v, dma_addr_t addr, DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED); } =20 -#define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ - static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ - dma_addr_t addr, \ - MemTxAttrs attrs) \ - { \ - uint##_bits##_t val; \ - ld##_l##_dma(pci_get_address_space(dev), addr, &val, attrs); \ - return val; \ - } \ +#define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ + static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \ + dma_addr_t addr, \ + uint##_bits##_t *val, \ + MemTxAttrs attrs) \ + { \ + return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs);= \ + } \ static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \ dma_addr_t addr, \ uint##_bits##_t val, \ diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c index e34b7ab0e92..2b55d521503 100644 --- a/hw/audio/intel-hda.c +++ b/hw/audio/intel-hda.c @@ -335,7 +335,7 @@ static void intel_hda_corb_run(IntelHDAState *d) =20 rp =3D (d->corb_rp + 1) & 0xff; addr =3D intel_hda_addr(d->corb_lbase, d->corb_ubase); - verb =3D ldl_le_pci_dma(&d->pci, addr + 4 * rp, MEMTXATTRS_UNSPECI= FIED); + ldl_le_pci_dma(&d->pci, addr + 4 * rp, &verb, MEMTXATTRS_UNSPECIFI= ED); d->corb_rp =3D rp; =20 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __func__, rp, verb); diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c index eb82e9cb118..679f52f80f1 100644 --- a/hw/net/eepro100.c +++ b/hw/net/eepro100.c @@ -769,18 +769,16 @@ static void tx_command(EEPRO100State *s) } else { /* Flexible mode. */ uint8_t tbd_count =3D 0; + uint32_t tx_buffer_address; + uint16_t tx_buffer_size; + uint16_t tx_buffer_el; + if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))= ) { /* Extended Flexible TCB. */ for (; tbd_count < 2; tbd_count++) { - uint32_t tx_buffer_address =3D ldl_le_pci_dma(&s->dev, - tbd_address, - attrs); - uint16_t tx_buffer_size =3D lduw_le_pci_dma(&s->dev, - tbd_address + 4, - attrs); - uint16_t tx_buffer_el =3D lduw_le_pci_dma(&s->dev, - tbd_address + 6, - attrs); + ldl_le_pci_dma(&s->dev, tbd_address, &tx_buffer_address, a= ttrs); + lduw_le_pci_dma(&s->dev, tbd_address + 4, &tx_buffer_size,= attrs); + lduw_le_pci_dma(&s->dev, tbd_address + 6, &tx_buffer_el, a= ttrs); tbd_address +=3D 8; TRACE(RXTX, logout ("TBD (extended flexible mode): buffer address 0x%08x,= size 0x%04x\n", @@ -796,12 +794,9 @@ static void tx_command(EEPRO100State *s) } tbd_address =3D tbd_array; for (; tbd_count < s->tx.tbd_count; tbd_count++) { - uint32_t tx_buffer_address =3D ldl_le_pci_dma(&s->dev, tbd_add= ress, - attrs); - uint16_t tx_buffer_size =3D lduw_le_pci_dma(&s->dev, tbd_addre= ss + 4, - attrs); - uint16_t tx_buffer_el =3D lduw_le_pci_dma(&s->dev, tbd_address= + 6, - attrs); + ldl_le_pci_dma(&s->dev, tbd_address, &tx_buffer_address, attrs= ); + lduw_le_pci_dma(&s->dev, tbd_address + 4, &tx_buffer_size, att= rs); + lduw_le_pci_dma(&s->dev, tbd_address + 6, &tx_buffer_el, attrs= ); tbd_address +=3D 8; TRACE(RXTX, logout ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\= n", diff --git a/hw/net/tulip.c b/hw/net/tulip.c index c76e4868f73..d5b6cc5ee69 100644 --- a/hw/net/tulip.c +++ b/hw/net/tulip.c @@ -73,15 +73,15 @@ static void tulip_desc_read(TULIPState *s, hwaddr p, const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; =20 if (s->csr[0] & CSR0_DBO) { - desc->status =3D ldl_be_pci_dma(&s->dev, p, attrs); - desc->control =3D ldl_be_pci_dma(&s->dev, p + 4, attrs); - desc->buf_addr1 =3D ldl_be_pci_dma(&s->dev, p + 8, attrs); - desc->buf_addr2 =3D ldl_be_pci_dma(&s->dev, p + 12, attrs); + ldl_be_pci_dma(&s->dev, p, &desc->status, attrs); + ldl_be_pci_dma(&s->dev, p + 4, &desc->control, attrs); + ldl_be_pci_dma(&s->dev, p + 8, &desc->buf_addr1, attrs); + ldl_be_pci_dma(&s->dev, p + 12, &desc->buf_addr2, attrs); } else { - desc->status =3D ldl_le_pci_dma(&s->dev, p, attrs); - desc->control =3D ldl_le_pci_dma(&s->dev, p + 4, attrs); - desc->buf_addr1 =3D ldl_le_pci_dma(&s->dev, p + 8, attrs); - desc->buf_addr2 =3D ldl_le_pci_dma(&s->dev, p + 12, attrs); + ldl_le_pci_dma(&s->dev, p, &desc->status, attrs); + ldl_le_pci_dma(&s->dev, p + 4, &desc->control, attrs); + ldl_le_pci_dma(&s->dev, p + 8, &desc->buf_addr1, attrs); + ldl_le_pci_dma(&s->dev, p + 12, &desc->buf_addr2, attrs); } } =20 diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c index d6b452f07ce..f523d720959 100644 --- a/hw/scsi/megasas.c +++ b/hw/scsi/megasas.c @@ -202,9 +202,12 @@ static uint64_t megasas_frame_get_context(MegasasState= *s, unsigned long frame) { PCIDevice *pci =3D &s->parent_obj; - return ldq_le_pci_dma(pci, - frame + offsetof(struct mfi_frame_header, contex= t), - MEMTXATTRS_UNSPECIFIED); + uint64_t val; + + ldq_le_pci_dma(pci, frame + offsetof(struct mfi_frame_header, context), + &val, MEMTXATTRS_UNSPECIFIED); + + return val; } =20 static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd) @@ -524,8 +527,8 @@ static MegasasCmd *megasas_enqueue_frame(MegasasState *= s, s->busy++; =20 if (s->consumer_pa) { - s->reply_queue_tail =3D ldl_le_pci_dma(pcid, s->consumer_pa, - MEMTXATTRS_UNSPECIFIED); + ldl_le_pci_dma(pcid, s->consumer_pa, &s->reply_queue_tail, + MEMTXATTRS_UNSPECIFIED); } trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context, s->reply_queue_head, s->reply_queue_tail, s->= busy); @@ -556,14 +559,14 @@ static void megasas_complete_frame(MegasasState *s, u= int64_t context) stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context, attrs); } - s->reply_queue_tail =3D ldl_le_pci_dma(pci_dev, s->consumer_pa, at= trs); + ldl_le_pci_dma(pci_dev, s->consumer_pa, &s->reply_queue_tail, attr= s); trace_megasas_qf_complete(context, s->reply_queue_head, s->reply_queue_tail, s->busy); } =20 if (megasas_intr_enabled(s)) { /* Update reply queue pointer */ - s->reply_queue_tail =3D ldl_le_pci_dma(pci_dev, s->consumer_pa, at= trs); + ldl_le_pci_dma(pci_dev, s->consumer_pa, &s->reply_queue_tail, attr= s); tail =3D s->reply_queue_head; s->reply_queue_head =3D megasas_next_index(s, tail, s->fw_cmds); trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail, @@ -667,9 +670,9 @@ static int megasas_init_firmware(MegasasState *s, Megas= asCmd *cmd) pa_lo =3D le32_to_cpu(initq->pi_addr_lo); pa_hi =3D le32_to_cpu(initq->pi_addr_hi); s->producer_pa =3D ((uint64_t) pa_hi << 32) | pa_lo; - s->reply_queue_head =3D ldl_le_pci_dma(pcid, s->producer_pa, attrs); + ldl_le_pci_dma(pcid, s->producer_pa, &s->reply_queue_head, attrs); s->reply_queue_head %=3D MEGASAS_MAX_FRAMES; - s->reply_queue_tail =3D ldl_le_pci_dma(pcid, s->consumer_pa, attrs); + ldl_le_pci_dma(pcid, s->consumer_pa, &s->reply_queue_tail, attrs); s->reply_queue_tail %=3D MEGASAS_MAX_FRAMES; flags =3D le32_to_cpu(initq->flags); if (flags & MFI_QUEUE_FLAG_CONTEXT64) { diff --git a/hw/scsi/mptsas.c b/hw/scsi/mptsas.c index ac9f4dfcd2a..5181b0c0b0d 100644 --- a/hw/scsi/mptsas.c +++ b/hw/scsi/mptsas.c @@ -177,10 +177,16 @@ static dma_addr_t mptsas_ld_sg_base(MPTSASState *s, u= int32_t flags_and_length, dma_addr_t addr; =20 if (flags_and_length & MPI_SGE_FLAGS_64_BIT_ADDRESSING) { - addr =3D ldq_le_pci_dma(pci, *sgaddr + 4, attrs); + uint64_t addr64; + + ldq_le_pci_dma(pci, *sgaddr + 4, &addr64, attrs); + addr =3D addr64; *sgaddr +=3D 12; } else { - addr =3D ldl_le_pci_dma(pci, *sgaddr + 4, attrs); + uint32_t addr32; + + ldl_le_pci_dma(pci, *sgaddr + 4, &addr32, attrs); + addr =3D addr32; *sgaddr +=3D 8; } return addr; @@ -204,7 +210,7 @@ static int mptsas_build_sgl(MPTSASState *s, MPTSASReque= st *req, hwaddr addr) dma_addr_t addr, len; uint32_t flags_and_length; =20 - flags_and_length =3D ldl_le_pci_dma(pci, sgaddr, MEMTXATTRS_UNSPEC= IFIED); + ldl_le_pci_dma(pci, sgaddr, &flags_and_length, MEMTXATTRS_UNSPECIF= IED); len =3D flags_and_length & MPI_SGE_LENGTH_MASK; if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK) !=3D MPI_SGE_FLAGS_SIMPLE_ELEMENT || @@ -235,8 +241,8 @@ static int mptsas_build_sgl(MPTSASState *s, MPTSASReque= st *req, hwaddr addr) break; } =20 - flags_and_length =3D ldl_le_pci_dma(pci, next_chain_addr, - MEMTXATTRS_UNSPECIFIED); + ldl_le_pci_dma(pci, next_chain_addr, &flags_and_length, + MEMTXATTRS_UNSPECIFIED); if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK) !=3D MPI_SGE_FLAGS_CHAIN_ELEMENT) { return MPI_IOCSTATUS_INVALID_SGL; diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index 33e16f91116..4d9969f3b16 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -50,10 +50,10 @@ #define PVSCSI_MAX_CMD_DATA_WORDS \ (sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t)) =20 -#define RS_GET_FIELD(m, field) \ - (ldl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \ +#define RS_GET_FIELD(pval, m, field) \ + ldl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \ (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), \ - MEMTXATTRS_UNSPECIFIED)) + pval, MEMTXATTRS_UNSPECIFIED) #define RS_SET_FIELD(m, field, val) \ (stl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \ (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), va= l, \ @@ -249,10 +249,11 @@ pvscsi_ring_cleanup(PVSCSIRingInfo *mgr) static hwaddr pvscsi_ring_pop_req_descr(PVSCSIRingInfo *mgr) { - uint32_t ready_ptr =3D RS_GET_FIELD(mgr, reqProdIdx); + uint32_t ready_ptr; uint32_t ring_size =3D PVSCSI_MAX_NUM_PAGES_REQ_RING * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; =20 + RS_GET_FIELD(&ready_ptr, mgr, reqProdIdx); if (ready_ptr !=3D mgr->consumed_ptr && ready_ptr - mgr->consumed_ptr < ring_size) { uint32_t next_ready_ptr =3D @@ -323,8 +324,11 @@ pvscsi_ring_flush_cmp(PVSCSIRingInfo *mgr) static bool pvscsi_ring_msg_has_room(PVSCSIRingInfo *mgr) { - uint32_t prodIdx =3D RS_GET_FIELD(mgr, msgProdIdx); - uint32_t consIdx =3D RS_GET_FIELD(mgr, msgConsIdx); + uint32_t prodIdx; + uint32_t consIdx; + + RS_GET_FIELD(&prodIdx, mgr, msgProdIdx); + RS_GET_FIELD(&consIdx, mgr, msgConsIdx); =20 return (prodIdx - consIdx) < (mgr->msg_len_mask + 1); } --=20 2.33.1