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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 16/33] target/arm: Assert thumb pc is aligned
Date: Wed, 15 Dec 2021 10:40:32 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Misaligned thumb PC is architecturally impossible.
Assert is better than proceeding, in case we've missed
something somewhere.
Expand a comment about aligning the pc in gdbstub.
Fail an incoming migrate if a thumb pc is misaligned.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/gdbstub.c | 9 +++++++--
target/arm/machine.c | 10 ++++++++++
target/arm/translate.c | 3 +++
3 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index 134da0d0ae3..ca1de475116 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -77,8 +77,13 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *me=
m_buf, int n)
=20
tmp =3D ldl_p(mem_buf);
=20
- /* Mask out low bit of PC to workaround gdb bugs. This will probably
- cause problems if we ever implement the Jazelle DBX extensions. */
+ /*
+ * Mask out low bits of PC to workaround gdb bugs.
+ * This avoids an assert in thumb_tr_translate_insn, because it is
+ * architecturally impossible to misalign the pc.
+ * This will probably cause problems if we ever implement the
+ * Jazelle DBX extensions.
+ */
if (n =3D=3D 15) {
tmp &=3D ~1;
}
diff --git a/target/arm/machine.c b/target/arm/machine.c
index c74d8c3f4b3..135d2420b5c 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -794,6 +794,16 @@ static int cpu_post_load(void *opaque, int version_id)
return -1;
}
}
+
+ /*
+ * Misaligned thumb pc is architecturally impossible.
+ * We have an assert in thumb_tr_translate_insn to verify this.
+ * Fail an incoming migrate to avoid this assert.
+ */
+ if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
+ return -1;
+ }
+
if (!kvm_enabled()) {
pmu_op_finish(&cpu->env);
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 45917c3a6d2..0a3840d227f 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9646,6 +9646,9 @@ static void thumb_tr_translate_insn(DisasContextBase =
*dcbase, CPUState *cpu)
uint32_t insn;
bool is_16bit;
=20
+ /* Misaligned thumb PC is architecturally impossible. */
+ assert((dc->base.pc_next & 1) =3D=3D 0);
+
if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
dc->base.pc_next =3D pc + 2;
return;
--=20
2.25.1