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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 15/33] target/arm: Take an exception if PC is misaligned
Date: Wed, 15 Dec 2021 10:40:31 +0000
Message-Id: <20211215104049.2030475-16-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
For A64, any input to an indirect branch can cause this.
For A32, many indirect branch paths force the branch to be aligned,
but BXWritePC does not. This includes the BX instruction but also
other interworking changes to PC. Prior to v8, this case is UNDEFINED.
With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an
exception or force align the PC.
We choose to raise an exception because we have the infrastructure,
it makes the generated code for gen_bx simpler, and it has the
possibility of catching more guest bugs.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.h | 1 +
target/arm/syndrome.h | 5 ++++
linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++++++---------------
target/arm/tlb_helper.c | 18 ++++++++++++++
target/arm/translate-a64.c | 15 ++++++++++++
target/arm/translate.c | 22 ++++++++++++++++-
6 files changed, 87 insertions(+), 20 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 448a86edfdc..b463d9343bc 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -47,6 +47,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
DEF_HELPER_2(exception_internal, void, env, i32)
DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32)
DEF_HELPER_2(exception_bkpt_insn, void, env, i32)
+DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl)
DEF_HELPER_1(setend, void, env)
DEF_HELPER_2(wfi, void, env, i32)
DEF_HELPER_1(wfe, void, env)
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index f30f4130a27..8cde8e7243a 100644
--- a/target/arm/syndrome.h
+++ b/target/arm/syndrome.h
@@ -282,4 +282,9 @@ static inline uint32_t syn_illegalstate(void)
return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL;
}
=20
+static inline uint32_t syn_pcalignment(void)
+{
+ return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
+}
+
#endif /* TARGET_ARM_SYNDROME_H */
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
index 97e0728b679..f9f3473288f 100644
--- a/linux-user/aarch64/cpu_loop.c
+++ b/linux-user/aarch64/cpu_loop.c
@@ -113,27 +113,35 @@ void cpu_loop(CPUARMState *env)
break;
case EXCP_PREFETCH_ABORT:
case EXCP_DATA_ABORT:
- /* We should only arrive here with EC in {DATAABORT, INSNABORT=
}. */
ec =3D syn_get_ec(env->exception.syndrome);
- assert(ec =3D=3D EC_DATAABORT || ec =3D=3D EC_INSNABORT);
-
- /* Both EC have the same format for FSC, or close enough. */
- fsc =3D extract32(env->exception.syndrome, 0, 6);
- switch (fsc) {
- case 0x04 ... 0x07: /* Translation fault, level {0-3} */
- si_signo =3D TARGET_SIGSEGV;
- si_code =3D TARGET_SEGV_MAPERR;
+ switch (ec) {
+ case EC_DATAABORT:
+ case EC_INSNABORT:
+ /* Both EC have the same format for FSC, or close enough. =
*/
+ fsc =3D extract32(env->exception.syndrome, 0, 6);
+ switch (fsc) {
+ case 0x04 ... 0x07: /* Translation fault, level {0-3} */
+ si_signo =3D TARGET_SIGSEGV;
+ si_code =3D TARGET_SEGV_MAPERR;
+ break;
+ case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
+ case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
+ si_signo =3D TARGET_SIGSEGV;
+ si_code =3D TARGET_SEGV_ACCERR;
+ break;
+ case 0x11: /* Synchronous Tag Check Fault */
+ si_signo =3D TARGET_SIGSEGV;
+ si_code =3D TARGET_SEGV_MTESERR;
+ break;
+ case 0x21: /* Alignment fault */
+ si_signo =3D TARGET_SIGBUS;
+ si_code =3D TARGET_BUS_ADRALN;
+ break;
+ default:
+ g_assert_not_reached();
+ }
break;
- case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
- case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
- si_signo =3D TARGET_SIGSEGV;
- si_code =3D TARGET_SEGV_ACCERR;
- break;
- case 0x11: /* Synchronous Tag Check Fault */
- si_signo =3D TARGET_SIGSEGV;
- si_code =3D TARGET_SEGV_MTESERR;
- break;
- case 0x21: /* Alignment fault */
+ case EC_PCALIGNMENT:
si_signo =3D TARGET_SIGBUS;
si_code =3D TARGET_BUS_ADRALN;
break;
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index 4cacb9658fb..b79004e0cca 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -9,6 +9,7 @@
#include "cpu.h"
#include "internals.h"
#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
=20
static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
unsigned int target_el,
@@ -134,6 +135,23 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr v=
addr,
arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
}
=20
+void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc)
+{
+ ARMMMUFaultInfo fi =3D { .type =3D ARMFault_Alignment };
+ int target_el =3D exception_target_el(env);
+ int mmu_idx =3D cpu_mmu_index(env, true);
+ uint32_t fsc;
+
+ env->exception.vaddress =3D pc;
+
+ /*
+ * Note that the fsc is not applicable to this exception,
+ * since any syndrome is pcalignment not insn_abort.
+ */
+ env->exception.fsr =3D compute_fsr_fsc(env, &fi, target_el, mmu_idx, &=
fsc);
+ raise_exception(env, EXCP_PREFETCH_ABORT, syn_pcalignment(), target_el=
);
+}
+
#if !defined(CONFIG_USER_ONLY)
=20
/*
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2986fe13935..130a9ff8d54 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14753,6 +14753,7 @@ static void aarch64_tr_translate_insn(DisasContextB=
ase *dcbase, CPUState *cpu)
uint64_t pc =3D s->base.pc_next;
uint32_t insn;
=20
+ /* Singlestep exceptions have the highest priority. */
if (s->ss_active && !s->pstate_ss) {
/* Singlestep state is Active-pending.
* If we're in this state at the start of a TB then either
@@ -14771,6 +14772,20 @@ static void aarch64_tr_translate_insn(DisasContext=
Base *dcbase, CPUState *cpu)
return;
}
=20
+ if (pc & 3) {
+ /*
+ * PC alignment fault. This has priority over the instruction abo=
rt
+ * that we would receive from a translation fault via arm_ldl_code.
+ * This should only be possible after an indirect branch, at the
+ * start of the TB.
+ */
+ assert(s->base.num_insns =3D=3D 1);
+ gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc));
+ s->base.is_jmp =3D DISAS_NORETURN;
+ s->base.pc_next =3D QEMU_ALIGN_UP(pc, 4);
+ return;
+ }
+
s->pc_curr =3D pc;
insn =3D arm_ldl_code(env, &s->base, pc, s->sctlr_b);
s->insn =3D insn;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0103c75a274..45917c3a6d2 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9555,7 +9555,27 @@ static void arm_tr_translate_insn(DisasContextBase *=
dcbase, CPUState *cpu)
uint32_t pc =3D dc->base.pc_next;
unsigned int insn;
=20
- if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
+ /* Singlestep exceptions have the highest priority. */
+ if (arm_check_ss_active(dc)) {
+ dc->base.pc_next =3D pc + 4;
+ return;
+ }
+
+ if (pc & 3) {
+ /*
+ * PC alignment fault. This has priority over the instruction abo=
rt
+ * that we would receive from a translation fault via arm_ldl_code
+ * (or the execution of the kernelpage entrypoint). This should on=
ly
+ * be possible after an indirect branch, at the start of the TB.
+ */
+ assert(dc->base.num_insns =3D=3D 1);
+ gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc));
+ dc->base.is_jmp =3D DISAS_NORETURN;
+ dc->base.pc_next =3D QEMU_ALIGN_UP(pc, 4);
+ return;
+ }
+
+ if (arm_check_kernelpage(dc)) {
dc->base.pc_next =3D pc + 4;
return;
}
--=20
2.25.1