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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 14/33] target/arm: Split compute_fsr_fsc out of
arm_deliver_fault
Date: Wed, 15 Dec 2021 10:40:30 +0000
Message-Id: <20211215104049.2030475-15-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
We will reuse this section of arm_deliver_fault for
raising pc alignment faults.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tlb_helper.c | 45 +++++++++++++++++++++++++----------------
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index 12a934e9248..4cacb9658fb 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -49,25 +49,11 @@ static inline uint32_t merge_syn_data_abort(uint32_t te=
mplate_syn,
return syn;
}
=20
-static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx, ARMMMUFaultInfo *=
fi)
+static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi,
+ int target_el, int mmu_idx, uint32_t *ret_=
fsc)
{
- CPUARMState *env =3D &cpu->env;
- int target_el;
- bool same_el;
- uint32_t syn, exc, fsr, fsc;
ARMMMUIdx arm_mmu_idx =3D core_to_arm_mmu_idx(env, mmu_idx);
-
- target_el =3D exception_target_el(env);
- if (fi->stage2) {
- target_el =3D 2;
- env->cp15.hpfar_el2 =3D extract64(fi->s2addr, 12, 47) << 4;
- if (arm_is_secure_below_el3(env) && fi->s1ns) {
- env->cp15.hpfar_el2 |=3D HPFAR_NS;
- }
- }
- same_el =3D (arm_current_el(env) =3D=3D target_el);
+ uint32_t fsr, fsc;
=20
if (target_el =3D=3D 2 || arm_el_is_aa64(env, target_el) ||
arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
@@ -88,6 +74,31 @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu,=
vaddr addr,
fsc =3D 0x3f;
}
=20
+ *ret_fsc =3D fsc;
+ return fsr;
+}
+
+static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx, ARMMMUFaultInfo *=
fi)
+{
+ CPUARMState *env =3D &cpu->env;
+ int target_el;
+ bool same_el;
+ uint32_t syn, exc, fsr, fsc;
+
+ target_el =3D exception_target_el(env);
+ if (fi->stage2) {
+ target_el =3D 2;
+ env->cp15.hpfar_el2 =3D extract64(fi->s2addr, 12, 47) << 4;
+ if (arm_is_secure_below_el3(env) && fi->s1ns) {
+ env->cp15.hpfar_el2 |=3D HPFAR_NS;
+ }
+ }
+ same_el =3D (arm_current_el(env) =3D=3D target_el);
+
+ fsr =3D compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc);
+
if (access_type =3D=3D MMU_INST_FETCH) {
syn =3D syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc);
exc =3D EXCP_PREFETCH_ABORT;
--=20
2.25.1