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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 01/33] hw/intc: clean-up error reporting for failed ITS cmd
Date: Wed, 15 Dec 2021 10:40:17 +0000
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From: Alex Benn=C3=A9e <alex.bennee@linaro.org>
While trying to debug a GIC ITS failure I saw some guest errors that
had poor formatting as well as leaving me confused as to what failed.
As most of the checks aren't possible without a valid dte split that
check apart and then check the other conditions in steps. This avoids
us relying on undefined data.
I still get a failure with the current kvm-unit-tests but at least I
know (partially) why now:
Exception return from AArch64 EL1 to AArch64 EL1 PC 0x40080588
PASS: gicv3: its-trigger: inv/invall: dev2/eventid=3D20 now triggers an L=
PI
ITS: MAPD devid=3D2 size =3D 0x8 itt=3D0x40430000 valid=3D0
INT dev_id=3D2 event_id=3D20
process_its_cmd: invalid command attributes: invalid dte: 0 for 2 (MEM_TX=
: 0)
PASS: gicv3: its-trigger: mapd valid=3Dfalse: no LPI after device unmap
SUMMARY: 6 tests, 1 unexpected failures
Signed-off-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20211112170454.3158925-1-alex.bennee@linaro.org
Cc: Shashi Mallela <shashi.mallela@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv3_its.c | 39 +++++++++++++++++++++++++++------------
1 file changed, 27 insertions(+), 12 deletions(-)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index c929a9cb5c3..b99e63d58f7 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -274,21 +274,36 @@ static bool process_its_cmd(GICv3ITSState *s, uint64_=
t value, uint32_t offset,
if (res !=3D MEMTX_OK) {
return result;
}
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid command attributes: "
+ "invalid dte: %"PRIx64" for %d (MEM_TX: %d)\n",
+ __func__, dte, devid, res);
+ return result;
}
=20
- if ((devid > s->dt.maxids.max_devids) || !dte_valid || !ite_valid ||
- !cte_valid || (eventid > max_eventid)) {
+
+ /*
+ * In this implementation, in case of guest errors we ignore the
+ * command and move onto the next command in the queue.
+ */
+ if (devid > s->dt.maxids.max_devids) {
qemu_log_mask(LOG_GUEST_ERROR,
- "%s: invalid command attributes "
- "devid %d or eventid %d or invalid dte %d or"
- "invalid cte %d or invalid ite %d\n",
- __func__, devid, eventid, dte_valid, cte_valid,
- ite_valid);
- /*
- * in this implementation, in case of error
- * we ignore this command and move onto the next
- * command in the queue
- */
+ "%s: invalid command attributes: devid %d>%d",
+ __func__, devid, s->dt.maxids.max_devids);
+
+ } else if (!dte_valid || !ite_valid || !cte_valid) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid command attributes: "
+ "dte: %s, ite: %s, cte: %s\n",
+ __func__,
+ dte_valid ? "valid" : "invalid",
+ ite_valid ? "valid" : "invalid",
+ cte_valid ? "valid" : "invalid");
+ } else if (eventid > max_eventid) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid command attributes: eventid %d > %d\n",
+ __func__, eventid, max_eventid);
} else {
/*
* Current implementation only supports rdbase =3D=3D procnum
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 02/33] docs: aspeed: Add new boards
Date: Wed, 15 Dec 2021 10:40:18 +0000
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X-ZM-MESSAGEID: 1639566785942100001
From: Joel Stanley <joel@jms.id.au>
Add X11, FP5280G2, G220A, Rainier and Fuji. Mention that Swift will be
removed in v7.0.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: C=C3=A9dric Le Goater <clg@kaod.org>
Message-id: 20211117065752.330632-2-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/aspeed.rst | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index cec87e3743d..41a9bd5608e 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -14,6 +14,7 @@ AST2400 SoC based machines :
=20
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
+- ``supermicrox11-bmc`` Supermicro X11 BMC
=20
AST2500 SoC based machines :
=20
@@ -21,12 +22,16 @@ AST2500 SoC based machines :
- ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC
- ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC
- ``sonorapass-bmc`` OCP SonoraPass BMC
-- ``swift-bmc`` OpenPOWER Swift BMC POWER9
+- ``swift-bmc`` OpenPOWER Swift BMC POWER9 (to be removed in v7=
.0)
+- ``fp5280g2-bmc`` Inspur FP5280G2 BMC
+- ``g220a-bmc`` Bytedance G220A BMC
=20
AST2600 SoC based machines :
=20
- ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex-A7)
- ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC
+- ``rainier-bmc`` IBM Rainier POWER10 BMC
+- ``fuji-bmc`` Facebook Fuji BMC
=20
Supported devices
-----------------
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 03/33] docs: aspeed: Update OpenBMC image URL
Date: Wed, 15 Dec 2021 10:40:19 +0000
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From: Joel Stanley <joel@jms.id.au>
This is the latest URL for the OpenBMC CI. The old URL still works, but
redirects.
Reviewed-by: C=C3=A9dric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-id: 20211117065752.330632-3-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/aspeed.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 41a9bd5608e..b87697fcf0b 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -82,7 +82,7 @@ The Aspeed machines can be started using the ``-kernel`` =
option to
load a Linux kernel or from a firmware. Images can be downloaded from
the OpenBMC jenkins :
=20
- https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/distro=
=3Dubuntu,label=3Ddocker-builder
+ https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/
=20
or directly from the OpenBMC GitHub release repository :
=20
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 04/33] docs: aspeed: Give an example of booting a kernel
Date: Wed, 15 Dec 2021 10:40:20 +0000
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From: Joel Stanley <joel@jms.id.au>
A common use case for the ASPEED machine is to boot a Linux kernel.
Provide a full example command line.
Reviewed-by: C=C3=A9dric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-id: 20211117065752.330632-4-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/aspeed.rst | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index b87697fcf0b..6aafd611e9a 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -78,9 +78,9 @@ Missing devices
Boot options
------------
=20
-The Aspeed machines can be started using the ``-kernel`` option to
-load a Linux kernel or from a firmware. Images can be downloaded from
-the OpenBMC jenkins :
+The Aspeed machines can be started using the ``-kernel`` and ``-dtb`` opti=
ons
+to load a Linux kernel or from a firmware. Images can be downloaded from t=
he
+OpenBMC jenkins :
=20
https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/
=20
@@ -88,6 +88,15 @@ or directly from the OpenBMC GitHub release repository :
=20
https://github.com/openbmc/openbmc/releases
=20
+To boot a kernel directly from a Linux build tree:
+
+.. code-block:: bash
+
+ $ qemu-system-arm -M ast2600-evb -nographic \
+ -kernel arch/arm/boot/zImage \
+ -dtb arch/arm/boot/dts/aspeed-ast2600-evb.dtb \
+ -initrd rootfs.cpio
+
The image should be attached as an MTD drive. Run :
=20
.. code-block:: bash
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 05/33] docs: aspeed: ADC is now modelled
Date: Wed, 15 Dec 2021 10:40:21 +0000
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From: Joel Stanley <joel@jms.id.au>
Move it to the supported list.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-id: 20211117065752.330632-5-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/aspeed.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 6aafd611e9a..d8b102fa0ad 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -56,13 +56,13 @@ Supported devices
* Front LEDs (PCA9552 on I2C bus)
* LPC Peripheral Controller (a subset of subdevices are supported)
* Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA
+ * ADC
=20
=20
Missing devices
---------------
=20
* Coprocessor support
- * ADC (out of tree implementation)
* PWM and Fan Controller
* Slave GPIO Controller
* Super I/O Controller
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 06/33] Fix STM32F2XX USART data register readout
Date: Wed, 15 Dec 2021 10:40:22 +0000
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From: Olivier H=C3=A9riveaux <olivier.heriveaux@ledger.fr>
Fix issue where the data register may be overwritten by next character
reception before being read and returned.
Signed-off-by: Olivier H=C3=A9riveaux <olivier.heriveaux@ledger.fr>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211128120723.4053-1-olivier.heriveaux@ledger.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/char/stm32f2xx_usart.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
index 8df0832424c..fde67f4f03f 100644
--- a/hw/char/stm32f2xx_usart.c
+++ b/hw/char/stm32f2xx_usart.c
@@ -103,10 +103,11 @@ static uint64_t stm32f2xx_usart_read(void *opaque, hw=
addr addr,
return retvalue;
case USART_DR:
DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usar=
t_dr);
+ retvalue =3D s->usart_dr & 0x3FF;
s->usart_sr &=3D ~USART_SR_RXNE;
qemu_chr_fe_accept_input(&s->chr);
qemu_set_irq(s->irq, 0);
- return s->usart_dr & 0x3FF;
+ return retvalue;
case USART_BRR:
return s->usart_brr;
case USART_CR1:
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 07/33] hw/intc/arm_gicv3: Extract gicv3_set_gicv3state from
arm_gicv3_cpuif.c
Date: Wed, 15 Dec 2021 10:40:23 +0000
Message-Id: <20211215104049.2030475-8-peter.maydell@linaro.org>
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From: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
gicv3_set_gicv3state() is used by arm_gicv3_common.c in
arm_gicv3_common_realize(). Since we want to restrict
arm_gicv3_cpuif.c to TCG, extract gicv3_set_gicv3state()
to a new file. Add this file to the meson 'specific'
source set, since it needs access to "cpu.h".
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20211115223619.2599282-2-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv3_cpuif.c | 10 +---------
hw/intc/arm_gicv3_cpuif_common.c | 22 ++++++++++++++++++++++
hw/intc/meson.build | 1 +
3 files changed, 24 insertions(+), 9 deletions(-)
create mode 100644 hw/intc/arm_gicv3_cpuif_common.c
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 85fc369e550..d7e03d0cab8 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -1,5 +1,5 @@
/*
- * ARM Generic Interrupt Controller v3
+ * ARM Generic Interrupt Controller v3 (emulation)
*
* Copyright (c) 2016 Linaro Limited
* Written by Peter Maydell
@@ -21,14 +21,6 @@
#include "hw/irq.h"
#include "cpu.h"
=20
-void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
-{
- ARMCPU *arm_cpu =3D ARM_CPU(cpu);
- CPUARMState *env =3D &arm_cpu->env;
-
- env->gicv3state =3D (void *)s;
-};
-
static GICv3CPUState *icc_cs_from_env(CPUARMState *env)
{
return env->gicv3state;
diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/intc/arm_gicv3_cpuif_com=
mon.c
new file mode 100644
index 00000000000..ff1239f65db
--- /dev/null
+++ b/hw/intc/arm_gicv3_cpuif_common.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * ARM Generic Interrupt Controller v3
+ *
+ * Copyright (c) 2016 Linaro Limited
+ * Written by Peter Maydell
+ *
+ * This code is licensed under the GPL, version 2 or (at your option)
+ * any later version.
+ */
+
+#include "qemu/osdep.h"
+#include "gicv3_internal.h"
+#include "cpu.h"
+
+void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
+{
+ ARMCPU *arm_cpu =3D ARM_CPU(cpu);
+ CPUARMState *env =3D &arm_cpu->env;
+
+ env->gicv3state =3D (void *)s;
+};
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index c89d2ca180e..11352806db2 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -25,6 +25,7 @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: f=
iles('xlnx-pmu-iomod-in
=20
specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinne=
r-a10-pic.c'))
specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common=
.c'))
+specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_co=
mmon.c'))
specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c'=
))
specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'=
))
specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: f=
iles('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 08/33] hw/intc/arm_gicv3: Introduce CONFIG_ARM_GIC_TCG Kconfig
selector
Date: Wed, 15 Dec 2021 10:40:24 +0000
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From: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
The TYPE_ARM_GICV3 device is an emulated one. When using
KVM, it is recommended to use the TYPE_KVM_ARM_GICV3 device
(which uses in-kernel support).
When using --with-devices-FOO, it is possible to build a
binary with a specific set of devices. When this binary is
restricted to KVM accelerator, the TYPE_ARM_GICV3 device is
irrelevant, and it is desirable to remove it from the binary.
Therefore introduce the CONFIG_ARM_GIC_TCG Kconfig selector
which select the files required to have the TYPE_ARM_GICV3
device, but also allowing to de-select this device.
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20211115223619.2599282-3-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv3.c | 2 +-
hw/intc/Kconfig | 5 +++++
hw/intc/meson.build | 10 ++++++----
3 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
index 9f5f815db9b..715df5421dd 100644
--- a/hw/intc/arm_gicv3.c
+++ b/hw/intc/arm_gicv3.c
@@ -1,5 +1,5 @@
/*
- * ARM Generic Interrupt Controller v3
+ * ARM Generic Interrupt Controller v3 (emulation)
*
* Copyright (c) 2015 Huawei.
* Copyright (c) 2016 Linaro Limited
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 78aed93c454..010ded7eae0 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -25,6 +25,11 @@ config APIC
select MSI_NONBROKEN
select I8259
=20
+config ARM_GIC_TCG
+ bool
+ default y
+ depends on ARM_GIC && TCG
+
config ARM_GIC_KVM
bool
default y
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 11352806db2..70080bc161c 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -3,12 +3,14 @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files(
'arm_gic.c',
'arm_gic_common.c',
'arm_gicv2m.c',
- 'arm_gicv3.c',
'arm_gicv3_common.c',
- 'arm_gicv3_dist.c',
'arm_gicv3_its_common.c',
- 'arm_gicv3_redist.c',
+))
+softmmu_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files(
+ 'arm_gicv3.c',
+ 'arm_gicv3_dist.c',
'arm_gicv3_its.c',
+ 'arm_gicv3_redist.c',
))
softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c'))
softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c=
'))
@@ -26,7 +28,7 @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: f=
iles('xlnx-pmu-iomod-in
specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinne=
r-a10-pic.c'))
specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common=
.c'))
specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_co=
mmon.c'))
-specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c'=
))
+specific_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files('arm_gicv3_cpui=
f.c'))
specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'=
))
specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: f=
iles('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
--=20
2.25.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 09/33] target/arm: Hoist pc_next to a local variable in
aarch64_tr_translate_insn
Date: Wed, 15 Dec 2021 10:40:25 +0000
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Content-Type: text/plain; charset="utf-8"
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a64.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index cec672f2296..9c4258ccac2 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14750,6 +14750,7 @@ static void aarch64_tr_translate_insn(DisasContextB=
ase *dcbase, CPUState *cpu)
{
DisasContext *s =3D container_of(dcbase, DisasContext, base);
CPUARMState *env =3D cpu->env_ptr;
+ uint64_t pc =3D s->base.pc_next;
uint32_t insn;
=20
if (s->ss_active && !s->pstate_ss) {
@@ -14769,10 +14770,10 @@ static void aarch64_tr_translate_insn(DisasContex=
tBase *dcbase, CPUState *cpu)
return;
}
=20
- s->pc_curr =3D s->base.pc_next;
- insn =3D arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b);
+ s->pc_curr =3D pc;
+ insn =3D arm_ldl_code(env, &s->base, pc, s->sctlr_b);
s->insn =3D insn;
- s->base.pc_next +=3D 4;
+ s->base.pc_next =3D pc + 4;
=20
s->fp_access_checked =3D false;
s->sve_access_checked =3D false;
--=20
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To: qemu-devel@nongnu.org
Subject: [PULL 10/33] target/arm: Hoist pc_next to a local variable in
arm_tr_translate_insn
Date: Wed, 15 Dec 2021 10:40:26 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 98f59259284..c721b2ce42c 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9548,17 +9548,18 @@ static void arm_tr_translate_insn(DisasContextBase =
*dcbase, CPUState *cpu)
{
DisasContext *dc =3D container_of(dcbase, DisasContext, base);
CPUARMState *env =3D cpu->env_ptr;
+ uint32_t pc =3D dc->base.pc_next;
unsigned int insn;
=20
if (arm_pre_translate_insn(dc)) {
- dc->base.pc_next +=3D 4;
+ dc->base.pc_next =3D pc + 4;
return;
}
=20
- dc->pc_curr =3D dc->base.pc_next;
- insn =3D arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
+ dc->pc_curr =3D pc;
+ insn =3D arm_ldl_code(env, &dc->base, pc, dc->sctlr_b);
dc->insn =3D insn;
- dc->base.pc_next +=3D 4;
+ dc->base.pc_next =3D pc + 4;
disas_arm_insn(dc, insn);
=20
arm_post_translate_insn(dc);
--=20
2.25.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 11/33] target/arm: Hoist pc_next to a local variable in
thumb_tr_translate_insn
Date: Wed, 15 Dec 2021 10:40:27 +0000
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Content-Type: text/plain; charset="utf-8"
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index c721b2ce42c..1c2a7274dfc 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9618,25 +9618,25 @@ static void thumb_tr_translate_insn(DisasContextBas=
e *dcbase, CPUState *cpu)
{
DisasContext *dc =3D container_of(dcbase, DisasContext, base);
CPUARMState *env =3D cpu->env_ptr;
+ uint32_t pc =3D dc->base.pc_next;
uint32_t insn;
bool is_16bit;
=20
if (arm_pre_translate_insn(dc)) {
- dc->base.pc_next +=3D 2;
+ dc->base.pc_next =3D pc + 2;
return;
}
=20
- dc->pc_curr =3D dc->base.pc_next;
- insn =3D arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
+ dc->pc_curr =3D pc;
+ insn =3D arm_lduw_code(env, &dc->base, pc, dc->sctlr_b);
is_16bit =3D thumb_insn_is_16bit(dc, dc->base.pc_next, insn);
- dc->base.pc_next +=3D 2;
+ pc +=3D 2;
if (!is_16bit) {
- uint32_t insn2 =3D arm_lduw_code(env, &dc->base, dc->base.pc_next,
- dc->sctlr_b);
-
+ uint32_t insn2 =3D arm_lduw_code(env, &dc->base, pc, dc->sctlr_b);
insn =3D insn << 16 | insn2;
- dc->base.pc_next +=3D 2;
+ pc +=3D 2;
}
+ dc->base.pc_next =3D pc;
dc->insn =3D insn;
=20
if (dc->pstate_il) {
--=20
2.25.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 12/33] target/arm: Split arm_pre_translate_insn
Date: Wed, 15 Dec 2021 10:40:28 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Create arm_check_ss_active and arm_check_kernelpage.
Reverse the order of the tests. While it doesn't matter in practice,
because only user-only has a kernel page and user-only never sets
ss_active, ss_active has priority over execution exceptions and it
is best to keep them in the proper order.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 1c2a7274dfc..0103c75a274 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9502,7 +9502,7 @@ static void arm_tr_insn_start(DisasContextBase *dcbas=
e, CPUState *cpu)
dc->insn_start =3D tcg_last_op();
}
=20
-static bool arm_pre_translate_insn(DisasContext *dc)
+static bool arm_check_kernelpage(DisasContext *dc)
{
#ifdef CONFIG_USER_ONLY
/* Intercept jump to the magic kernel page. */
@@ -9514,7 +9514,11 @@ static bool arm_pre_translate_insn(DisasContext *dc)
return true;
}
#endif
+ return false;
+}
=20
+static bool arm_check_ss_active(DisasContext *dc)
+{
if (dc->ss_active && !dc->pstate_ss) {
/* Singlestep state is Active-pending.
* If we're in this state at the start of a TB then either
@@ -9551,7 +9555,7 @@ static void arm_tr_translate_insn(DisasContextBase *d=
cbase, CPUState *cpu)
uint32_t pc =3D dc->base.pc_next;
unsigned int insn;
=20
- if (arm_pre_translate_insn(dc)) {
+ if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
dc->base.pc_next =3D pc + 4;
return;
}
@@ -9622,7 +9626,7 @@ static void thumb_tr_translate_insn(DisasContextBase =
*dcbase, CPUState *cpu)
uint32_t insn;
bool is_16bit;
=20
- if (arm_pre_translate_insn(dc)) {
+ if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
dc->base.pc_next =3D pc + 2;
return;
}
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 13/33] target/arm: Advance pc for arch single-step exception
Date: Wed, 15 Dec 2021 10:40:29 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
The size of the code covered by a TranslationBlock cannot be 0;
this is checked via assert in tb_gen_code.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 9c4258ccac2..2986fe13935 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14767,6 +14767,7 @@ static void aarch64_tr_translate_insn(DisasContextB=
ase *dcbase, CPUState *cpu)
assert(s->base.num_insns =3D=3D 1);
gen_swstep_exception(s, 0, 0);
s->base.is_jmp =3D DISAS_NORETURN;
+ s->base.pc_next =3D pc + 4;
return;
}
=20
--=20
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To: qemu-devel@nongnu.org
Subject: [PULL 14/33] target/arm: Split compute_fsr_fsc out of
arm_deliver_fault
Date: Wed, 15 Dec 2021 10:40:30 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
We will reuse this section of arm_deliver_fault for
raising pc alignment faults.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tlb_helper.c | 45 +++++++++++++++++++++++++----------------
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index 12a934e9248..4cacb9658fb 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -49,25 +49,11 @@ static inline uint32_t merge_syn_data_abort(uint32_t te=
mplate_syn,
return syn;
}
=20
-static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx, ARMMMUFaultInfo *=
fi)
+static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi,
+ int target_el, int mmu_idx, uint32_t *ret_=
fsc)
{
- CPUARMState *env =3D &cpu->env;
- int target_el;
- bool same_el;
- uint32_t syn, exc, fsr, fsc;
ARMMMUIdx arm_mmu_idx =3D core_to_arm_mmu_idx(env, mmu_idx);
-
- target_el =3D exception_target_el(env);
- if (fi->stage2) {
- target_el =3D 2;
- env->cp15.hpfar_el2 =3D extract64(fi->s2addr, 12, 47) << 4;
- if (arm_is_secure_below_el3(env) && fi->s1ns) {
- env->cp15.hpfar_el2 |=3D HPFAR_NS;
- }
- }
- same_el =3D (arm_current_el(env) =3D=3D target_el);
+ uint32_t fsr, fsc;
=20
if (target_el =3D=3D 2 || arm_el_is_aa64(env, target_el) ||
arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
@@ -88,6 +74,31 @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu,=
vaddr addr,
fsc =3D 0x3f;
}
=20
+ *ret_fsc =3D fsc;
+ return fsr;
+}
+
+static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx, ARMMMUFaultInfo *=
fi)
+{
+ CPUARMState *env =3D &cpu->env;
+ int target_el;
+ bool same_el;
+ uint32_t syn, exc, fsr, fsc;
+
+ target_el =3D exception_target_el(env);
+ if (fi->stage2) {
+ target_el =3D 2;
+ env->cp15.hpfar_el2 =3D extract64(fi->s2addr, 12, 47) << 4;
+ if (arm_is_secure_below_el3(env) && fi->s1ns) {
+ env->cp15.hpfar_el2 |=3D HPFAR_NS;
+ }
+ }
+ same_el =3D (arm_current_el(env) =3D=3D target_el);
+
+ fsr =3D compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc);
+
if (access_type =3D=3D MMU_INST_FETCH) {
syn =3D syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc);
exc =3D EXCP_PREFETCH_ABORT;
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 15/33] target/arm: Take an exception if PC is misaligned
Date: Wed, 15 Dec 2021 10:40:31 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
For A64, any input to an indirect branch can cause this.
For A32, many indirect branch paths force the branch to be aligned,
but BXWritePC does not. This includes the BX instruction but also
other interworking changes to PC. Prior to v8, this case is UNDEFINED.
With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an
exception or force align the PC.
We choose to raise an exception because we have the infrastructure,
it makes the generated code for gen_bx simpler, and it has the
possibility of catching more guest bugs.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.h | 1 +
target/arm/syndrome.h | 5 ++++
linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++++++---------------
target/arm/tlb_helper.c | 18 ++++++++++++++
target/arm/translate-a64.c | 15 ++++++++++++
target/arm/translate.c | 22 ++++++++++++++++-
6 files changed, 87 insertions(+), 20 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 448a86edfdc..b463d9343bc 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -47,6 +47,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
DEF_HELPER_2(exception_internal, void, env, i32)
DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32)
DEF_HELPER_2(exception_bkpt_insn, void, env, i32)
+DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl)
DEF_HELPER_1(setend, void, env)
DEF_HELPER_2(wfi, void, env, i32)
DEF_HELPER_1(wfe, void, env)
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index f30f4130a27..8cde8e7243a 100644
--- a/target/arm/syndrome.h
+++ b/target/arm/syndrome.h
@@ -282,4 +282,9 @@ static inline uint32_t syn_illegalstate(void)
return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL;
}
=20
+static inline uint32_t syn_pcalignment(void)
+{
+ return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
+}
+
#endif /* TARGET_ARM_SYNDROME_H */
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
index 97e0728b679..f9f3473288f 100644
--- a/linux-user/aarch64/cpu_loop.c
+++ b/linux-user/aarch64/cpu_loop.c
@@ -113,27 +113,35 @@ void cpu_loop(CPUARMState *env)
break;
case EXCP_PREFETCH_ABORT:
case EXCP_DATA_ABORT:
- /* We should only arrive here with EC in {DATAABORT, INSNABORT=
}. */
ec =3D syn_get_ec(env->exception.syndrome);
- assert(ec =3D=3D EC_DATAABORT || ec =3D=3D EC_INSNABORT);
-
- /* Both EC have the same format for FSC, or close enough. */
- fsc =3D extract32(env->exception.syndrome, 0, 6);
- switch (fsc) {
- case 0x04 ... 0x07: /* Translation fault, level {0-3} */
- si_signo =3D TARGET_SIGSEGV;
- si_code =3D TARGET_SEGV_MAPERR;
+ switch (ec) {
+ case EC_DATAABORT:
+ case EC_INSNABORT:
+ /* Both EC have the same format for FSC, or close enough. =
*/
+ fsc =3D extract32(env->exception.syndrome, 0, 6);
+ switch (fsc) {
+ case 0x04 ... 0x07: /* Translation fault, level {0-3} */
+ si_signo =3D TARGET_SIGSEGV;
+ si_code =3D TARGET_SEGV_MAPERR;
+ break;
+ case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
+ case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
+ si_signo =3D TARGET_SIGSEGV;
+ si_code =3D TARGET_SEGV_ACCERR;
+ break;
+ case 0x11: /* Synchronous Tag Check Fault */
+ si_signo =3D TARGET_SIGSEGV;
+ si_code =3D TARGET_SEGV_MTESERR;
+ break;
+ case 0x21: /* Alignment fault */
+ si_signo =3D TARGET_SIGBUS;
+ si_code =3D TARGET_BUS_ADRALN;
+ break;
+ default:
+ g_assert_not_reached();
+ }
break;
- case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
- case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
- si_signo =3D TARGET_SIGSEGV;
- si_code =3D TARGET_SEGV_ACCERR;
- break;
- case 0x11: /* Synchronous Tag Check Fault */
- si_signo =3D TARGET_SIGSEGV;
- si_code =3D TARGET_SEGV_MTESERR;
- break;
- case 0x21: /* Alignment fault */
+ case EC_PCALIGNMENT:
si_signo =3D TARGET_SIGBUS;
si_code =3D TARGET_BUS_ADRALN;
break;
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index 4cacb9658fb..b79004e0cca 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -9,6 +9,7 @@
#include "cpu.h"
#include "internals.h"
#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
=20
static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
unsigned int target_el,
@@ -134,6 +135,23 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr v=
addr,
arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
}
=20
+void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc)
+{
+ ARMMMUFaultInfo fi =3D { .type =3D ARMFault_Alignment };
+ int target_el =3D exception_target_el(env);
+ int mmu_idx =3D cpu_mmu_index(env, true);
+ uint32_t fsc;
+
+ env->exception.vaddress =3D pc;
+
+ /*
+ * Note that the fsc is not applicable to this exception,
+ * since any syndrome is pcalignment not insn_abort.
+ */
+ env->exception.fsr =3D compute_fsr_fsc(env, &fi, target_el, mmu_idx, &=
fsc);
+ raise_exception(env, EXCP_PREFETCH_ABORT, syn_pcalignment(), target_el=
);
+}
+
#if !defined(CONFIG_USER_ONLY)
=20
/*
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2986fe13935..130a9ff8d54 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14753,6 +14753,7 @@ static void aarch64_tr_translate_insn(DisasContextB=
ase *dcbase, CPUState *cpu)
uint64_t pc =3D s->base.pc_next;
uint32_t insn;
=20
+ /* Singlestep exceptions have the highest priority. */
if (s->ss_active && !s->pstate_ss) {
/* Singlestep state is Active-pending.
* If we're in this state at the start of a TB then either
@@ -14771,6 +14772,20 @@ static void aarch64_tr_translate_insn(DisasContext=
Base *dcbase, CPUState *cpu)
return;
}
=20
+ if (pc & 3) {
+ /*
+ * PC alignment fault. This has priority over the instruction abo=
rt
+ * that we would receive from a translation fault via arm_ldl_code.
+ * This should only be possible after an indirect branch, at the
+ * start of the TB.
+ */
+ assert(s->base.num_insns =3D=3D 1);
+ gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc));
+ s->base.is_jmp =3D DISAS_NORETURN;
+ s->base.pc_next =3D QEMU_ALIGN_UP(pc, 4);
+ return;
+ }
+
s->pc_curr =3D pc;
insn =3D arm_ldl_code(env, &s->base, pc, s->sctlr_b);
s->insn =3D insn;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0103c75a274..45917c3a6d2 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9555,7 +9555,27 @@ static void arm_tr_translate_insn(DisasContextBase *=
dcbase, CPUState *cpu)
uint32_t pc =3D dc->base.pc_next;
unsigned int insn;
=20
- if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
+ /* Singlestep exceptions have the highest priority. */
+ if (arm_check_ss_active(dc)) {
+ dc->base.pc_next =3D pc + 4;
+ return;
+ }
+
+ if (pc & 3) {
+ /*
+ * PC alignment fault. This has priority over the instruction abo=
rt
+ * that we would receive from a translation fault via arm_ldl_code
+ * (or the execution of the kernelpage entrypoint). This should on=
ly
+ * be possible after an indirect branch, at the start of the TB.
+ */
+ assert(dc->base.num_insns =3D=3D 1);
+ gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc));
+ dc->base.is_jmp =3D DISAS_NORETURN;
+ dc->base.pc_next =3D QEMU_ALIGN_UP(pc, 4);
+ return;
+ }
+
+ if (arm_check_kernelpage(dc)) {
dc->base.pc_next =3D pc + 4;
return;
}
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 16/33] target/arm: Assert thumb pc is aligned
Date: Wed, 15 Dec 2021 10:40:32 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Misaligned thumb PC is architecturally impossible.
Assert is better than proceeding, in case we've missed
something somewhere.
Expand a comment about aligning the pc in gdbstub.
Fail an incoming migrate if a thumb pc is misaligned.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/gdbstub.c | 9 +++++++--
target/arm/machine.c | 10 ++++++++++
target/arm/translate.c | 3 +++
3 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index 134da0d0ae3..ca1de475116 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -77,8 +77,13 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *me=
m_buf, int n)
=20
tmp =3D ldl_p(mem_buf);
=20
- /* Mask out low bit of PC to workaround gdb bugs. This will probably
- cause problems if we ever implement the Jazelle DBX extensions. */
+ /*
+ * Mask out low bits of PC to workaround gdb bugs.
+ * This avoids an assert in thumb_tr_translate_insn, because it is
+ * architecturally impossible to misalign the pc.
+ * This will probably cause problems if we ever implement the
+ * Jazelle DBX extensions.
+ */
if (n =3D=3D 15) {
tmp &=3D ~1;
}
diff --git a/target/arm/machine.c b/target/arm/machine.c
index c74d8c3f4b3..135d2420b5c 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -794,6 +794,16 @@ static int cpu_post_load(void *opaque, int version_id)
return -1;
}
}
+
+ /*
+ * Misaligned thumb pc is architecturally impossible.
+ * We have an assert in thumb_tr_translate_insn to verify this.
+ * Fail an incoming migrate to avoid this assert.
+ */
+ if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
+ return -1;
+ }
+
if (!kvm_enabled()) {
pmu_op_finish(&cpu->env);
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 45917c3a6d2..0a3840d227f 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9646,6 +9646,9 @@ static void thumb_tr_translate_insn(DisasContextBase =
*dcbase, CPUState *cpu)
uint32_t insn;
bool is_16bit;
=20
+ /* Misaligned thumb PC is architecturally impossible. */
+ assert((dc->base.pc_next & 1) =3D=3D 0);
+
if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
dc->base.pc_next =3D pc + 2;
return;
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 17/33] target/arm: Suppress bp for exceptions with more
priority
Date: Wed, 15 Dec 2021 10:40:33 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Both single-step and pc alignment faults have priority over
breakpoint exceptions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/debug_helper.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index 2983e36dd33..32f3caec238 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -220,6 +220,7 @@ bool arm_debug_check_breakpoint(CPUState *cs)
{
ARMCPU *cpu =3D ARM_CPU(cs);
CPUARMState *env =3D &cpu->env;
+ target_ulong pc;
int n;
=20
/*
@@ -231,6 +232,28 @@ bool arm_debug_check_breakpoint(CPUState *cs)
return false;
}
=20
+ /*
+ * Single-step exceptions have priority over breakpoint exceptions.
+ * If single-step state is active-pending, suppress the bp.
+ */
+ if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) {
+ return false;
+ }
+
+ /*
+ * PC alignment faults have priority over breakpoint exceptions.
+ */
+ pc =3D is_a64(env) ? env->pc : env->regs[15];
+ if ((is_a64(env) || !env->thumb) && (pc & 3) !=3D 0) {
+ return false;
+ }
+
+ /*
+ * Instruction aborts have priority over breakpoint exceptions.
+ * TODO: We would need to look up the page for PC and verify that
+ * it is present and executable.
+ */
+
for (n =3D 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
if (bp_wp_matches(cpu, n, false)) {
return true;
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 18/33] tests/tcg: Add arm and aarch64 pc alignment tests
Date: Wed, 15 Dec 2021 10:40:34 +0000
Message-Id: <20211215104049.2030475-19-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/tcg/aarch64/pcalign-a64.c | 37 +++++++++++++++++++++++++
tests/tcg/arm/pcalign-a32.c | 46 +++++++++++++++++++++++++++++++
tests/tcg/aarch64/Makefile.target | 4 +--
tests/tcg/arm/Makefile.target | 4 +++
4 files changed, 89 insertions(+), 2 deletions(-)
create mode 100644 tests/tcg/aarch64/pcalign-a64.c
create mode 100644 tests/tcg/arm/pcalign-a32.c
diff --git a/tests/tcg/aarch64/pcalign-a64.c b/tests/tcg/aarch64/pcalign-a6=
4.c
new file mode 100644
index 00000000000..6b9277f919f
--- /dev/null
+++ b/tests/tcg/aarch64/pcalign-a64.c
@@ -0,0 +1,37 @@
+/* Test PC misalignment exception */
+
+#include <assert.h>
+#include <signal.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+static void *expected;
+
+static void sigbus(int sig, siginfo_t *info, void *vuc)
+{
+ assert(info->si_code =3D=3D BUS_ADRALN);
+ assert(info->si_addr =3D=3D expected);
+ exit(EXIT_SUCCESS);
+}
+
+int main()
+{
+ void *tmp;
+
+ struct sigaction sa =3D {
+ .sa_sigaction =3D sigbus,
+ .sa_flags =3D SA_SIGINFO
+ };
+
+ if (sigaction(SIGBUS, &sa, NULL) < 0) {
+ perror("sigaction");
+ return EXIT_FAILURE;
+ }
+
+ asm volatile("adr %0, 1f + 1\n\t"
+ "str %0, %1\n\t"
+ "br %0\n"
+ "1:"
+ : "=3D&r"(tmp), "=3Dm"(expected));
+ abort();
+}
diff --git a/tests/tcg/arm/pcalign-a32.c b/tests/tcg/arm/pcalign-a32.c
new file mode 100644
index 00000000000..3c9c8cc97b1
--- /dev/null
+++ b/tests/tcg/arm/pcalign-a32.c
@@ -0,0 +1,46 @@
+/* Test PC misalignment exception */
+
+#ifdef __thumb__
+#error "This test must be compiled for ARM"
+#endif
+
+#include <assert.h>
+#include <signal.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+static void *expected;
+
+static void sigbus(int sig, siginfo_t *info, void *vuc)
+{
+ assert(info->si_code =3D=3D BUS_ADRALN);
+ assert(info->si_addr =3D=3D expected);
+ exit(EXIT_SUCCESS);
+}
+
+int main()
+{
+ void *tmp;
+
+ struct sigaction sa =3D {
+ .sa_sigaction =3D sigbus,
+ .sa_flags =3D SA_SIGINFO
+ };
+
+ if (sigaction(SIGBUS, &sa, NULL) < 0) {
+ perror("sigaction");
+ return EXIT_FAILURE;
+ }
+
+ asm volatile("adr %0, 1f + 2\n\t"
+ "str %0, %1\n\t"
+ "bx %0\n"
+ "1:"
+ : "=3D&r"(tmp), "=3Dm"(expected));
+
+ /*
+ * From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns
+ * the address or not. If so, we can legitimately fall through.
+ */
+ return EXIT_SUCCESS;
+}
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile=
.target
index 2c05c90d170..1d967901bd2 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -8,8 +8,8 @@ VPATH +=3D $(ARM_SRC)
AARCH64_SRC=3D$(SRC_PATH)/tests/tcg/aarch64
VPATH +=3D $(AARCH64_SRC)
=20
-# Float-convert Tests
-AARCH64_TESTS=3Dfcvt
+# Base architecture tests
+AARCH64_TESTS=3Dfcvt pcalign-a64
=20
fcvt: LDFLAGS+=3D-lm
=20
diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target
index 5ab59ed6ce1..f509d823d4f 100644
--- a/tests/tcg/arm/Makefile.target
+++ b/tests/tcg/arm/Makefile.target
@@ -29,6 +29,10 @@ run-fcvt: fcvt
$(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)")
$(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref)
=20
+# PC alignment test
+ARM_TESTS +=3D pcalign-a32
+pcalign-a32: CFLAGS+=3D-marm
+
ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y)
=20
# Semihosting smoke test for linux-user
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 19/33] target/i386: Use assert() to sanity-check b1 in SSE
decode
Date: Wed, 15 Dec 2021 10:40:35 +0000
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In the SSE decode function gen_sse(), we combine a byte
'b' and a value 'b1' which can be [0..3], and switch on them:
b |=3D (b1 << 8);
switch (b) {
...
default:
unknown_op:
gen_unknown_opcode(env, s);
return;
}
In three cases inside this switch, we were then also checking for
"if (b1 >=3D 2) { goto unknown_op; }".
However, this can never happen, because the 'case' values in each place
are 0x0nn or 0x1nn and the switch will have directed the b1 =3D=3D (2, 3)
cases to the default already.
This check was added in commit c045af25a52e9 in 2010; the added code
was unnecessary then as well, and was apparently intended only to
ensure that we never accidentally ended up indexing off the end
of an sse_op_table with only 2 entries as a result of future bugs
in the decode logic.
Change the checks to assert() instead, and make sure they're always
immediately before the array access they are protecting.
Fixes: Coverity CID 1460207
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/tcg/translate.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index e9e14515409..05f9336c9b9 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -3519,9 +3519,6 @@ static void gen_sse(CPUX86State *env, DisasContext *s=
, int b,
case 0x171: /* shift xmm, im */
case 0x172:
case 0x173:
- if (b1 >=3D 2) {
- goto unknown_op;
- }
val =3D x86_ldub_code(env, s);
if (is_xmm) {
tcg_gen_movi_tl(s->T0, val);
@@ -3540,6 +3537,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s=
, int b,
offsetof(CPUX86State, mmx_t0.MMX_L(1)));
op1_offset =3D offsetof(CPUX86State,mmx_t0);
}
+ assert(b1 < 2);
sse_fn_epp =3D sse_op_table2[((b - 1) & 3) * 8 +
(((modrm >> 3)) & 7)][b1];
if (!sse_fn_epp) {
@@ -3770,10 +3768,8 @@ static void gen_sse(CPUX86State *env, DisasContext *=
s, int b,
rm =3D modrm & 7;
reg =3D ((modrm >> 3) & 7) | REX_R(s);
mod =3D (modrm >> 6) & 3;
- if (b1 >=3D 2) {
- goto unknown_op;
- }
=20
+ assert(b1 < 2);
sse_fn_epp =3D sse_op_table6[b].op[b1];
if (!sse_fn_epp) {
goto unknown_op;
@@ -4200,10 +4196,8 @@ static void gen_sse(CPUX86State *env, DisasContext *=
s, int b,
rm =3D modrm & 7;
reg =3D ((modrm >> 3) & 7) | REX_R(s);
mod =3D (modrm >> 6) & 3;
- if (b1 >=3D 2) {
- goto unknown_op;
- }
=20
+ assert(b1 < 2);
sse_fn_eppi =3D sse_op_table7[b].op[b1];
if (!sse_fn_eppi) {
goto unknown_op;
--=20
2.25.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 20/33] include/hw/i386: Don't include qemu-common.h in .h files
Date: Wed, 15 Dec 2021 10:40:36 +0000
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The qemu-common.h header is not supposed to be included from any
other header files, only from .c files (as documented in a comment at
the start of it).
include/hw/i386/x86.h and include/hw/i386/microvm.h break this rule.
In fact, the include is not required at all, so we can just drop it
from both files.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Message-id: 20211129200510.1233037-2-peter.maydell@linaro.org
---
include/hw/i386/microvm.h | 1 -
include/hw/i386/x86.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h
index 4d9c732d4b2..efcbd926fd4 100644
--- a/include/hw/i386/microvm.h
+++ b/include/hw/i386/microvm.h
@@ -18,7 +18,6 @@
#ifndef HW_I386_MICROVM_H
#define HW_I386_MICROVM_H
=20
-#include "qemu-common.h"
#include "exec/hwaddr.h"
#include "qemu/notify.h"
=20
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
index bb1cfb88966..a145a303703 100644
--- a/include/hw/i386/x86.h
+++ b/include/hw/i386/x86.h
@@ -17,7 +17,6 @@
#ifndef HW_I386_X86_H
#define HW_I386_X86_H
=20
-#include "qemu-common.h"
#include "exec/hwaddr.h"
#include "qemu/notify.h"
=20
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 21/33] target/hexagon/cpu.h: don't include qemu-common.h
Date: Wed, 15 Dec 2021 10:40:37 +0000
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The qemu-common.h header is not supposed to be included from any
other header files, only from .c files (as documented in a comment at
the start of it).
Move the include to linux-user/hexagon/cpu_loop.c, which needs it for
the declaration of cpu_exec_step_atomic().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Message-id: 20211129200510.1233037-3-peter.maydell@linaro.org
---
target/hexagon/cpu.h | 1 -
linux-user/hexagon/cpu_loop.c | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index de121d950f2..58a0d3870bb 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -23,7 +23,6 @@ typedef struct CPUHexagonState CPUHexagonState;
=20
#include "fpu/softfloat-types.h"
=20
-#include "qemu-common.h"
#include "exec/cpu-defs.h"
#include "hex_regs.h"
#include "mmvec/mmvec.h"
diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c
index 6b24cbaba93..e47f8348d56 100644
--- a/linux-user/hexagon/cpu_loop.c
+++ b/linux-user/hexagon/cpu_loop.c
@@ -19,6 +19,7 @@
*/
=20
#include "qemu/osdep.h"
+#include "qemu-common.h"
#include "qemu.h"
#include "user-internals.h"
#include "cpu_loop-common.h"
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 22/33] target/rx/cpu.h: Don't include qemu-common.h
Date: Wed, 15 Dec 2021 10:40:38 +0000
Message-Id: <20211215104049.2030475-23-peter.maydell@linaro.org>
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The qemu-common.h header is not supposed to be included from any
other header files, only from .c files (as documented in a comment at
the start of it).
Nothing actually relies on target/rx/cpu.h including it, so we can
just drop the include.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-id: 20211129200510.1233037-4-peter.maydell@linaro.org
---
target/rx/cpu.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 4ac71aec370..657db84ef0a 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -20,7 +20,6 @@
#define RX_CPU_H
=20
#include "qemu/bitops.h"
-#include "qemu-common.h"
#include "hw/registerfields.h"
#include "cpu-qom.h"
=20
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 23/33] hw/arm: Don't include qemu-common.h unnecessarily
Date: Wed, 15 Dec 2021 10:40:39 +0000
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A lot of C files in hw/arm include qemu-common.h when they don't
need anything from it. Drop the include lines.
omap1.c, pxa2xx.c and strongarm.c retain the include because they
use it for the prototype of qemu_get_timedate().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-id: 20211129200510.1233037-5-peter.maydell@linaro.org
---
hw/arm/boot.c | 1 -
hw/arm/digic_boards.c | 1 -
hw/arm/highbank.c | 1 -
hw/arm/npcm7xx_boards.c | 1 -
hw/arm/sbsa-ref.c | 1 -
hw/arm/stm32f405_soc.c | 1 -
hw/arm/vexpress.c | 1 -
hw/arm/virt.c | 1 -
8 files changed, 8 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 74ad397b1ff..399f8e837ce 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -8,7 +8,6 @@
*/
=20
#include "qemu/osdep.h"
-#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index b771a3d8b74..4093af09cb2 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
@@ -25,7 +25,6 @@
=20
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "qemu-common.h"
#include "qemu/datadir.h"
#include "hw/boards.h"
#include "qemu/error-report.h"
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index c3cb315dbc6..4210894d814 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -18,7 +18,6 @@
*/
=20
#include "qemu/osdep.h"
-#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qapi/error.h"
#include "hw/sysbus.h"
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index dec7d16ae51..aff8c870420 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -24,7 +24,6 @@
#include "hw/qdev-core.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"
-#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "sysemu/blockdev.h"
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 358714bd3e8..dd944553f78 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -18,7 +18,6 @@
*/
=20
#include "qemu/osdep.h"
-#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
index 0019b7f4785..c07947d9f8b 100644
--- a/hw/arm/stm32f405_soc.c
+++ b/hw/arm/stm32f405_soc.c
@@ -24,7 +24,6 @@
=20
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "qemu-common.h"
#include "exec/address-spaces.h"
#include "sysemu/sysemu.h"
#include "hw/arm/stm32f405_soc.h"
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 58481c07629..3e6d63c7f96 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -23,7 +23,6 @@
=20
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "qemu-common.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "hw/sysbus.h"
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 30da05dfe04..3e2144e31af 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -29,7 +29,6 @@
*/
=20
#include "qemu/osdep.h"
-#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "qemu/option.h"
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 24/33] target/arm: Correct calculation of tlb range invalidate
length
Date: Wed, 15 Dec 2021 10:40:40 +0000
Message-Id: <20211215104049.2030475-25-peter.maydell@linaro.org>
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The calculation of the length of TLB range invalidate operations
in tlbi_aa64_range_get_length() is incorrect in two ways:
* the NUM field is 5 bits, but we read only 4 bits
* we miscalculate the page_shift value, because of an
off-by-one error:
TG 0b00 is invalid
TG 0b01 is 4K granule size =3D=3D 4096 =3D=3D 2^12
TG 0b10 is 16K granule size =3D=3D 16384 =3D=3D 2^14
TG 0b11 is 64K granule size =3D=3D 65536 =3D=3D 2^16
so page_shift should be (TG - 1) * 2 + 12
Thanks to the bug report submitter Cha HyunSoo for identifying
both these errors.
Fixes: 84940ed82552d3c ("target/arm: Add support for FEAT_TLBIRANGE")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/734
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Message-id: 20211130173257.1274194-1-peter.maydell@linaro.org
---
target/arm/helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9b317899a66..db837d53bd9 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4519,18 +4519,18 @@ static uint64_t tlbi_aa64_range_get_length(CPUARMSt=
ate *env,
uint64_t exponent;
uint64_t length;
=20
- num =3D extract64(value, 39, 4);
+ num =3D extract64(value, 39, 5);
scale =3D extract64(value, 44, 2);
page_size_granule =3D extract64(value, 46, 2);
=20
- page_shift =3D page_size_granule * 2 + 12;
-
if (page_size_granule =3D=3D 0) {
qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n",
page_size_granule);
return 0;
}
=20
+ page_shift =3D (page_size_granule - 1) * 2 + 12;
+
exponent =3D (5 * scale) + 1;
length =3D (num + 1) << (exponent + page_shift);
=20
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 25/33] hw/net: npcm7xx_emc fix missing queue_flush
Date: Wed, 15 Dec 2021 10:40:41 +0000
Message-Id: <20211215104049.2030475-26-peter.maydell@linaro.org>
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From: Patrick Venture <venture@google.com>
The rx_active boolean change to true should always trigger a try_read
call that flushes the queue.
Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Message-id: 20211203221002.1719306-1-venture@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/net/npcm7xx_emc.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c
index 7c892f820fb..545b2b74108 100644
--- a/hw/net/npcm7xx_emc.c
+++ b/hw/net/npcm7xx_emc.c
@@ -284,6 +284,12 @@ static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t=
mista_flag)
emc_set_mista(emc, mista_flag);
}
=20
+static void emc_enable_rx_and_flush(NPCM7xxEMCState *emc)
+{
+ emc->rx_active =3D true;
+ qemu_flush_queued_packets(qemu_get_queue(emc->nic));
+}
+
static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc,
const NPCM7xxEMCTxDesc *tx_desc,
uint32_t desc_addr)
@@ -581,13 +587,6 @@ static ssize_t emc_receive(NetClientState *nc, const u=
int8_t *buf, size_t len1)
return len;
}
=20
-static void emc_try_receive_next_packet(NPCM7xxEMCState *emc)
-{
- if (emc_can_receive(qemu_get_queue(emc->nic))) {
- qemu_flush_queued_packets(qemu_get_queue(emc->nic));
- }
-}
-
static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned siz=
e)
{
NPCM7xxEMCState *emc =3D opaque;
@@ -703,7 +702,7 @@ static void npcm7xx_emc_write(void *opaque, hwaddr offs=
et,
emc->regs[REG_MGSTA] |=3D REG_MGSTA_RXHA;
}
if (value & REG_MCMDR_RXON) {
- emc->rx_active =3D true;
+ emc_enable_rx_and_flush(emc);
} else {
emc_halt_rx(emc, 0);
}
@@ -739,8 +738,7 @@ static void npcm7xx_emc_write(void *opaque, hwaddr offs=
et,
break;
case REG_RSDR:
if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) {
- emc->rx_active =3D true;
- emc_try_receive_next_packet(emc);
+ emc_enable_rx_and_flush(emc);
}
break;
case REG_MIIDA:
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 26/33] hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu
Date: Wed, 15 Dec 2021 10:40:42 +0000
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From: Jean-Philippe Brucker <jean-philippe@linaro.org>
When a virtio-iommu is instantiated, describe it using the ACPI VIOT
table.
Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-2-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt-acpi-build.c | 7 +++++++
hw/arm/Kconfig | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 674f9026525..d0f4867fdfe 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -55,6 +55,7 @@
#include "kvm_arm.h"
#include "migration/vmstate.h"
#include "hw/acpi/ghes.h"
+#include "hw/acpi/viot.h"
=20
#define ARM_SPI_BASE 32
=20
@@ -1011,6 +1012,12 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuil=
dTables *tables)
}
#endif
=20
+ if (vms->iommu =3D=3D VIRT_IOMMU_VIRTIO) {
+ acpi_add_table(table_offsets, tables_blob);
+ build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf,
+ vms->oem_id, vms->oem_table_id);
+ }
+
/* XSDT is pointed to by RSDP */
xsdt =3D tables_blob->len;
build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id,
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 2d37d29f02b..e6525909438 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -27,6 +27,7 @@ config ARM_VIRT
select DIMM
select ACPI_HW_REDUCED
select ACPI_APEI
+ select ACPI_VIOT
=20
config CHEETAH
bool
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 27/33] hw/arm/virt: Remove device tree restriction for
virtio-iommu
Date: Wed, 15 Dec 2021 10:40:43 +0000
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From: Jean-Philippe Brucker <jean-philippe@linaro.org>
virtio-iommu is now supported with ACPI VIOT as well as device tree.
Remove the restriction that prevents from instantiating a virtio-iommu
device under ACPI.
Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-3-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 10 ++--------
hw/virtio/virtio-iommu-pci.c | 12 ++----------
2 files changed, 4 insertions(+), 18 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 3e2144e31af..e621cada990 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -2613,16 +2613,10 @@ static HotplugHandler *virt_machine_get_hotplug_han=
dler(MachineState *machine,
MachineClass *mc =3D MACHINE_GET_CLASS(machine);
=20
if (device_is_dynamic_sysbus(mc, dev) ||
- (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) {
+ object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
+ object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
return HOTPLUG_HANDLER(machine);
}
- if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
- VirtMachineState *vms =3D VIRT_MACHINE(machine);
-
- if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) {
- return HOTPLUG_HANDLER(machine);
- }
- }
return NULL;
}
=20
diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c
index a160ae6b413..6a1df7fe503 100644
--- a/hw/virtio/virtio-iommu-pci.c
+++ b/hw/virtio/virtio-iommu-pci.c
@@ -48,16 +48,8 @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpc=
i_dev, Error **errp)
VirtIOIOMMU *s =3D VIRTIO_IOMMU(vdev);
=20
if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) {
- MachineClass *mc =3D MACHINE_GET_CLASS(qdev_get_machine());
-
- error_setg(errp,
- "%s machine fails to create iommu-map device tree bindi=
ngs",
- mc->name);
- error_append_hint(errp,
- "Check your machine implements a hotplug handler=
"
- "for the virtio-iommu-pci device\n");
- error_append_hint(errp, "Check the guest is booted without FW or w=
ith "
- "-no-acpi\n");
+ error_setg(errp, "Check your machine implements a hotplug handler "
+ "for the virtio-iommu-pci device");
return;
}
for (int i =3D 0; i < s->nb_reserved_regions; i++) {
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 28/33] hw/arm/virt: Reject instantiation of multiple IOMMUs
Date: Wed, 15 Dec 2021 10:40:44 +0000
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From: Jean-Philippe Brucker <jean-philippe@linaro.org>
We do not support instantiating multiple IOMMUs. Before adding a
virtio-iommu, check that no other IOMMU is present. This will detect
both "iommu=3Dsmmuv3" machine parameter and another virtio-iommu instance.
Fixes: 70e89132c9 ("hw/arm/virt: Add the virtio-iommu device tree mappings")
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-4-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index e621cada990..41c9808a3fd 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -2493,6 +2493,11 @@ static void virt_machine_device_pre_plug_cb(HotplugH=
andler *hotplug_dev,
hwaddr db_start =3D 0, db_end =3D 0;
char *resv_prop_str;
=20
+ if (vms->iommu !=3D VIRT_IOMMU_NONE) {
+ error_setg(errp, "virt machine does not support multiple IOMMU=
s");
+ return;
+ }
+
switch (vms->msi_controller) {
case VIRT_MSI_CTRL_NONE:
return;
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 29/33] hw/arm/virt: Use object_property_set instead of
qdev_prop_set
Date: Wed, 15 Dec 2021 10:40:45 +0000
Message-Id: <20211215104049.2030475-30-peter.maydell@linaro.org>
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From: Jean-Philippe Brucker <jean-philippe@linaro.org>
To propagate errors to the caller of the pre_plug callback, use the
object_poperty_set*() functions directly instead of the qdev_prop_set*()
helpers.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-5-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 41c9808a3fd..6bce595aba2 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -2517,8 +2517,9 @@ static void virt_machine_device_pre_plug_cb(HotplugHa=
ndler *hotplug_dev,
db_start, db_end,
VIRTIO_IOMMU_RESV_MEM_T_MSI);
=20
- qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
- qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
+ object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, e=
rrp);
+ object_property_set_str(OBJECT(dev), "reserved-regions[0]",
+ resv_prop_str, errp);
g_free(resv_prop_str);
}
}
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 30/33] tests/acpi: allow updates of VIOT expected data files
Date: Wed, 15 Dec 2021 10:40:46 +0000
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From: Jean-Philippe Brucker <jean-philippe@linaro.org>
Create empty data files and allow updates for the upcoming VIOT tests.
Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-6-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
tests/data/acpi/q35/DSDT.viot | 0
tests/data/acpi/q35/VIOT.viot | 0
tests/data/acpi/virt/VIOT | 0
4 files changed, 3 insertions(+)
create mode 100644 tests/data/acpi/q35/DSDT.viot
create mode 100644 tests/data/acpi/q35/VIOT.viot
create mode 100644 tests/data/acpi/virt/VIOT
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios=
-tables-test-allowed-diff.h
index dfb8523c8bf..29b5b1eabc7 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,4 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/virt/VIOT",
+"tests/data/acpi/q35/DSDT.viot",
+"tests/data/acpi/q35/VIOT.viot",
diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT
new file mode 100644
index 00000000000..e69de29bb2d
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 31/33] tests/acpi: add test case for VIOT
Date: Wed, 15 Dec 2021 10:40:47 +0000
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From: Jean-Philippe Brucker <jean-philippe@linaro.org>
Add two test cases for VIOT, one on the q35 machine and the other on
virt. To test complex topologies the q35 test has two PCIe buses that
bypass the IOMMU (and are therefore not described by VIOT), and two
buses that are translated by virtio-iommu.
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-7-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reported-by: Richard Henderson <richard.henderson@linaro.org>
---
tests/qtest/bios-tables-test.c | 38 ++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 258874167ef..58df53b15b5 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1465,6 +1465,42 @@ static void test_acpi_virt_tcg(void)
free_test_data(&data);
}
=20
+static void test_acpi_q35_viot(void)
+{
+ test_data data =3D {
+ .machine =3D MACHINE_Q35,
+ .variant =3D ".viot",
+ };
+
+ /*
+ * To keep things interesting, two buses bypass the IOMMU.
+ * VIOT should only describes the other two buses.
+ */
+ test_acpi_one("-machine default_bus_bypass_iommu=3Don "
+ "-device virtio-iommu-pci "
+ "-device pxb-pcie,bus_nr=3D0x10,id=3Dpcie.100,bus=3Dpcie=
.0 "
+ "-device pxb-pcie,bus_nr=3D0x20,id=3Dpcie.200,bus=3Dpcie=
.0,bypass_iommu=3Don "
+ "-device pxb-pcie,bus_nr=3D0x30,id=3Dpcie.300,bus=3Dpcie=
.0",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_virt_viot(void)
+{
+ test_data data =3D {
+ .machine =3D "virt",
+ .uefi_fl1 =3D "pc-bios/edk2-aarch64-code.fd",
+ .uefi_fl2 =3D "pc-bios/edk2-arm-vars.fd",
+ .cd =3D "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.=
qcow2",
+ .ram_start =3D 0x40000000ULL,
+ .scan_len =3D 128ULL * 1024 * 1024,
+ };
+
+ test_acpi_one("-cpu cortex-a57 "
+ "-device virtio-iommu-pci", &data);
+ free_test_data(&data);
+}
+
static void test_oem_fields(test_data *data)
{
int i;
@@ -1639,6 +1675,7 @@ int main(int argc, char *argv[])
qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xapic);
qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar);
}
+ qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
} else if (strcmp(arch, "aarch64") =3D=3D 0) {
if (has_tcg) {
qtest_add_func("acpi/virt", test_acpi_virt_tcg);
@@ -1646,6 +1683,7 @@ int main(int argc, char *argv[])
qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp);
qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb);
qtest_add_func("acpi/virt/oem-fields", test_acpi_oem_fields_vi=
rt);
+ qtest_add_func("acpi/virt/viot", test_acpi_virt_viot);
}
}
ret =3D g_test_run();
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 32/33] tests/acpi: add expected blobs for VIOT test on q35
machine
Date: Wed, 15 Dec 2021 10:40:48 +0000
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From: Jean-Philippe Brucker <jean-philippe@linaro.org>
Add expected blobs of the VIOT and DSDT table for the VIOT test on the
q35 machine.
Since the test instantiates a virtio device and two PCIe expander
bridges, DSDT.viot has more blocks than the base DSDT.
The VIOT table generated for the q35 test is:
[000h 0000 4] Signature : "VIOT" [Virtual I/O Trans=
lation Table]
[004h 0004 4] Table Length : 00000070
[008h 0008 1] Revision : 00
[009h 0009 1] Checksum : 3D
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 2] Node count : 0003
[026h 0038 2] Node offset : 0030
[028h 0040 8] Reserved : 0000000000000000
[030h 0048 1] Type : 03 [VirtIO-PCI IOMMU]
[031h 0049 1] Reserved : 00
[032h 0050 2] Length : 0010
[034h 0052 2] PCI Segment : 0000
[036h 0054 2] PCI BDF number : 0010
[038h 0056 8] Reserved : 0000000000000000
[040h 0064 1] Type : 01 [PCI Range]
[041h 0065 1] Reserved : 00
[042h 0066 2] Length : 0018
[044h 0068 4] Endpoint start : 00003000
[048h 0072 2] PCI Segment start : 0000
[04Ah 0074 2] PCI Segment end : 0000
[04Ch 0076 2] PCI BDF start : 3000
[04Eh 0078 2] PCI BDF end : 30FF
[050h 0080 2] Output node : 0030
[052h 0082 6] Reserved : 000000000000
[058h 0088 1] Type : 01 [PCI Range]
[059h 0089 1] Reserved : 00
[05Ah 0090 2] Length : 0018
[05Ch 0092 4] Endpoint start : 00001000
[060h 0096 2] PCI Segment start : 0000
[062h 0098 2] PCI Segment end : 0000
[064h 0100 2] PCI BDF start : 1000
[066h 0102 2] PCI BDF end : 10FF
[068h 0104 2] Output node : 0030
[06Ah 0106 6] Reserved : 000000000000
And the DSDT diff is:
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/q35/DSDT, Fri Dec 10 15:03:08 2021
+ * Disassembly of /tmp/aml-H9Y5D1, Fri Dec 10 15:02:27 2021
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00002061 (8289)
+ * Length 0x000024B6 (9398)
* Revision 0x01 **** 32-bit table (V1), no 64-bit math support
- * Checksum 0xFA
+ * Checksum 0xA7
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
@@ -3114,6 +3114,339 @@
}
}
+ Scope (\_SB)
+ {
+ Device (PC30)
+ {
+ Name (_UID, 0x30) // _UID: Unique ID
+ Name (_BBN, 0x30) // _BBN: BIOS Bus Number
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID=
: Hardware ID
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compat=
ible ID
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap=
abilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 =3D=3D ToUUID ("33db4d5b-1ff7-401c-9657-7441c03d=
d766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Local0 =3D CDW3 /* \_SB_.PC30._OSC.CDW3 */
+ Local0 &=3D 0x1F
+ If ((Arg1 !=3D One))
+ {
+ CDW1 |=3D 0x08
+ }
+
+ If ((CDW3 !=3D Local0))
+ {
+ CDW1 |=3D 0x10
+ }
+
+ CDW3 =3D Local0
+ }
+ Else
+ {
+ CDW1 |=3D 0x04
+ }
+
+ Return (Arg3)
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Local0 =3D Package (0x80){}
+ Local1 =3D Zero
+ While ((Local1 < 0x80))
+ {
+ Local2 =3D (Local1 >> 0x02)
+ Local3 =3D ((Local1 + Local2) & 0x03)
+ If ((Local3 =3D=3D Zero))
+ {
+ Local4 =3D Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKD,
+ Zero
+ }
+ }
+
+ If ((Local3 =3D=3D One))
+ {
+ Local4 =3D Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKA,
+ Zero
+ }
+ }
+
+ If ((Local3 =3D=3D 0x02))
+ {
+ Local4 =3D Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKB,
+ Zero
+ }
+ }
+
+ If ((Local3 =3D=3D 0x03))
+ {
+ Local4 =3D Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKC,
+ Zero
+ }
+ }
+
+ Local4 [Zero] =3D ((Local2 << 0x10) | 0xFFFF)
+ Local4 [One] =3D (Local1 & 0x03)
+ Local0 [Local1] =3D Local4
+ Local1++
+ }
+
+ Return (Local0)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDe=
code,
+ 0x0000, // Granularity
+ 0x0030, // Range Minimum
+ 0x0030, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0001, // Length
+ ,, )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Device (PC20)
+ {
+ Name (_UID, 0x20) // _UID: Unique ID
+ Name (_BBN, 0x20) // _BBN: BIOS Bus Number
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID=
: Hardware ID
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compat=
ible ID
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap=
abilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 =3D=3D ToUUID ("33db4d5b-1ff7-401c-9657-7441c03d=
d766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Local0 =3D CDW3 /* \_SB_.PC20._OSC.CDW3 */
+ Local0 &=3D 0x1F
+ If ((Arg1 !=3D One))
+ {
+ CDW1 |=3D 0x08
+ }
+
+ If ((CDW3 !=3D Local0))
+ {
+ CDW1 |=3D 0x10
+ }
+
+ CDW3 =3D Local0
+ }
+ Else
+ {
+ CDW1 |=3D 0x04
+ }
+
+ Return (Arg3)
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Local0 =3D Package (0x80){}
+ Local1 =3D Zero
+ While ((Local1 < 0x80))
+ {
+ Local2 =3D (Local1 >> 0x02)
+ Local3 =3D ((Local1 + Local2) & 0x03)
+ If ((Local3 =3D=3D Zero))
+ {
+ Local4 =3D Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKD,
+ Zero
+ }
+ }
+
+ If ((Local3 =3D=3D One))
+ {
+ Local4 =3D Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKA,
+ Zero
+ }
+ }
+
+ If ((Local3 =3D=3D 0x02))
+ {
+ Local4 =3D Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKB,
+ Zero
+ }
+ }
+
+ If ((Local3 =3D=3D 0x03))
+ {
+ Local4 =3D Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKC,
+ Zero
+ }
+ }
+
+ Local4 [Zero] =3D ((Local2 << 0x10) | 0xFFFF)
+ Local4 [One] =3D (Local1 & 0x03)
+ Local0 [Local1] =3D Local4
+ Local1++
+ }
+
+ Return (Local0)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDe=
code,
+ 0x0000, // Granularity
+ 0x0020, // Range Minimum
+ 0x0020, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0001, // Length
+ ,, )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Device (PC10)
+ {
+ Name (_UID, 0x10) // _UID: Unique ID
+ Name (_BBN, 0x10) // _BBN: BIOS Bus Number
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID=
: Hardware ID
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compat=
ible ID
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap=
abilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 =3D=3D ToUUID ("33db4d5b-1ff7-401c-9657-7441c03d=
d766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Local0 =3D CDW3 /* \_SB_.PC10._OSC.CDW3 */
+ Local0 &=3D 0x1F
+ If ((Arg1 !=3D One))
+ {
+ CDW1 |=3D 0x08
+ }
+
+ If ((CDW3 !=3D Local0))
+ {
+ CDW1 |=3D 0x10
+ }
+
+ CDW3 =3D Local0
+ }
+ Else
+ {
+ CDW1 |=3D 0x04
+ }
+
+ Return (Arg3)
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Local0 =3D Package (0x80){}
+ Local1 =3D Zero
+ While ((Local1 < 0x80))
+ {
+ Local2 =3D (Local1 >> 0x02)
+ Local3 =3D ((Local1 + Local2) & 0x03)
+ If ((Local3 =3D=3D Zero))
+ {
+ Local4 =3D Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKD,
+ Zero
+ }
+ }
+
+ If ((Local3 =3D=3D One))
+ {
+ Local4 =3D Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKA,
+ Zero
+ }
+ }
+
+ If ((Local3 =3D=3D 0x02))
+ {
+ Local4 =3D Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKB,
+ Zero
+ }
+ }
+
+ If ((Local3 =3D=3D 0x03))
+ {
+ Local4 =3D Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKC,
+ Zero
+ }
+ }
+
+ Local4 [Zero] =3D ((Local2 << 0x10) | 0xFFFF)
+ Local4 [One] =3D (Local1 & 0x03)
+ Local0 [Local1] =3D Local4
+ Local1++
+ }
+
+ Return (Local0)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDe=
code,
+ 0x0000, // Granularity
+ 0x0010, // Range Minimum
+ 0x0010, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0001, // Length
+ ,, )
+ })
+ }
+ }
+
Scope (\_SB.PCI0)
{
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
@@ -3121,9 +3454,9 @@
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
- 0x00FF, // Range Maximum
+ 0x000F, // Range Maximum
0x0000, // Translation Offset
- 0x0100, // Length
+ 0x0010, // Length
,, )
IO (Decode16,
0x0CF8, // Range Minimum
@@ -3278,6 +3611,26 @@
}
}
+ Device (S10)
+ {
+ Name (_ADR, 0x00020000) // _ADR: Address
+ }
+
+ Device (S18)
+ {
+ Name (_ADR, 0x00030000) // _ADR: Address
+ }
+
+ Device (S20)
+ {
+ Name (_ADR, 0x00040000) // _ADR: Address
+ }
+
+ Device (S28)
+ {
+ Name (_ADR, 0x00050000) // _ADR: Address
+ }
+
Method (PCNT, 0, NotSerialized)
{
}
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-8-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
tests/data/acpi/q35/DSDT.viot | Bin 0 -> 9398 bytes
tests/data/acpi/q35/VIOT.viot | Bin 0 -> 112 bytes
3 files changed, 2 deletions(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios=
-tables-test-allowed-diff.h
index 29b5b1eabc7..8367ffe1d40 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,4 +1,2 @@
/* List of comma-separated changed AML files to ignore */
"tests/data/acpi/virt/VIOT",
-"tests/data/acpi/q35/DSDT.viot",
-"tests/data/acpi/q35/VIOT.viot",
diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..1c3b4da5cbe81ecab5e1ef50d38=
3b561c5e0f55f 100644
GIT binary patch
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literal 0
HcmV?d00001
diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..9b179266ccbf84f1c250ee64681=
2d17e27987764 100644
GIT binary patch
literal 112
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Q0Zb)W9Hva*zW_`e0M!8s0RR91
literal 0
HcmV?d00001
--=20
2.25.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 33/33] tests/acpi: add expected blob for VIOT test on virt
machine
Date: Wed, 15 Dec 2021 10:40:49 +0000
Message-Id: <20211215104049.2030475-34-peter.maydell@linaro.org>
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From: Jean-Philippe Brucker <jean-philippe@linaro.org>
The VIOT blob contains the following:
[000h 0000 4] Signature : "VIOT" [Virtual I/O Trans=
lation Table]
[004h 0004 4] Table Length : 00000058
[008h 0008 1] Revision : 00
[009h 0009 1] Checksum : 66
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 2] Node count : 0002
[026h 0038 2] Node offset : 0030
[028h 0040 8] Reserved : 0000000000000000
[030h 0048 1] Type : 03 [VirtIO-PCI IOMMU]
[031h 0049 1] Reserved : 00
[032h 0050 2] Length : 0010
[034h 0052 2] PCI Segment : 0000
[036h 0054 2] PCI BDF number : 0008
[038h 0056 8] Reserved : 0000000000000000
[040h 0064 1] Type : 01 [PCI Range]
[041h 0065 1] Reserved : 00
[042h 0066 2] Length : 0018
[044h 0068 4] Endpoint start : 00000000
[048h 0072 2] PCI Segment start : 0000
[04Ah 0074 2] PCI Segment end : 0000
[04Ch 0076 2] PCI BDF start : 0000
[04Eh 0078 2] PCI BDF end : 00FF
[050h 0080 2] Output node : 0030
[052h 0082 6] Reserved : 000000000000
Acked-by: Ani Sinha <ani@anisinha.ca>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-9-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
tests/data/acpi/virt/VIOT | Bin 0 -> 88 bytes
2 files changed, 1 deletion(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios=
-tables-test-allowed-diff.h
index 8367ffe1d40..dfb8523c8bf 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/virt/VIOT",
diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..921f40d88c28ba2171a4d664e11=
9914335309e7d 100644
GIT binary patch
literal 88
zcmWIZ^bd((0D?3pe`k+i1*eDrX9XZ&1PX!JAexE60Hgv8m>C3sGzXN&z`)2L0cSHX
I{D-Rq0Q5fy0RR91
literal 0
HcmV?d00001
--=20
2.25.1