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[83.50.185.174]) by smtp.gmail.com with ESMTPSA id u13sm9389401wmq.14.2021.12.13.10.56.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Dec 2021 10:56:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mbs0XnxAH9XZ1rqWsX8q/JBDekNQiMIH/00Vs+Bfjx8=; b=JFKS5mQHN8821VaJhUAUg/Dzr0jAK/sNb+RHEnD9SZVivZKJB2+3D8XngGmUWi8kB2 vBi3s0+X2mchW/kWth3ftHP0diuDeT0fmrXHGeqOCZv+KWaqKMQ+g/9Bd8kTFDdqcKOj gqtan/MLrEmCnePaf4E+VBkZCWORnTSzYHjYOuxLaKGWFD72jRqUMEGVVrd6MJN/pswW dJlojhT5uZ8M73ZHZRLK3m3plUaFUxkKWgF1JH8LB6ZanXvLr2K31EEoHCykghYFdNBS OQCS/28LBbjLj3VtiZDoOcRxzlrjgnHpMppyp2zS5QZeJrlimwtSIQuJHxb8I7g5U0Rh WDng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=mbs0XnxAH9XZ1rqWsX8q/JBDekNQiMIH/00Vs+Bfjx8=; b=5tHqAfPf/oBEOeRKepbEcRn/BexBXMcBxkfq6oiEz+98VkaYYj+whzA9vDVSo4plzI sdgdF3lALp0tixbpBeLfr5VA+ebSExPXS6ARSZ3l7fs0KPTDJc1i9Cl0J0781yswxgtc DV+Sdfwm2uYU0Rplt7qC7WLDJvR9H/Pfx1oKavsN5km8opZIhLiNrELTF19jt3CllYA+ kG0wUTrhSmbsa34JRCBfAx4IlmAmZ+sa4Ua0St8xTSaZi9vCAjhLiKHtXhpWWDgNMt8j OBzwdyQyD7bvLjn+VbHskAxj2nkzI/GQI+isOjN9PPHKqXhllfBSi+UXdahFuFRihMTM 2y/w== X-Gm-Message-State: AOAM5335JUzmS5s8bulWEjVP2qBJ39KOij+z43SjzO10E30OTDBFjUH1 t0XxJf3iBoz6DjS5UXVDaAg= X-Google-Smtp-Source: ABdhPJwnzGyngdYa0UAmNr3GfJPhDslH89Ek9Dzb5gFTxrWBj6Fq0SmpmHkP4VwrwzB7/tlM+8a2KQ== X-Received: by 2002:a7b:c155:: with SMTP id z21mr39315256wmi.107.1639421782208; Mon, 13 Dec 2021 10:56:22 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Helge Deller , Richard Henderson , Sven Schnelle Subject: [PATCH v2 2/2] target/hppa: Fix deposit assert from trans_shrpw_imm Date: Mon, 13 Dec 2021 19:56:10 +0100 Message-Id: <20211213185610.1987974-3-f4bug@amsat.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211213185610.1987974-1-f4bug@amsat.org> References: <20211213185610.1987974-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1639421785822100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Because sa may be 0, tcg_gen_deposit_reg(dest, t0, cpu_gr[a->r1], 32 - sa, sa); may attempt a zero-width deposit at bit 32, which will assert for TARGET_REGISTER_BITS =3D=3D 32. Use the newer extract2 when possible, which itself includes the rotri special case; otherwise mirror the code from trans_shrpw_sar, using concat and shri. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/635 Signed-off-by: Richard Henderson Message-Id: <20211213174248.29222-1-richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/hppa/translate.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 261e4c75c7c..952027a28e1 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -140,6 +140,7 @@ #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64 #define tcg_gen_extract_reg tcg_gen_extract_i64 #define tcg_gen_sextract_reg tcg_gen_sextract_i64 +#define tcg_gen_extract2_reg tcg_gen_extract2_i64 #define tcg_const_reg tcg_const_i64 #define tcg_const_local_reg tcg_const_local_i64 #define tcg_constant_reg tcg_constant_i64 @@ -234,6 +235,7 @@ #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32 #define tcg_gen_extract_reg tcg_gen_extract_i32 #define tcg_gen_sextract_reg tcg_gen_sextract_i32 +#define tcg_gen_extract2_reg tcg_gen_extract2_i32 #define tcg_const_reg tcg_const_i32 #define tcg_const_local_reg tcg_const_local_i32 #define tcg_constant_reg tcg_constant_i32 @@ -3206,6 +3208,8 @@ static bool trans_shrpw_imm(DisasContext *ctx, arg_sh= rpw_imm *a) t2 =3D load_gpr(ctx, a->r2); if (a->r1 =3D=3D 0) { tcg_gen_extract_reg(dest, t2, sa, 32 - sa); + } else if (TARGET_REGISTER_BITS =3D=3D 32) { + tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa); } else if (a->r1 =3D=3D a->r2) { TCGv_i32 t32 =3D tcg_temp_new_i32(); tcg_gen_trunc_reg_i32(t32, t2); @@ -3213,10 +3217,11 @@ static bool trans_shrpw_imm(DisasContext *ctx, arg_= shrpw_imm *a) tcg_gen_extu_i32_reg(dest, t32); tcg_temp_free_i32(t32); } else { - TCGv_reg t0 =3D tcg_temp_new(); - tcg_gen_extract_reg(t0, t2, sa, 32 - sa); - tcg_gen_deposit_reg(dest, t0, cpu_gr[a->r1], 32 - sa, sa); - tcg_temp_free(t0); + TCGv_i64 t64 =3D tcg_temp_new_i64(); + tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]); + tcg_gen_shri_i64(t64, t64, sa); + tcg_gen_trunc_i64_reg(dest, t64); + tcg_temp_free_i64(t64); } save_gpr(ctx, a->t, dest); =20 --=20 2.33.1