From nobody Tue Feb 10 12:59:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163939788355135.349070176622604; Mon, 13 Dec 2021 04:18:03 -0800 (PST) Received: from localhost ([::1]:53950 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mwkHK-0004ns-Ij for importer@patchew.org; Mon, 13 Dec 2021 07:18:02 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58742) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mwkAP-0006x9-1J; Mon, 13 Dec 2021 07:10:53 -0500 Received: from [201.28.113.2] (port=36754 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mwkAN-0008FP-Bt; Mon, 13 Dec 2021 07:10:52 -0500 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Mon, 13 Dec 2021 09:10:39 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id 6ADC9800A5A; Mon, 13 Dec 2021 09:10:39 -0300 (-03) From: Victor Colombo To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v2 1/4] target/ppc: Fix xs{max, min}[cj]dp to use VSX registers Date: Mon, 13 Dec 2021 09:09:55 -0300 Message-Id: <20211213120958.24443-2-victor.colombo@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211213120958.24443-1-victor.colombo@eldorado.org.br> References: <20211213120958.24443-1-victor.colombo@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 13 Dec 2021 12:10:39.0833 (UTC) FILETIME=[71B6A490:01D7F01A] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=victor.colombo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: danielhb413@gmail.com, richard.henderson@linaro.org, groug@kaod.org, victor.colombo@eldorado.org.br, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1639397885083100001 Content-Type: text/plain; charset="utf-8" PPC instruction xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are using vector registers when they should be using VSX ones. This happens because the instructions are using GEN_VSX_HELPER_R3, which adds 32 to the register numbers, effectively making them vector registers. This patch fixes it by changing these instructions to use GEN_VSX_HELPER_X3. Reviewed-by: Richard Henderson Signed-off-by: Victor Colombo --- target/ppc/fpu_helper.c | 4 ++-- target/ppc/helper.h | 8 ++++---- target/ppc/translate/vsx-impl.c.inc | 8 ++++---- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index c4896cecc8..ad41ef1606 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2420,7 +2420,7 @@ VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i)) VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i)) =20 #define VSX_MAX_MINC(name, max) = \ -void helper_##name(CPUPPCState *env, uint32_t opcode, = \ +void helper_##name(CPUPPCState *env, = \ ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) = \ { = \ ppc_vsr_t t =3D *xt; = \ @@ -2455,7 +2455,7 @@ VSX_MAX_MINC(xsmaxcdp, 1); VSX_MAX_MINC(xsmincdp, 0); =20 #define VSX_MAX_MINJ(name, max) = \ -void helper_##name(CPUPPCState *env, uint32_t opcode, = \ +void helper_##name(CPUPPCState *env, = \ ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) = \ { = \ ppc_vsr_t t =3D *xt; = \ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 627811cefc..12a3d5f269 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -392,10 +392,10 @@ DEF_HELPER_4(xscmpoqp, void, env, i32, vsr, vsr) DEF_HELPER_4(xscmpuqp, void, env, i32, vsr, vsr) DEF_HELPER_4(xsmaxdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xsmindp, void, env, vsr, vsr, vsr) -DEF_HELPER_5(xsmaxcdp, void, env, i32, vsr, vsr, vsr) -DEF_HELPER_5(xsmincdp, void, env, i32, vsr, vsr, vsr) -DEF_HELPER_5(xsmaxjdp, void, env, i32, vsr, vsr, vsr) -DEF_HELPER_5(xsminjdp, void, env, i32, vsr, vsr, vsr) +DEF_HELPER_4(xsmaxcdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsmincdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsmaxjdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsminjdp, void, env, vsr, vsr, vsr) DEF_HELPER_3(xscvdphp, void, env, vsr, vsr) DEF_HELPER_4(xscvdpqp, void, env, i32, vsr, vsr) DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr) diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx= -impl.c.inc index c0e38060b4..02df75339e 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -1098,10 +1098,10 @@ GEN_VSX_HELPER_R2_AB(xscmpoqp, 0x04, 0x04, 0, PPC2_= VSX) GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX) -GEN_VSX_HELPER_R3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300) -GEN_VSX_HELPER_R3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300) -GEN_VSX_HELPER_R3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300) -GEN_VSX_HELPER_R3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300) --=20 2.25.1