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[83.50.185.174]) by smtp.gmail.com with ESMTPSA id x13sm10419767wrr.47.2021.12.13.02.23.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Dec 2021 02:23:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=d5gjd7DkXzFFar/87LfemtzCmDf71l2zjA4L0nnmEjE=; b=F7vxifWg+DWYnJC/9tgbXC4ggFouOTsTUAg8ktrNJYYVRhjC4RZDK9drxyclWvH9lQ m4daYx2V1p+t2JcCWyEstfbWH3eXBCBXLic/p+JgHZmovuceySV9KNDRbzIU4oWC7hPx J4NxSsj8ZkBZY7TmfU/vvWU4Owxhpu5wVJqa2pCIkh4/+75kuIQNYsWIkCOdVawsOarA Y72ojQAJGwcTclW90BGdfbc+v2brl9NMQrzNxvQ8BYIejAqvKwMAw+UbchUkqY1M9rvD LI8O6MroShNX/g9oO04NFs3kOtrPy4YBrPFT9l5VqeAEqfdvOIipBMD1YxePdXEJ/pnd PiMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=d5gjd7DkXzFFar/87LfemtzCmDf71l2zjA4L0nnmEjE=; b=2SHq9a1u0J5sKy9Xxbl+Nj4lvSkNjPspjS2tzK2AVYI2ke36IecPqZ7qz6/hdvYjZP 8wcSckxqcjr2Fe/9RkCnqPRObbhGUWhWhbFLdhlL4c1UFo5IdrhuEDOHI4rgVWceSTI6 VLTniRrSgcpaoSzl4uo23vcmvGILiVDuYQeNXGD4d66Lxfo+tKYIGmvBe7XLD2+aDQ5m IJJ1gZa0paIRD9X1VqONdRGiVZmFAWtH72i/fagIkTEL2Ktgpaj39NhGu7NylZyjZE8K CJGgpdcvJNi6PgGFGwf24aHvgMovsVrxnaFPpaud/wxbdt+c1TsjggiuM9ipqQ1U/p3k mmlQ== X-Gm-Message-State: AOAM530e9hGpPj8gS4AcN8FvG4vvEnqF8s2TucMY16ls8ycFGgy28rtu wl2PVmYJ0oJ/yJdIze5ssQI= X-Google-Smtp-Source: ABdhPJyrzu9UjLrKPOIN3d1SbY21zr8Z6VbIoxGp392Yde8p95syaCVdmMUMic/OXejQIDc5v++hAw== X-Received: by 2002:a1c:7418:: with SMTP id p24mr36173717wmc.71.1639391022157; Mon, 13 Dec 2021 02:23:42 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Simon Burge , Jiaxun Yang Subject: [PATCH] target/mips: Remove duplicated MIPSCPU::cp0_count_rate Date: Mon, 13 Dec 2021 11:23:40 +0100 Message-Id: <20211213102340.1847248-1-f4bug@amsat.org> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1639391026044100002 Since the previous commit 9ea89876f9d ("target/mips: Fix cycle counter timing calculations"), MIPSCPU::cp0_count_rate is not used anymore. We don't need it since it is already expressed as mips_def_t::CCRes. Remove the duplicate and clean. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- Based-on: <20211116072606.BE9C8A1856@thoreau.thistledown.com.au> --- target/mips/cpu.h | 9 --------- target/mips/internal.h | 9 +++++++++ target/mips/cpu.c | 10 ---------- 3 files changed, 9 insertions(+), 19 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 56b1cbd091d..ea66b866c69 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1168,7 +1168,6 @@ struct CPUMIPSState { * @env: #CPUMIPSState * @clock: this CPU input clock (may be connected * to an output clock from another device). - * @cp0_count_rate: rate at which the coprocessor 0 counter increments * * A MIPS CPU. */ @@ -1180,14 +1179,6 @@ struct MIPSCPU { Clock *clock; CPUNegativeOffsetState neg; CPUMIPSState env; - /* - * The Count register acts as a timer, incrementing at a constant rate, - * whether or not an instruction is executed, retired, or any forward - * progress is made through the pipeline. The rate at which the counter - * increments is implementation dependent, and is a function of the - * pipeline clock of the processor, not the issue width of the process= or. - */ - unsigned cp0_count_rate; }; =20 =20 diff --git a/target/mips/internal.h b/target/mips/internal.h index daddb05fd43..1526fb880da 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -46,6 +46,15 @@ struct mips_def_t { target_ulong CP0_LLAddr_rw_bitmask; int CP0_LLAddr_shift; int32_t SYNCI_Step; + /* + * @CCRes: rate at which the coprocessor 0 counter increments + * + * The Count register acts as a timer, incrementing at a constant rate, + * whether or not an instruction is executed, retired, or any forward + * progress is made through the pipeline. The rate at which the counter + * increments is implementation dependent, and is a function of the + * pipeline clock of the processor, not the issue width of the process= or. + */ int32_t CCRes; int32_t CP0_Status_rw_bitmask; int32_t CP0_TCStatus_rw_bitmask; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 0766e256931..af287177d5a 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -434,13 +434,11 @@ static void mips_cpu_disas_set_info(CPUState *s, disa= ssemble_info *info) * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz. */ #define CPU_FREQ_HZ_DEFAULT 200000000 -#define CP0_COUNT_RATE_DEFAULT 2 =20 static void mips_cp0_period_set(MIPSCPU *cpu) { CPUMIPSState *env =3D &cpu->env; =20 - /* env->CCRes isn't initialised this early, use env->cpu_model->CCRes.= */ env->cp0_count_ns =3D clock_ticks_to_ns(MIPS_CPU(cpu)->clock, env->cpu_model->CCRes); assert(env->cp0_count_ns); @@ -515,13 +513,6 @@ static ObjectClass *mips_cpu_class_by_name(const char = *cpu_model) return oc; } =20 -static Property mips_cpu_properties[] =3D { - /* CP0 timer running at half the clock of the CPU */ - DEFINE_PROP_UINT32("cp0-count-rate", MIPSCPU, cp0_count_rate, - CP0_COUNT_RATE_DEFAULT), - DEFINE_PROP_END_OF_LIST() -}; - #ifndef CONFIG_USER_ONLY #include "hw/core/sysemu-cpu-ops.h" =20 @@ -561,7 +552,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset); - device_class_set_props(dc, mips_cpu_properties); =20 cc->class_by_name =3D mips_cpu_class_by_name; cc->has_work =3D mips_cpu_has_work; --=20 2.33.1