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From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Subject: [PATCH v5 03/23] target/riscv: Implement hgeie and hgeip CSRs Date: Sat, 11 Dec 2021 09:48:57 +0530 Message-Id: <20211211041917.135345-4-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211211041917.135345-1-anup.patel@wdc.com> References: <20211211041917.135345-1-anup.patel@wdc.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MA1PR0101CA0041.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:22::27) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f6271c4d-dbbd-4378-40e6-08d9bc5d81bb X-MS-TrafficTypeDiagnostic: CO1PR04MB8265:EE_ X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OBV2ojZG+pzSr3NqYtHYiusIOJeIe+w3D2aI5WIdj56/BmnIWqV6T+D2rKC+MfZ+QWhLlEibvfZEkrsW/UsFWjQ+6KHQ7J2XC6z9A+JBf1B2mBJT55OUDn30R9in1gKqw14ZgEEIMDwObqwWsUxsohmup/8rx//4R37a4SUaDN1AhBho+t5OnxVn2F3kBf8lnCD0beaZOYn0qFO4yHfxeOBNV47aC/uJFda2KXT8jTB3mwQt4C0duI9oRmdQbp0SvOr0C16iJncFV8FdXssuW6FGGuuSaBqRVHLTUfK7qHsFEB39DgLBWSJiLp8s7Kkqrgb5bZ9lR/0OgnxfqlXOrOlarkL4CT7fxNxvVhY7vWZqubdhVOOaE367kfIRYl7YTngY7I7Lubx9fC/EB93pKTV3g7auexK5xq4MdcGj0HXjShB/u2fI7D/tQXd4ikd++dR1+FTBfDK8irMn9wH2jhKn41r2s1qSQfOAdX1p1H+mME4hMLUrqFRagbHx0nayzsMoPCHvTWCq45MHOxUXxDoI6K03yLazlD5XE6S7bx5nElc4KX+Kog7nvxuIfkDZ5k8BjBYSuk+xWAEts6yZvOj2ptsnA91XlB4/O98Ejggn7cCAHCvVI9POF8lV3pGvuPXM1OLCGKGWP4G4QCUbGrRdTbu4OOnxjGPO3oYZTR5M/US/6zTG0n+M/E+x7Dm6+EFF+78pULv0Y+PxGak8IQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=972e533d7=Anup.Patel@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Anup Patel , Anup Patel , qemu-devel@nongnu.org, Alistair Francis , Atish Patra , Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @sharedspace.onmicrosoft.com) X-ZM-MESSAGEID: 1639196519972100005 Content-Type: text/plain; charset="utf-8" The hgeie and hgeip CSRs are required for emulating an external interrupt controller capable of injecting virtual external interrupt to Guest/VM running at VS-level. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 61 ++++++++++++++++++++++++++++----------- target/riscv/cpu.h | 5 ++++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 37 ++++++++++++++++++++++-- target/riscv/csr.c | 43 ++++++++++++++++++--------- target/riscv/machine.c | 6 ++-- 6 files changed, 118 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f3b1b9a775..da58a9654f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -582,23 +582,49 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) static void riscv_cpu_set_irq(void *opaque, int irq, int level) { RISCVCPU *cpu =3D RISCV_CPU(opaque); + CPURISCVState *env =3D &cpu->env; =20 - switch (irq) { - case IRQ_U_SOFT: - case IRQ_S_SOFT: - case IRQ_VS_SOFT: - case IRQ_M_SOFT: - case IRQ_U_TIMER: - case IRQ_S_TIMER: - case IRQ_VS_TIMER: - case IRQ_M_TIMER: - case IRQ_U_EXT: - case IRQ_S_EXT: - case IRQ_VS_EXT: - case IRQ_M_EXT: - riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); - break; - default: + if (irq < IRQ_LOCAL_MAX) { + switch (irq) { + case IRQ_U_SOFT: + case IRQ_S_SOFT: + case IRQ_VS_SOFT: + case IRQ_M_SOFT: + case IRQ_U_TIMER: + case IRQ_S_TIMER: + case IRQ_VS_TIMER: + case IRQ_M_TIMER: + case IRQ_U_EXT: + case IRQ_S_EXT: + case IRQ_VS_EXT: + case IRQ_M_EXT: + riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); + break; + default: + g_assert_not_reached(); + } + } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { + /* Require H-extension for handling guest local interrupts */ + if (!riscv_has_ext(env, RVH)) { + g_assert_not_reached(); + } + + /* Compute bit position in HGEIP CSR */ + irq =3D irq - IRQ_LOCAL_MAX + 1; + if (env->geilen < irq) { + g_assert_not_reached(); + } + + /* Update HGEIP CSR */ + env->hgeip &=3D ~((target_ulong)1 << irq); + if (level) { + env->hgeip |=3D (target_ulong)1 << irq; + } + + /* Update mip.SGEIP bit */ + riscv_cpu_update_mip(cpu, MIP_SGEIP, + BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); + } else { g_assert_not_reached(); } } @@ -611,7 +637,8 @@ static void riscv_cpu_init(Object *obj) cpu_set_cpustate_pointers(cpu); =20 #ifndef CONFIG_USER_ONLY - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX); + qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, + IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); #endif /* CONFIG_USER_ONLY */ } =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0760c0af93..92a276f109 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -149,6 +149,7 @@ struct CPURISCVState { target_ulong priv; /* This contains QEMU specific information about the virt state. */ target_ulong virt; + target_ulong geilen; target_ulong resetvec; =20 target_ulong mhartid; @@ -186,6 +187,8 @@ struct CPURISCVState { target_ulong htval; target_ulong htinst; target_ulong hgatp; + target_ulong hgeie; + target_ulong hgeip; uint64_t htimedelta; =20 /* Virtual CSRs */ @@ -350,6 +353,8 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f,= CPUState *cs, int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_fp_enabled(CPURISCVState *env); +target_ulong riscv_cpu_get_geilen(CPURISCVState *env); +void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_two_stage_lookup(int mmu_idx); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index c8ce77b1bb..0c6ef6e51c 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -526,6 +526,7 @@ typedef enum RISCVException { #define IRQ_M_EXT 11 #define IRQ_S_GEXT 12 #define IRQ_LOCAL_MAX 16 +#define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) =20 /* mip masks */ #define MIP_USIP (1 << IRQ_U_SOFT) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9eeed38c7e..bf28118ff5 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -140,7 +140,11 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *= env) target_ulong mstatus_mie =3D get_field(env->mstatus, MSTATUS_MIE); target_ulong mstatus_sie =3D get_field(env->mstatus, MSTATUS_SIE); =20 - target_ulong pending =3D env->mip & env->mie; + target_ulong vsgemask =3D + (target_ulong)1 << get_field(env->hstatus, HSTATUS_VGEIN); + target_ulong vsgein =3D (env->hgeip & vsgemask) ? MIP_VSEIP : 0; + + target_ulong pending =3D (env->mip | vsgein) & env->mie; =20 target_ulong mie =3D env->priv < PRV_M || (env->priv =3D=3D PRV_M && mstatus_mie); @@ -247,6 +251,28 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) } } =20 +target_ulong riscv_cpu_get_geilen(CPURISCVState *env) +{ + if (!riscv_has_ext(env, RVH)) { + return 0; + } + + return env->geilen; +} + +void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) +{ + if (!riscv_has_ext(env, RVH)) { + return; + } + + if (geilen > (TARGET_LONG_BITS - 1)) { + return; + } + + env->geilen =3D geilen; +} + bool riscv_cpu_virt_enabled(CPURISCVState *env) { if (!riscv_has_ext(env, RVH)) { @@ -290,9 +316,14 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t = mask, uint32_t value) { CPURISCVState *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); - uint32_t old =3D env->mip; + uint32_t gein, vsgein =3D 0, old =3D env->mip; bool locked =3D false; =20 + if (riscv_cpu_virt_enabled(env)) { + gein =3D get_field(env->hstatus, HSTATUS_VGEIN); + vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; + } + if (!qemu_mutex_iothread_locked()) { locked =3D true; qemu_mutex_lock_iothread(); @@ -300,7 +331,7 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t m= ask, uint32_t value) =20 env->mip =3D (env->mip & ~mask) | (value & mask); =20 - if (env->mip) { + if (env->mip | vsgein) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 56e8d35217..e5234a1964 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -803,7 +803,7 @@ static RISCVException rmw_mip(CPURISCVState *env, int c= srno, RISCVCPU *cpu =3D env_archcpu(env); /* Allow software control of delegable interrupts not claimed by hardw= are */ target_ulong mask =3D write_mask & delegable_ints & ~env->miclaim; - uint32_t old_mip; + uint32_t gin, old_mip; =20 if (mask) { old_mip =3D riscv_cpu_update_mip(cpu, mask, (new_value & mask)); @@ -811,6 +811,11 @@ static RISCVException rmw_mip(CPURISCVState *env, int = csrno, old_mip =3D env->mip; } =20 + if (csrno !=3D CSR_HVIP) { + gin =3D get_field(env->hstatus, HSTATUS_VGEIN); + old_mip |=3D (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP := 0; + } + if (ret_value) { *ret_value =3D old_mip; } @@ -973,7 +978,7 @@ static RISCVException rmw_vsip(CPURISCVState *env, int = csrno, target_ulong new_value, target_ulong write_= mask) { /* Shift the S bits to their VS bit location in mip */ - int ret =3D rmw_mip(env, 0, ret_value, new_value << 1, + int ret =3D rmw_mip(env, csrno, ret_value, new_value << 1, (write_mask << 1) & vsip_writable_mask & env->hidele= g); =20 if (ret_value) { @@ -993,7 +998,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int c= srno, if (riscv_cpu_virt_enabled(env)) { ret =3D rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); } else { - ret =3D rmw_mip(env, CSR_MSTATUS, ret_value, new_value, + ret =3D rmw_mip(env, csrno, ret_value, new_value, write_mask & env->mideleg & sip_writable_mask); } =20 @@ -1112,7 +1117,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, in= t csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_= mask) { - int ret =3D rmw_mip(env, 0, ret_value, new_value, + int ret =3D rmw_mip(env, csrno, ret_value, new_value, write_mask & hvip_writable_mask); =20 if (ret_value) { @@ -1125,7 +1130,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int= csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_m= ask) { - int ret =3D rmw_mip(env, 0, ret_value, new_value, + int ret =3D rmw_mip(env, csrno, ret_value, new_value, write_mask & hip_writable_mask); =20 if (ret_value) { @@ -1162,15 +1167,27 @@ static RISCVException write_hcounteren(CPURISCVStat= e *env, int csrno, return RISCV_EXCP_NONE; } =20 -static RISCVException write_hgeie(CPURISCVState *env, int csrno, - target_ulong val) +static RISCVException read_hgeie(CPURISCVState *env, int csrno, + target_ulong *val) { if (val) { - qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + *val =3D env->hgeie; } return RISCV_EXCP_NONE; } =20 +static RISCVException write_hgeie(CPURISCVState *env, int csrno, + target_ulong val) +{ + /* Only GEILEN:1 bits implemented and BIT0 is never implemented */ + val &=3D ((((target_ulong)1) << env->geilen) - 1) << 1; + env->hgeie =3D val; + /* Update mip.SGEIP bit */ + riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP, + BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); + return RISCV_EXCP_NONE; +} + static RISCVException read_htval(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1198,11 +1215,11 @@ static RISCVException write_htinst(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 -static RISCVException write_hgeip(CPURISCVState *env, int csrno, - target_ulong val) +static RISCVException read_hgeip(CPURISCVState *env, int csrno, + target_ulong *val) { if (val) { - qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + *val =3D env->hgeip; } return RISCV_EXCP_NONE; } @@ -1891,10 +1908,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_HIP] =3D { "hip", hmode, NULL, NULL, rmw_= hip }, [CSR_HIE] =3D { "hie", hmode, read_hie, writ= e_hie }, [CSR_HCOUNTEREN] =3D { "hcounteren", hmode, read_hcounteren, writ= e_hcounteren }, - [CSR_HGEIE] =3D { "hgeie", hmode, read_zero, writ= e_hgeie }, + [CSR_HGEIE] =3D { "hgeie", hmode, read_hgeie, writ= e_hgeie }, [CSR_HTVAL] =3D { "htval", hmode, read_htval, writ= e_htval }, [CSR_HTINST] =3D { "htinst", hmode, read_htinst, writ= e_htinst }, - [CSR_HGEIP] =3D { "hgeip", hmode, read_zero, writ= e_hgeip }, + [CSR_HGEIP] =3D { "hgeip", hmode, read_hgeip, NULL= }, [CSR_HGATP] =3D { "hgatp", hmode, read_hgatp, writ= e_hgatp }, [CSR_HTIMEDELTA] =3D { "htimedelta", hmode, read_htimedelta, writ= e_htimedelta }, [CSR_HTIMEDELTAH] =3D { "htimedeltah", hmode32, read_htimedeltah, writ= e_htimedeltah }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ad8248ebfd..76dd0d415c 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -78,8 +78,8 @@ static bool hyper_needed(void *opaque) =20 static const VMStateDescription vmstate_hyper =3D { .name =3D "cpu/hyper", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .needed =3D hyper_needed, .fields =3D (VMStateField[]) { VMSTATE_UINTTL(env.hstatus, RISCVCPU), @@ -89,6 +89,8 @@ static const VMStateDescription vmstate_hyper =3D { VMSTATE_UINTTL(env.htval, RISCVCPU), VMSTATE_UINTTL(env.htinst, RISCVCPU), VMSTATE_UINTTL(env.hgatp, RISCVCPU), + VMSTATE_UINTTL(env.hgeie, RISCVCPU), + VMSTATE_UINTTL(env.hgeip, RISCVCPU), VMSTATE_UINT64(env.htimedelta, RISCVCPU), =20 VMSTATE_UINT64(env.vsstatus, RISCVCPU), --=20 2.25.1