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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1639117620; x=1641709621; bh=6wAGSI6QUZs5W11re+ UV7WaEUxAjGogCqsZ8UfXLz34=; b=GBTW1AjyFy/YqvqYJxukhcJ8Eom3ttXvIW 1fT5+G6MFyTJRdIwn1YxYOhAEq5XlEDJzFk28yDOkKd6fX/oHoe5qbD11oLNBfVh C/FlFRmRrqb0noovCH722LrHCwoDrVdz5HcrP99cuA6xiBMXzbqLMJzgIoembv0i kBROm9teEvZIl8SvYxpEX0KOC+6GcwXv8rU/xvzvf1Urhu6jt8wDI/1HnkGXlOZQ ZvZKXMTF4qeR0AqKhZBbJtTY0L+mIWPj0BJ/ikIn3USq6LmMRpAdsl58uYxmgofI rY3gsZNnXZYSLufNxBpSkDpYaCBjK+0nA83wqOeAwQbwIhvA/26A== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair Francis , palmer@dabbelt.com, alistair23@gmail.com, Bin Meng , bmeng.cn@gmail.com Subject: [PATCH 1/2] target/riscv: Set the opcode in DisasContext Date: Fri, 10 Dec 2021 16:26:37 +1000 Message-Id: <20211210062638.824672-2-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211210062638.824672-1-alistair.francis@opensource.wdc.com> References: <20211210062638.824672-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: permerror (zohomail.com: Error in processing SPF Record) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=9719c98f0=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1639118138976100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1d57bc97b5..24251bc8cc 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -586,6 +586,7 @@ static void decode_opc(CPURISCVState *env, DisasContext= *ctx, uint16_t opcode) if (!has_ext(ctx, RVC)) { gen_exception_illegal(ctx); } else { + ctx->opcode =3D opcode; ctx->pc_succ_insn =3D ctx->base.pc_next + 2; if (!decode_insn16(ctx, opcode)) { gen_exception_illegal(ctx); @@ -596,6 +597,7 @@ static void decode_opc(CPURISCVState *env, DisasContext= *ctx, uint16_t opcode) opcode32 =3D deposit32(opcode32, 16, 16, translator_lduw(env, &ctx->base, ctx->base.pc_next + 2)); + ctx->opcode =3D opcode32; ctx->pc_succ_insn =3D ctx->base.pc_next + 4; if (!decode_insn32(ctx, opcode32)) { gen_exception_illegal(ctx); --=20 2.31.1 From nobody Mon Feb 9 12:28:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=permerror (zohomail.com: Error in processing SPF Record) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1639118662184619.8495935148934; Thu, 9 Dec 2021 22:44:22 -0800 (PST) Received: from localhost ([::1]:42940 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mvZdk-000484-LR for importer@patchew.org; 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s=dkim; t=1639117625; x=1641709626; bh=ULrWoIzf+Nv3eSfqER 7vaO5dGa9cRP9lkwCIvaxZ/Qc=; b=P0LZhOiO37QbIfcuK0WCg02nD08q4uwAS6 vAEW2dYwBSbQJ+QXZaRQBlwVQZooU/Lc5zpOqC3sisuXb67dO82hD37HITGsBi4z VkHWmzLmtLjkWdrTBzj/yxvWQDWoMS+5IQDAVcifKX3sX7TLfaE/UT9gp9P+2vkg TxTv7L3zSET609kzka//0jyZNKVmRJEM5efR7C/CsBE7a5/ByNDNer4FRd4ykVJx Sgake78sTBmYWGYsj2haefqLEWncUdyFz0l9nWr/EqLkECM8UYMJ/yWD3rTZK9wF pymhmrtQuv6fnXV5mxUjmo7sbxXU8S/PBCLiJwJXRIXNmjqi9wEQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair Francis , palmer@dabbelt.com, alistair23@gmail.com, Bin Meng , bmeng.cn@gmail.com Subject: [PATCH 2/2] target/riscv: Implement the stval/mtval illegal instruction Date: Fri, 10 Dec 2021 16:26:38 +1000 Message-Id: <20211210062638.824672-3-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211210062638.824672-1-alistair.francis@opensource.wdc.com> References: <20211210062638.824672-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: permerror (zohomail.com: Error in processing SPF Record) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=9719c98f0=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1639118664481100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis The stval and mtval registers can optionally contain the faulting instruction on an illegal instruction exception. This patch adds support for setting the stval and mtval registers based on the CPU feature. Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 25 +++++++++++-------------- target/riscv/translate.c | 3 +++ 3 files changed, 16 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0760c0af93..3a163b57ed 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -127,6 +127,8 @@ struct CPURISCVState { target_ulong frm; =20 target_ulong badaddr; + uint32_t bins; + target_ulong guest_phys_fault_addr; =20 target_ulong priv_ver; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9eeed38c7e..cb5833a6d2 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -975,7 +975,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool async =3D !!(cs->exception_index & RISCV_EXCP_INT_FLAG); target_ulong cause =3D cs->exception_index & RISCV_EXCP_INT_MASK; target_ulong deleg =3D async ? env->mideleg : env->medeleg; - bool write_tval =3D false; target_ulong tval =3D 0; target_ulong htval =3D 0; target_ulong mtval2 =3D 0; @@ -1004,9 +1003,11 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_INST_PAGE_FAULT: case RISCV_EXCP_LOAD_PAGE_FAULT: case RISCV_EXCP_STORE_PAGE_FAULT: - write_tval =3D true; tval =3D env->badaddr; break; + case RISCV_EXCP_ILLEGAL_INST: + tval =3D env->bins; + break; default: break; } @@ -1041,17 +1042,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_has_ext(env, RVH)) { target_ulong hdeleg =3D async ? env->hideleg : env->hedeleg; =20 - if (env->two_stage_lookup && write_tval) { - /* - * If we are writing a guest virtual address to stval, set - * this to 1. If we are trapping to VS we will set this to= 0 - * later. - */ - env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, 1); - } else { - /* For other HS-mode traps, we set this to 0. */ - env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, 0); - } + env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, 0); =20 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { /* Trap to VS mode */ @@ -1063,7 +1054,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) cause =3D=3D IRQ_VS_EXT) { cause =3D cause - 1; } - env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, 0); } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ riscv_cpu_swap_hypervisor_regs(env); @@ -1071,6 +1061,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->priv); env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, riscv_cpu_virt_enabled(env)); + if (tval) { + /* + * If we are writing a guest virtual address to stval,= set + * this to 1. + */ + env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, = 1); + } =20 htval =3D env->guest_phys_fault_addr; =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 24251bc8cc..921ca06bf9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -167,6 +167,9 @@ static void generate_exception_mtval(DisasContext *ctx,= int excp) =20 static void gen_exception_illegal(DisasContext *ctx) { + tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, + offsetof(CPURISCVState, bins)); + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); } =20 --=20 2.31.1