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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1639005657837100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 12 +++++++ target/arm/internals.h | 2 ++ target/arm/cpu64.c | 2 ++ target/arm/helper.c | 80 +++++++++++++++++++++++++++++++++++------- 4 files changed, 83 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3149000004..379585352b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4283,6 +4283,18 @@ static inline bool isar_feature_aa64_i8mm(const ARMI= SARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) !=3D 0; } =20 +static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) +{ + return sextract64(id->id_aa64mmfr0, + R_ID_AA64MMFR0_TGRAN4_SHIFT, + R_ID_AA64MMFR0_TGRAN4_LENGTH) >=3D 1; +} + +static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *i= d) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >=3D 2; +} + static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) !=3D 0; diff --git a/target/arm/internals.h b/target/arm/internals.h index 3e801833b4..868cae2a55 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1033,12 +1033,14 @@ static inline uint32_t aarch64_pstate_valid_mask(co= nst ARMISARegisters *id) typedef struct ARMVAParameters { unsigned tsz : 8; unsigned ps : 3; + unsigned sh : 2; unsigned select : 1; bool tbi : 1; bool epd : 1; bool hpd : 1; bool using16k : 1; bool using64k : 1; + bool ds : 1; } ARMVAParameters; =20 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3bb79ca744..5a1940aa94 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -740,6 +740,8 @@ static void aarch64_max_initfn(Object *obj) =20 t =3D cpu->isar.id_aa64mmfr0; t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bit= s */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* FEAT_LPA2: 52 bi= ts */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* FEAT_LPA2: 52 bi= ts */ cpu->isar.id_aa64mmfr0 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; diff --git a/target/arm/helper.c b/target/arm/helper.c index e39c1f5b3a..f4a8b37f98 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11008,8 +11008,13 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool i= s_aa64, int level, const int grainsize =3D stride + 3; int startsizecheck; =20 - /* Negative levels are never allowed. */ - if (level < 0) { + /* + * Negative levels are usually not allowed... + * Except for FEAT_LPA2, 4k page table, 52-bit address space, which + * begins with level -1. Note that previous feature tests will have + * eliminated this combination if it is not enabled. + */ + if (level < (inputsize =3D=3D 52 && stride =3D=3D 9 ? -1 : 0)) { return false; } =20 @@ -11150,8 +11155,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, ARMMMUIdx mmu_idx, bool data) { uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; - bool epd, hpd, using16k, using64k; - int select, tsz, tbi, ps; + bool epd, hpd, using16k, using64k, ds; + int select, tsz, tbi, ps, sh; =20 if (!regime_has_2_ranges(mmu_idx)) { select =3D 0; @@ -11165,7 +11170,9 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, hpd =3D extract32(tcr, 24, 1); } epd =3D false; + sh =3D extract64(tcr, 12, 2); ps =3D extract64(tcr, 16, 3); + ds =3D extract64(tcr, 32, 1); } else { /* * Bit 55 is always between the two regions, and is canonical for @@ -11175,6 +11182,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, if (!select) { tsz =3D extract32(tcr, 0, 6); epd =3D extract32(tcr, 7, 1); + sh =3D extract32(tcr, 12, 2); using64k =3D extract32(tcr, 14, 1); using16k =3D extract32(tcr, 15, 1); hpd =3D extract64(tcr, 41, 1); @@ -11184,9 +11192,11 @@ ARMVAParameters aa64_va_parameters(CPUARMState *en= v, uint64_t va, using64k =3D tg =3D=3D 3; tsz =3D extract32(tcr, 16, 6); epd =3D extract32(tcr, 23, 1); + sh =3D extract32(tcr, 28, 2); hpd =3D extract64(tcr, 42, 1); } ps =3D extract64(tcr, 32, 3); + ds =3D extract64(tcr, 59, 1); } =20 /* Present TBI as a composite with TBID. */ @@ -11199,12 +11209,14 @@ ARMVAParameters aa64_va_parameters(CPUARMState *e= nv, uint64_t va, return (ARMVAParameters) { .tsz =3D tsz, .ps =3D ps, + .sh =3D sh, .select =3D select, .tbi =3D tbi, .epd =3D epd, .hpd =3D hpd, .using16k =3D using16k, .using64k =3D using64k, + .ds =3D ds, }; } =20 @@ -11332,15 +11344,31 @@ static bool get_phys_addr_lpae(CPUARMState *env, = uint64_t address, access_type !=3D MMU_INST_FETCH); level =3D 0; =20 - if (cpu_isar_feature(aa64_st, env_archcpu(env))) { + /* Find the minimum allowed input address size. */ + if (cpu_isar_feature(aa64_st, cpu)) { max_tsz =3D 48 - param.using64k; } + + /* + * Find the maximum allowed input address size. + * DS is RES0 unless FEAT_LPA2 is supported for the given page siz= e; + * adjust param.ds to the effective value of DS, as documented. + */ if (param.using64k) { - if (cpu_isar_feature(aa64_lva, env_archcpu(env))) { + if (cpu_isar_feature(aa64_lva, cpu)) { min_tsz =3D 12; } + param.ds =3D false; + } else if (param.ds) { + /* ??? Assume tgran{4,16}_2 =3D=3D 0, i.e. match tgran{4,16}. = */ + if (param.using16k + ? cpu_isar_feature(aa64_tgran16_lpa2, cpu) + : cpu_isar_feature(aa64_tgran4_lpa2, cpu)) { + min_tsz =3D 12; + } else { + param.ds =3D false; + } } - /* TODO: FEAT_LPA2 */ =20 /* * If TxSZ is programmed to a value larger than the maximum, @@ -11441,10 +11469,19 @@ static bool get_phys_addr_lpae(CPUARMState *env, = uint64_t address, * VTCR_EL2.SL0 field (whose interpretation depends on the page si= ze) */ uint32_t sl0 =3D extract32(tcr->raw_tcr, 6, 2); + uint32_t sl2 =3D extract64(tcr->raw_tcr, 33, 1); uint32_t startlevel; bool ok; =20 - if (!aarch64 || stride =3D=3D 9) { + /* SL2 is RES0 unless DS=3D1 & 4kb granule. */ + if (param.ds && stride =3D=3D 9 && sl2) { + if (sl0 !=3D 0) { + level =3D 0; + fault_type =3D ARMFault_Translation; + goto do_fault; + } + startlevel =3D -1; + } else if (!aarch64 || stride =3D=3D 9) { /* AArch32 or 4KB pages */ startlevel =3D 2 - sl0; =20 @@ -11499,7 +11536,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, * but in ARMv8 they are checked for zero and an AddressSize fault * is raised if they are not. */ - if (aarch64 || arm_feature(env, ARM_FEATURE_V8)) { + if (param.ds) { + descaddrmask =3D MAKE_64BIT_MASK(0, 50); + } else if (aarch64 || arm_feature(env, ARM_FEATURE_V8)) { descaddrmask =3D MAKE_64BIT_MASK(0, 48); } else { descaddrmask =3D MAKE_64BIT_MASK(0, 40); @@ -11534,11 +11573,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, = uint64_t address, =20 /* * For FEAT_LPA and PS=3D6, bits [51:48] of descaddr are in [15:12] - * of descriptor. Otherwise, if descaddr is out of range, raise - * AddressSizeFault. + * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of + * descaddr are in [9:8]. Otherwise, if descaddr is out of range, + * raise AddressSizeFault. */ if (outputsize > 48) { - descaddr |=3D extract64(descriptor, 12, 4) << 48; + if (param.ds) { + descaddr |=3D extract64(descriptor, 8, 2) << 50; + } else { + descaddr |=3D extract64(descriptor, 12, 4) << 48; + } } else if (descaddr >> outputsize) { fault_type =3D ARMFault_AddressSize; goto do_fault; @@ -11632,7 +11676,17 @@ static bool get_phys_addr_lpae(CPUARMState *env, u= int64_t address, assert(attrindx <=3D 7); cacheattrs->attrs =3D extract64(mair, attrindx * 8, 8); } - cacheattrs->shareability =3D extract32(attrs, 6, 2); + + /* + * For FEAT_LPA2 and effective DS, the SH field in the attributes + * was re-purposed for output address bits. The SH attribute in + * that case comes from TCR_ELx, which we extracted earlier. + */ + if (param.ds) { + cacheattrs->shareability =3D param.sh; + } else { + cacheattrs->shareability =3D extract32(attrs, 6, 2); + } =20 *phys_ptr =3D descaddr; *page_size_ptr =3D page_size; --=20 2.25.1