From nobody Sat May 18 06:50:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1638898432; cv=none; d=zohomail.com; s=zohoarc; b=UTdYzVe8SPTjSYTK7Aikh5710fml8w1nxjHj39xV1rSCOPbgguONrAnZUHYEKJ0D4sFdxXw4fAYv1lq81jiDYqkj8rbWIAXzRagNFwfvBwCrEoQasKz0pcDkFiirqMVxxA848JMVbpdEU5PvX2mZJt9rSR8d/5MZmxRxbnFEEPM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1638898432; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WOvboszOk6X+DuFeJ6cNHXTo+LaaTm0H0HRRbAGFH48=; b=nc+zBsIAghmdWnOcNg52x3JkUUxztC+xVgCpp1aqVQ4IV9MxCab0EhTE8lnS2RRR33AQGjqoY2c5ZaYtYgxrVtwYcosauYOUB6F/BAaV7jqiN1jOWfxZYcoWA2m5D7eznm+N1lYghXWEpnHgvT+8dvKkbDz44YIrMy8DkfNQan4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1638898432588393.9305165794832; Tue, 7 Dec 2021 09:33:52 -0800 (PST) Received: from localhost ([::1]:46468 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mueLf-0004nz-IM for importer@patchew.org; Tue, 07 Dec 2021 12:33:51 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46604) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mueDq-0001Cv-I4 for qemu-devel@nongnu.org; Tue, 07 Dec 2021 12:25:46 -0500 Received: from [2a00:1450:4864:20::433] (port=38681 helo=mail-wr1-x433.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mueDk-0002sr-Am for qemu-devel@nongnu.org; Tue, 07 Dec 2021 12:25:44 -0500 Received: by mail-wr1-x433.google.com with SMTP id q3so30981026wru.5 for ; Tue, 07 Dec 2021 09:25:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bg34sm3556060wmb.47.2021.12.07.09.25.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Dec 2021 09:25:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WOvboszOk6X+DuFeJ6cNHXTo+LaaTm0H0HRRbAGFH48=; b=h4Jen9At+PJT8sMmbHiK/swTOF8RVuasfKfSxsINBUuB6clfX369dvF/rjyNojz2lm lk6wbVDFex4go6qQrEuZZDdv+yPUCyTLOVilAPQX4T+2GuROS9Ny536oenjak5lGEiK/ PBIRcHvzmB8w4u0dVNyw4UaxvfpCExcHTXgZw47rZxfcp2b3kAIDojl4WqYt0xTX9hj1 Z4teuj6aUf2+dXJlOo0ma5x+pfXbALUBNW4dsoVb01VP8KBhNz22dm4D692LhpbIxdUJ p6PfrA56qmZac+sL4CgQhQSKZPojI7NnoRgod9+G/9zJLEhRnNBQm9QxPfHR0FSBrXiW ifwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WOvboszOk6X+DuFeJ6cNHXTo+LaaTm0H0HRRbAGFH48=; b=PGwigDsdljDjErojHUY5vOdm7FMG2KhmB06HdEr7pAHiP1f1ACp0veqL7BFxiqMDul aLZtfvK3+Ye902TETycND4nBGVduP7L1/IKbugoq8K3BKBNyPyzK3Oy9QRHt2eVg1Hfs AMnsXN3uqi7j4Pj+yIu2gNg3X2Cj0vb3RUp0TT29rG8yagVUuJ77C48wqh5suIyFcgo5 Yvm8djixZRdzgmKADAdWguFFFtxTVcaX2ZeCPcaNN2BMtoWUcXYMRVw8X/DEZa32Wff9 NfEP8iDNBBhjRw0CEK3CQtGaHdZ0BR1Bl1WVNKs0/iU/N2eNoqaZ8meQtbHiWNh4gvMS OM8g== X-Gm-Message-State: AOAM531JzUkmh6D/8ErWXY/mV8WW7EMOudJYpjO6iEDveve1C2LGiZcT DfX7rbIL4Vi3CN7l1LDD3t1XEsfgVlKrew== X-Google-Smtp-Source: ABdhPJz+83Ao1uzFXbBxgC6ZeivLk1XSVCXfCtBYgRd5tR/gxul0xzXXgDDz+VvhKGgX2RNcGxwAsQ== X-Received: by 2002:adf:e0c3:: with SMTP id m3mr52685733wri.546.1638897935875; Tue, 07 Dec 2021 09:25:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 1/1] gicv3: fix ICH_MISR's LRENP computation Date: Tue, 7 Dec 2021 17:25:33 +0000 Message-Id: <20211207172533.1410205-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211207172533.1410205-1-peter.maydell@linaro.org> References: <20211207172533.1410205-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::433 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1638898434532100001 Content-Type: text/plain; charset="utf-8" From: Damien Hedde According to the "Arm Generic Interrupt Controller Architecture Specification GIC architecture version 3 and 4" (version G: page 345 for aarch64 or 509 for aarch32): LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE=3D=3D1 and ICH_HCR.EOIcount is non-zero. When only LRENPIE was set (and EOI count was zero), the LRENP bit was wrongly set and MISR value was wrong. As an additional consequence, if an hypervisor set ICH_HCR.LRENPIE, the maintenance interrupt was constantly fired. It happens since patch 9cee1efe92 ("hw/intc: Set GIC maintenance interrupt level to only 0 or 1") which fixed another bug about maintenance interrupt (most significant bits of misr, including this one, were ignored in the interrupt trigger). Fixes: 83f036fe3d ("hw/intc/arm_gicv3: Add accessors for ICH_ system regist= ers") Signed-off-by: Damien Hedde Reviewed-by: Peter Maydell Message-id: 20211207094427.3473-1-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 7fba9314508..85fc369e550 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -351,7 +351,8 @@ static uint32_t maintenance_interrupt_state(GICv3CPUSta= te *cs) /* Scan list registers and fill in the U, NP and EOI bits */ eoi_maintenance_interrupt_state(cs, &value); =20 - if (cs->ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK= )) { + if ((cs->ich_hcr_el2 & ICH_HCR_EL2_LRENPIE) && + (cs->ich_hcr_el2 & ICH_HCR_EL2_EOICOUNT_MASK)) { value |=3D ICH_MISR_EL2_LRENP; } =20 --=20 2.25.1