From nobody Mon Feb 9 18:45:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1638155566727631.4062837147002; Sun, 28 Nov 2021 19:12:46 -0800 (PST) Received: from localhost ([::1]:42964 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mrX5x-0001IS-JQ for importer@patchew.org; Sun, 28 Nov 2021 22:12:45 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44060) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mrWyg-0001lK-5K for qemu-devel@nongnu.org; Sun, 28 Nov 2021 22:05:14 -0500 Received: from [2607:f8b0:4864:20::432] (port=36431 helo=mail-pf1-x432.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mrWye-00007h-4d for qemu-devel@nongnu.org; Sun, 28 Nov 2021 22:05:13 -0500 Received: by mail-pf1-x432.google.com with SMTP id n26so15321063pff.3 for ; Sun, 28 Nov 2021 19:05:11 -0800 (PST) Received: from frankchang-ThinkPad-T490.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id oj11sm17904040pjb.46.2021.11.28.19.05.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Nov 2021 19:05:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h7X73d3mXV4NiBkNQSBQTknzEgHjhBjFiLZpuoeqIgY=; b=Y6J/u1OwFY82E7wkcNLZ+YM9aYBmkjM2kgWE9Ws4YwbB1FRe12Po6yC2y8WPqnjREN nLY0/1TGk89S67V5Cr6u9H3bFzCqYSSkhbJ+fcVc1hMCOmZShqJX9DXqdcoZjSmH+wJR 3db5WuVSu+QSHzAJ7dGIQ1fDgNsdvWsrpK6YGizk6tc+Vm2cYBs0XUyF5YOxMMGSZtY1 c4st/WjC6VInIB955oB+c3elud0A476qxPBP0hcoyS71DEws7foMeUiQQ+dBGK1CxdRK qfxsqi07gC8YSQVnZATJgNNrLaBP4cwmIxb2sOU78azkUytHUkFkNqIlmk37euewRgg0 erKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h7X73d3mXV4NiBkNQSBQTknzEgHjhBjFiLZpuoeqIgY=; b=G8FU55s1h9tWehkU/BM5yhIxTAIgus5knxCY2+km2GkfObr04/U9TE0uik0ZWZQYU5 g6qip4MqSRtLT+tpKFObsQyZA8l4ICceDvyRH+qhswv3O6kpc8N2M3h1eDbaxEg6gQib /yMVWKWlWAmFPkAaziA0PnJhtNmaL0GhThWeecqupDAc01fktgJK25an8rWCHFQ1AU2Y HQo3qTgN9i5fXaQhMfngrn7leGta5XQsL4O10Cgu2Nk2KaeNWphlNWLpmLPTlx8L4PKn vfoVOYMZhSi566Ej5gMOwAWAIcL8UOHss31SEBvGt1z3jFL+IUVQALSmFtgYPsfC5p9d lOcA== X-Gm-Message-State: AOAM532fYPTbpXD6TuYWl8+A8YhqCyxdcNFXc+WW0AI3cYz33ahtlD5j 57B6TxYkxO/xfGTcERry3HOociRo81T3C8Io X-Google-Smtp-Source: ABdhPJz7D1Gv7HvIgjG0IN7KtZW2rIRY/InyOprVOCIfzIs2bQ5eJ/ftoJWr717wrC+OlQbskzHvEg== X-Received: by 2002:a63:f24:: with SMTP id e36mr32952650pgl.4.1638155110813; Sun, 28 Nov 2021 19:05:10 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v10 19/77] target/riscv: rvv-1.0: configure instructions Date: Mon, 29 Nov 2021 11:02:39 +0800 Message-Id: <20211129030340.429689-20-frank.chang@sifive.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211129030340.429689-1-frank.chang@sifive.com> References: <20211129030340.429689-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::432 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Frank Chang , Bin Meng , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1638155568505100001 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 62 +++++++++++-------------- target/riscv/vector_helper.c | 14 +++++- 2 files changed, 40 insertions(+), 36 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index afec1873333..049688d83a8 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -120,59 +120,51 @@ static bool require_noover(const int8_t dst, const in= t8_t dst_lmul, return !is_overlapped(dst, dst_size, src, src_size); } =20 -static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) +static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2) { - TCGv s1, s2, dst; + TCGv s1, dst; =20 - if (!require_rvv(ctx) || !has_ext(ctx, RVV)) { + if (!require_rvv(s) || !has_ext(s, RVV)) { return false; } =20 - s2 =3D get_gpr(ctx, a->rs2, EXT_ZERO); - dst =3D dest_gpr(ctx, a->rd); + dst =3D dest_gpr(s, rd); =20 - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ - if (a->rs1 =3D=3D 0) { + if (rd =3D=3D 0 && rs1 =3D=3D 0) { + s1 =3D tcg_temp_new(); + tcg_gen_mov_tl(s1, cpu_vl); + } else if (rs1 =3D=3D 0) { /* As the mask is at least one bit, RV_VLEN_MAX is >=3D VLMAX */ s1 =3D tcg_constant_tl(RV_VLEN_MAX); } else { - s1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); + s1 =3D get_gpr(s, rs1, EXT_ZERO); } + gen_helper_vsetvl(dst, cpu_env, s1, s2); - gen_set_gpr(ctx, a->rd, dst); - mark_vs_dirty(ctx); + gen_set_gpr(s, rd, dst); + mark_vs_dirty(s); =20 - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); + tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn); tcg_gen_lookup_and_goto_ptr(); - ctx->base.is_jmp =3D DISAS_NORETURN; - return true; -} + s->base.is_jmp =3D DISAS_NORETURN; =20 -static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a) -{ - TCGv s1, s2, dst; - - if (!require_rvv(ctx) || !has_ext(ctx, RVV)) { - return false; + if (rd =3D=3D 0 && rs1 =3D=3D 0) { + tcg_temp_free(s1); } =20 - s2 =3D tcg_constant_tl(a->zimm); - dst =3D dest_gpr(ctx, a->rd); + return true; +} =20 - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ - if (a->rs1 =3D=3D 0) { - /* As the mask is at least one bit, RV_VLEN_MAX is >=3D VLMAX */ - s1 =3D tcg_constant_tl(RV_VLEN_MAX); - } else { - s1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); - } - gen_helper_vsetvl(dst, cpu_env, s1, s2); - gen_set_gpr(ctx, a->rd, dst); - mark_vs_dirty(ctx); +static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a) +{ + TCGv s2 =3D get_gpr(s, a->rs2, EXT_ZERO); + return do_vsetvl(s, a->rd, a->rs1, s2); +} =20 - gen_goto_tb(ctx, 0, ctx->pc_succ_insn); - ctx->base.is_jmp =3D DISAS_NORETURN; - return true; +static bool trans_vsetvli(DisasContext *s, arg_vsetvli *a) +{ + TCGv s2 =3D tcg_constant_tl(a->zimm); + return do_vsetvl(s, a->rd, a->rs1, s2); } =20 /* vector register offset from env */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index bf976d364f1..78fae782840 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -31,12 +31,24 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_= ulong s1, { int vlmax, vl; RISCVCPU *cpu =3D env_archcpu(env); + uint64_t lmul =3D FIELD_EX64(s2, VTYPE, VLMUL); uint16_t sew =3D 8 << FIELD_EX64(s2, VTYPE, VSEW); uint8_t ediv =3D FIELD_EX64(s2, VTYPE, VEDIV); bool vill =3D FIELD_EX64(s2, VTYPE, VILL); target_ulong reserved =3D FIELD_EX64(s2, VTYPE, RESERVED); =20 - if ((sew > cpu->cfg.elen) || vill || (ediv !=3D 0) || (reserved !=3D 0= )) { + if (lmul & 4) { + /* Fractional LMUL. */ + if (lmul =3D=3D 4 || + cpu->cfg.elen >> (8 - lmul) < sew) { + vill =3D true; + } + } + + if ((sew > cpu->cfg.elen) + || vill + || (ediv !=3D 0) + || (reserved !=3D 0)) { /* only set vill bit. */ env->vtype =3D FIELD_DP64(0, VTYPE, VILL, 1); env->vl =3D 0; --=20 2.25.1