From nobody Tue Apr 23 10:48:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637853020712192.74959622284985; Thu, 25 Nov 2021 07:10:20 -0800 (PST) Received: from localhost ([::1]:44476 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mqGOB-0005fg-4N for importer@patchew.org; Thu, 25 Nov 2021 10:10:19 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37264) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mqGMT-0002ZA-MB; Thu, 25 Nov 2021 10:08:33 -0500 Received: from [2607:f8b0:4864:20::a32] (port=40800 helo=mail-vk1-xa32.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mqGMR-00020U-2P; Thu, 25 Nov 2021 10:08:33 -0500 Received: by mail-vk1-xa32.google.com with SMTP id 70so4107769vkx.7; Thu, 25 Nov 2021 07:08:30 -0800 (PST) Received: from rekt.ibmuc.com ([191.19.215.188]) by smtp.gmail.com with ESMTPSA id i27sm2081057uab.8.2021.11.25.07.08.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Nov 2021 07:08:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=90A0I2S7okRovUezGDsi2nBN42VirmN9p2lN7iC2f7Q=; b=S9xapjzKzeGrqxTGUXEXn4vagr0c8Qw1WBhMU5m4s0IafqWu1KKf08V1+OOn4Mkpsc /lZizrTYB2HMhJDiPHkLAOS5puy5o7s+7S98ATvja9Sh4cuwhHKhCeVHkGX2f6oskFSv TN2olPAyeVizJKZ5KwpsmlI9dNof5A6RjgeUIy8XWsZcx6jgMA/tOV4GtNyvUWbfnDo4 LM6PDwYdTqFrftEYWuur3V2PsRmjJJOdYr3UUE9K8S/zxHbXzx8dwp0jsnNFuo1PPZ/y 2GxAzzT+luXjGyt5/pKpbTvyyRVsTl1U9SRRygSUmiOmtN8yG9RnXX3usFxAo3vq/sic NhLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=90A0I2S7okRovUezGDsi2nBN42VirmN9p2lN7iC2f7Q=; b=xsM74tHuT4/XHQaa7dKJMZxurzCLbdrm1fiiQqVzK6Pjfpt25cr4hYFwZS9eXxUK+s yftLuD29pMymw7NfygSBlHxpbxBDvtW4qtcOW5vRIEaYfbiGzE7DETVt+Xbz7uATHHPb QCA9A3mqJ9ssPM97OuJFYnOfvIXGsjY/4znAYWSjf0D/OUuQnkQRF1NpbI5QTJxTwPHK 5S3Vaox947uDfLAhDcQdqSyhq9jV5r8VqMfw/MMu0m8Enixoa2qTn5w22YARLvj/4A0r zrar8q91UaKEAFSTU/BE2um05vsuQFrbisKjpz3X3IDF2JyuX6H6Oh6k2VuVNemZ/X5j xr5g== X-Gm-Message-State: AOAM533YfR1u3ht27Rw51T7PahuBfVMGo0Vwc402nEgpMmSUlYzhPssj kdugN9A2J0P3RcESq9HdthX3cmKa/hs= X-Google-Smtp-Source: ABdhPJxlKf8yX0r78dBX804Rr0aFUmAPSp8/brw4opkqjX6h9UZd/x+f0hozwJm3vc2dnGpLyYnnkw== X-Received: by 2002:a05:6122:997:: with SMTP id g23mr12328534vkd.15.1637852909559; Thu, 25 Nov 2021 07:08:29 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v8 01/10] target/ppc: introduce PMUEventType and PMU overflow timers Date: Thu, 25 Nov 2021 12:08:08 -0300 Message-Id: <20211125150817.573204-2-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211125150817.573204-1-danielhb413@gmail.com> References: <20211125150817.573204-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::a32 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::a32; envelope-from=danielhb413@gmail.com; helo=mail-vk1-xa32.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1637853022044100001 Content-Type: text/plain; charset="utf-8" This patch starts an IBM Power8+ compatible PMU implementation by adding the representation of PMU events that we are going to sample, PMUEventType. This enum represents a Perf event that is being sampled by a specific counter 'sprn'. Events that aren't available (i.e. no event was set in MMCR1) will be of type 'PMU_EVENT_INVALID'. Events that are inactive due to frozen counter bits state are of type 'PMU_EVENT_INACTIVE'. Other types added in this patch are PMU_EVENT_CYCLES and PMU_EVENT_INSTRUCTIONS. More types will be added later on. Let's also add the required PMU cycle overflow timers. They will be used to trigger cycle overflows when cycle events are being sampled. This timer will call cpu_ppc_pmu_timer_cb(), which in turn calls fire_PMC_interrupt(). Both functions are stubs that will be implemented later on when EBB support is added. Two new helper files are created to host this new logic. cpu_ppc_pmu_init() will init all overflow timers during CPU init time. Reviewed-by: David Gibson Signed-off-by: Daniel Henrique Barboza --- hw/ppc/spapr_cpu_core.c | 1 + target/ppc/cpu.h | 16 ++++++++++++ target/ppc/cpu_init.c | 24 ++++++++++++++++++ target/ppc/meson.build | 1 + target/ppc/power8-pmu.c | 56 +++++++++++++++++++++++++++++++++++++++++ target/ppc/power8-pmu.h | 25 ++++++++++++++++++ 6 files changed, 123 insertions(+) create mode 100644 target/ppc/power8-pmu.c create mode 100644 target/ppc/power8-pmu.h diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 58e7341cb7..a57ba70a87 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -20,6 +20,7 @@ #include "target/ppc/kvm_ppc.h" #include "hw/ppc/ppc.h" #include "target/ppc/mmu-hash64.h" +#include "target/ppc/power8-pmu.h" #include "sysemu/numa.h" #include "sysemu/reset.h" #include "sysemu/hw_accel.h" diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e946da5f3a..2ad47b06d0 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -296,6 +296,16 @@ typedef struct ppc_v3_pate_t { uint64_t dw1; } ppc_v3_pate_t; =20 +/* PMU related structs and defines */ +#define PMU_COUNTERS_NUM 6 +#define PMU_TIMERS_NUM (PMU_COUNTERS_NUM - 1) /* PMC5 doesn't count cycl= es */ +typedef enum { + PMU_EVENT_INVALID =3D 0, + PMU_EVENT_INACTIVE, + PMU_EVENT_CYCLES, + PMU_EVENT_INSTRUCTIONS, +} PMUEventType; + /*************************************************************************= ****/ /* Machine state register bits definition = */ #define MSR_SF 63 /* Sixty-four-bit mode hfla= gs */ @@ -1191,6 +1201,12 @@ struct CPUPPCState { uint32_t tm_vscr; uint64_t tm_dscr; uint64_t tm_tar; + + /* + * Timers used to fire performance monitor alerts + * when counting cycles. + */ + QEMUTimer *pmu_cyc_overflow_timers[PMU_TIMERS_NUM]; }; =20 #define SET_FIT_PERIOD(a_, b_, c_, d_) \ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 6695985e9b..9610e65c76 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -45,6 +45,7 @@ #include "helper_regs.h" #include "internal.h" #include "spr_tcg.h" +#include "power8-pmu.h" =20 /* #define PPC_DEBUG_SPR */ /* #define USE_APPLE_GDB */ @@ -7377,6 +7378,20 @@ static void register_power9_mmu_sprs(CPUPPCState *en= v) #endif } =20 +/* + * Initialize PMU counter overflow timers for Power8 and + * newer Power chips when using TCG. + */ +static void init_tcg_pmu_power8(CPUPPCState *env) +{ +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + /* Init PMU overflow timers */ + if (!kvm_enabled()) { + cpu_ppc_pmu_init(env); + } +#endif +} + static void init_proc_book3s_common(CPUPPCState *env) { register_ne_601_sprs(env); @@ -7694,6 +7709,9 @@ static void init_proc_POWER8(CPUPPCState *env) register_sdr1_sprs(env); register_book3s_207_dbg_sprs(env); =20 + /* Common TCG PMU */ + init_tcg_pmu_power8(env); + /* POWER8 Specific Registers */ register_book3s_ids_sprs(env); register_rmor_sprs(env); @@ -7888,6 +7906,9 @@ static void init_proc_POWER9(CPUPPCState *env) init_proc_book3s_common(env); register_book3s_207_dbg_sprs(env); =20 + /* Common TCG PMU */ + init_tcg_pmu_power8(env); + /* POWER8 Specific Registers */ register_book3s_ids_sprs(env); register_amr_sprs(env); @@ -8104,6 +8125,9 @@ static void init_proc_POWER10(CPUPPCState *env) init_proc_book3s_common(env); register_book3s_207_dbg_sprs(env); =20 + /* Common TCG PMU */ + init_tcg_pmu_power8(env); + /* POWER8 Specific Registers */ register_book3s_ids_sprs(env); register_amr_sprs(env); diff --git a/target/ppc/meson.build b/target/ppc/meson.build index b85f295703..a49a8911e0 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -51,6 +51,7 @@ ppc_softmmu_ss.add(when: 'TARGET_PPC64', if_true: files( 'mmu-book3s-v3.c', 'mmu-hash64.c', 'mmu-radix64.c', + 'power8-pmu.c', )) =20 target_arch +=3D {'ppc': ppc_ss} diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c new file mode 100644 index 0000000000..e66c152eb5 --- /dev/null +++ b/target/ppc/power8-pmu.c @@ -0,0 +1,56 @@ +/* + * PMU emulation helpers for TCG IBM POWER chips + * + * Copyright IBM Corp. 2021 + * + * Authors: + * Daniel Henrique Barboza + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" + +#include "power8-pmu.h" +#include "cpu.h" +#include "helper_regs.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "qemu/error-report.h" +#include "qemu/main-loop.h" +#include "hw/ppc/ppc.h" + +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + +static void fire_PMC_interrupt(PowerPCCPU *cpu) +{ + CPUPPCState *env =3D &cpu->env; + + if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_EBE)) { + return; + } + + /* PMC interrupt not implemented yet */ + return; +} + +static void cpu_ppc_pmu_timer_cb(void *opaque) +{ + PowerPCCPU *cpu =3D opaque; + + fire_PMC_interrupt(cpu); +} + +void cpu_ppc_pmu_init(CPUPPCState *env) +{ + PowerPCCPU *cpu =3D env_archcpu(env); + int i; + + for (i =3D 0; i < PMU_TIMERS_NUM; i++) { + env->pmu_cyc_overflow_timers[i] =3D timer_new_ns(QEMU_CLOCK_VIRTUA= L, + &cpu_ppc_pmu_timer_= cb, + cpu); + } +} +#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ diff --git a/target/ppc/power8-pmu.h b/target/ppc/power8-pmu.h new file mode 100644 index 0000000000..49a813a443 --- /dev/null +++ b/target/ppc/power8-pmu.h @@ -0,0 +1,25 @@ +/* + * PMU emulation helpers for TCG IBM POWER chips + * + * Copyright IBM Corp. 2021 + * + * Authors: + * Daniel Henrique Barboza + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef POWER8_PMU +#define POWER8_PMU + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "qemu/error-report.h" +#include "qemu/main-loop.h" + +void cpu_ppc_pmu_init(CPUPPCState *env); + +#endif --=20 2.31.1 From nobody Tue Apr 23 10:48:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637853030344267.1947536359006; Thu, 25 Nov 2021 07:10:30 -0800 (PST) Received: from localhost ([::1]:45020 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mqGOL-00060u-4g for importer@patchew.org; Thu, 25 Nov 2021 10:10:29 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37278) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mqGMV-0002di-8y; Thu, 25 Nov 2021 10:08:35 -0500 Received: from [2607:f8b0:4864:20::929] (port=38436 helo=mail-ua1-x929.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mqGMT-00020v-92; Thu, 25 Nov 2021 10:08:35 -0500 Received: by mail-ua1-x929.google.com with SMTP id w23so12927156uao.5; Thu, 25 Nov 2021 07:08:32 -0800 (PST) Received: from rekt.ibmuc.com ([191.19.215.188]) by smtp.gmail.com with ESMTPSA id i27sm2081057uab.8.2021.11.25.07.08.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Nov 2021 07:08:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1jT+EAhjZBgR8sNMY7uDNM+3Z55BOM4YqtCLLIcWG9o=; b=cBoikFpWZOtIZlq1ofnJCEwfYq4LfS3irMzVQa4WG+Bg27wp/Vx69dDtEMgz9gDMCU h+LU+ON0GxUVAhT5jGpzGFzmEwZaHHBH6ISsAWElPAwT5O/PaVXUyHUZmC3DNfxxXflA aUD2PVX7GYsqpGUD2qAwVKaXvKhieIf6hTLsynYoO2KSP3Ws7yyxobEkhndwi+znJ7p/ 20+QxDtb76kmSQ3GRN++2h8IHs9UH7nDbMAwRx6I5e41Gstb2EDPnpCBOsbaZGbyg6n0 7dXkp/Bo1bxXS4qAgKG6qLBt/66zIpTt0Qd0hIYg8qB/OJH4/zlPDPZ8bun8YH7chJ/m nU8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1jT+EAhjZBgR8sNMY7uDNM+3Z55BOM4YqtCLLIcWG9o=; b=OuPLyuZjTeErPdlB+fBmSpRCW4NzcsZGboIhI2rtxrQvKKqlQFMjvQvOz+OeyOuXrf SWlhho3WSDCZjvKa21oS2ZFmYnTSZajMLPSnmGHQmdtWbDrkrfrNNsW+ewkS4C+7KQ4A xglViCIsh79Nx9ZUH1I9pCMsfH0dK1hEOlAxunE851yAXef+Mwvp08gtkKRaA3sIS2uA B4jTU2umxeHK9D/KgPkRLtxsSIgsA536TSdF9FoD8OIq81H1e5dI/VbYne2wYYxajp3g 333y7JIUMaMQh5g5htgsCZdbRo/Bb/pcQOnCijQhyehRGATw9ZyZctRfIQ6d1jhYmGWI KCFQ== X-Gm-Message-State: AOAM530odRV1718PX3FU58mOZakUmsXDqi+srGNY1ysx3F6U6VyohvDQ cgw8JZrVdMgqKuMt5LNfVYgvVP4aD04= X-Google-Smtp-Source: ABdhPJwN3caJh4koejbQdtfIV7cI/Au7WWeR5v+oNgFdEN2lkubPKTSgymv0itOPdZlzm7RHifhHZQ== X-Received: by 2002:a05:6102:358b:: with SMTP id h11mr10073559vsu.24.1637852911809; Thu, 25 Nov 2021 07:08:31 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v8 02/10] target/ppc: PMU basic cycle count for pseries TCG Date: Thu, 25 Nov 2021 12:08:09 -0300 Message-Id: <20211125150817.573204-3-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211125150817.573204-1-danielhb413@gmail.com> References: <20211125150817.573204-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::929 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::929; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x929.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1637853032419100001 Content-Type: text/plain; charset="utf-8" This patch adds the barebones of the PMU logic by enabling cycle counting. The overall logic goes as follows: - MMCR0 reg initial value is set to 0x80000000 (MMCR0_FC set) to avoid having to spin the PMU right at system init; - to retrieve the events that are being profiled, pmc_get_event() will check the current MMCR0 and MMCR1 value and return the appropriate PMUEventType. For PMCs 1-4, event 0x2 is the implementation dependent value of PMU_EVENT_INSTRUCTIONS and event 0x1E is the implementation dependent value of PMU_EVENT_CYCLES. These events are supported by IBM Power chips since Power8, at least, and the Linux Perf driver makes use of these events until kernel v5.15. For PMC1, event 0xF0 is the architected PowerISA event for cycles. Event 0xFE is the architected PowerISA event for instructions; - if the counter is frozen, either via the global MMCR0_FC bit or its individual frozen counter bit, PMU_EVENT_INACTIVE is returned; - pmu_update_cycles() will go through each counter and update the values of all PMCs that are counting cycles. This function will be called every time a MMCR0 update is done to keep counters values up to date. Upcoming patches will use this function to allow the counters to be properly updated during read/write of the PMCs and MMCR1 writes. Given that the base CPU frequency is fixed at 1Ghz for both powernv and pseries clock, cycle calculation assumes that 1 nanosecond equals 1 CPU cycle. Cycle value is then calculated by adding the elapsed time, in nanoseconds, of the last cycle update done via pmu_update_cycles(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: David Gibson --- target/ppc/cpu.h | 20 +++++ target/ppc/cpu_init.c | 6 +- target/ppc/helper.h | 1 + target/ppc/power8-pmu-regs.c.inc | 23 +++++- target/ppc/power8-pmu.c | 122 +++++++++++++++++++++++++++++++ target/ppc/spr_tcg.h | 1 + 6 files changed, 169 insertions(+), 4 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 2ad47b06d0..9c732953f0 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -361,6 +361,9 @@ typedef enum { #define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */ #define MMCR0_PMCC0 PPC_BIT(44) /* PMC Control bit 0 */ #define MMCR0_PMCC1 PPC_BIT(45) /* PMC Control bit 1 */ +#define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */ +#define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */ +#define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */ /* MMCR0 userspace r/w mask */ #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE) /* MMCR2 userspace r/w mask */ @@ -373,6 +376,17 @@ typedef enum { #define MMCR2_UREG_MASK (MMCR2_FC1P0 | MMCR2_FC2P0 | MMCR2_FC3P0 | \ MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0) =20 +#define MMCR1_EVT_SIZE 8 +/* extract64() does a right shift before extracting */ +#define MMCR1_PMC1SEL_START 32 +#define MMCR1_PMC1EVT_EXTR (64 - MMCR1_PMC1SEL_START - MMCR1_EVT_SIZE) +#define MMCR1_PMC2SEL_START 40 +#define MMCR1_PMC2EVT_EXTR (64 - MMCR1_PMC2SEL_START - MMCR1_EVT_SIZE) +#define MMCR1_PMC3SEL_START 48 +#define MMCR1_PMC3EVT_EXTR (64 - MMCR1_PMC3SEL_START - MMCR1_EVT_SIZE) +#define MMCR1_PMC4SEL_START 56 +#define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) @@ -1207,6 +1221,12 @@ struct CPUPPCState { * when counting cycles. */ QEMUTimer *pmu_cyc_overflow_timers[PMU_TIMERS_NUM]; + + /* + * PMU base time value used by the PMU to calculate + * running cycles. + */ + uint64_t pmu_base_time; }; =20 #define SET_FIT_PERIOD(a_, b_, c_, d_) \ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 9610e65c76..e0b6fe4057 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6821,8 +6821,8 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState = *env) { spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_MMCR0, 0x00000000); + &spr_read_generic, &spr_write_MMCR0, + KVM_REG_PPC_MMCR0, 0x80000000); spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -6870,7 +6870,7 @@ static void register_book3s_pmu_user_sprs(CPUPPCState= *env) spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, &spr_read_ureg, &spr_write_ureg, - 0x00000000); + 0x80000000); spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", &spr_read_ureg, SPR_NOACCESS, &spr_read_ureg, &spr_write_ureg, diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 627811cefc..ea60a7493c 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -20,6 +20,7 @@ DEF_HELPER_1(rfscv, void, env) DEF_HELPER_1(hrfid, void, env) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) +DEF_HELPER_2(store_mmcr0, void, env, tl) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.= c.inc index 7391851238..fbb8977641 100644 --- a/target/ppc/power8-pmu-regs.c.inc +++ b/target/ppc/power8-pmu-regs.c.inc @@ -104,6 +104,17 @@ void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, = int sprn) tcg_temp_free(t0); } =20 +static void write_MMCR0_common(DisasContext *ctx, TCGv val) +{ + /* + * helper_store_mmcr0 will make clock based operations that + * will cause 'bad icount read' errors if we do not execute + * gen_icount_io_start() beforehand. + */ + gen_icount_io_start(ctx); + gen_helper_store_mmcr0(cpu_env, val); +} + void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn) { TCGv masked_gprn; @@ -119,7 +130,7 @@ void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, = int gprn) */ masked_gprn =3D masked_gprn_for_spr_write(gprn, SPR_POWER_MMCR0, MMCR0_UREG_MASK); - gen_store_spr(SPR_POWER_MMCR0, masked_gprn); + write_MMCR0_common(ctx, masked_gprn); =20 tcg_temp_free(masked_gprn); } @@ -219,6 +230,11 @@ void spr_write_PMC56_ureg(DisasContext *ctx, int sprn,= int gprn) /* The remaining steps are similar to PMCs 1-4 userspace write */ spr_write_PMC14_ureg(ctx, sprn, gprn); } + +void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn) +{ + write_MMCR0_common(ctx, cpu_gpr[gprn]); +} #else void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn) { @@ -259,4 +275,9 @@ void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, = int gprn) { spr_noaccess(ctx, gprn, sprn); } + +void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn) +{ + spr_write_generic(ctx, sprn, gprn); +} #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index e66c152eb5..47932ded4f 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -23,6 +23,128 @@ =20 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) =20 +static bool pmc_is_inactive(CPUPPCState *env, int sprn) +{ + if (env->spr[SPR_POWER_MMCR0] & MMCR0_FC) { + return true; + } + + if (sprn < SPR_POWER_PMC5) { + return env->spr[SPR_POWER_MMCR0] & MMCR0_FC14; + } + + return env->spr[SPR_POWER_MMCR0] & MMCR0_FC56; +} + +/* + * For PMCs 1-4, IBM POWER chips has support for an implementation + * dependent event, 0x1E, that enables cycle counting. The Linux kernel + * makes extensive use of 0x1E, so let's also support it. + * + * Likewise, event 0x2 is an implementation-dependent event that IBM + * POWER chips implement (at least since POWER8) that is equivalent to + * PM_INST_CMPL. Let's support this event on PMCs 1-4 as well. + */ +static PMUEventType pmc_get_event(CPUPPCState *env, int sprn) +{ + uint8_t mmcr1_evt_extr[] =3D { MMCR1_PMC1EVT_EXTR, MMCR1_PMC2EVT_EXTR, + MMCR1_PMC3EVT_EXTR, MMCR1_PMC4EVT_EXTR }; + PMUEventType evt_type =3D PMU_EVENT_INVALID; + uint8_t pmcsel; + int i; + + if (pmc_is_inactive(env, sprn)) { + return PMU_EVENT_INACTIVE; + } + + if (sprn =3D=3D SPR_POWER_PMC5) { + return PMU_EVENT_INSTRUCTIONS; + } + + if (sprn =3D=3D SPR_POWER_PMC6) { + return PMU_EVENT_CYCLES; + } + + i =3D sprn - SPR_POWER_PMC1; + pmcsel =3D extract64(env->spr[SPR_POWER_MMCR1], mmcr1_evt_extr[i], + MMCR1_EVT_SIZE); + + switch (pmcsel) { + case 0x2: + evt_type =3D PMU_EVENT_INSTRUCTIONS; + break; + case 0x1E: + evt_type =3D PMU_EVENT_CYCLES; + break; + case 0xF0: + /* + * PMC1SEL =3D 0xF0 is the architected PowerISA v3.1 + * event that counts cycles using PMC1. + */ + if (sprn =3D=3D SPR_POWER_PMC1) { + evt_type =3D PMU_EVENT_CYCLES; + } + break; + case 0xFE: + /* + * PMC1SEL =3D 0xFE is the architected PowerISA v3.1 + * event to sample instructions using PMC1. + */ + if (sprn =3D=3D SPR_POWER_PMC1) { + evt_type =3D PMU_EVENT_INSTRUCTIONS; + } + break; + default: + break; + } + + return evt_type; +} + +static void pmu_update_cycles(CPUPPCState *env) +{ + uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint64_t time_delta =3D now - env->pmu_base_time; + int sprn; + + for (sprn =3D SPR_POWER_PMC1; sprn <=3D SPR_POWER_PMC6; sprn++) { + if (pmc_get_event(env, sprn) !=3D PMU_EVENT_CYCLES) { + continue; + } + + /* + * The pseries and powernv clock runs at 1Ghz, meaning + * that 1 nanosec equals 1 cycle. + */ + env->spr[sprn] +=3D time_delta; + } + + /* Update base_time for future calculations */ + env->pmu_base_time =3D now; +} + +void helper_store_mmcr0(CPUPPCState *env, target_ulong value) +{ + target_ulong curr_value =3D env->spr[SPR_POWER_MMCR0]; + bool curr_FC =3D curr_value & MMCR0_FC; + bool new_FC =3D value & MMCR0_FC; + + pmu_update_cycles(env); + + env->spr[SPR_POWER_MMCR0] =3D value; + + /* + * MMCR0 writes can change HFLAGS_PMCCCLEAR and HFLAGS_MMCR0FC. + * hreg_compute_hflags() does too much stuff to be called + * needlessly, so check beforehand if we really need a hflags + * update. + */ + if (((curr_value & MMCR0_PMCC) !=3D (value & MMCR0_PMCC)) || + (curr_FC !=3D new_FC)) { + hreg_compute_hflags(env); + } +} + static void fire_PMC_interrupt(PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index 520f1ef233..eb1d0c2bf0 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -25,6 +25,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn); void spr_read_generic(DisasContext *ctx, int gprn, int sprn); void spr_write_generic(DisasContext *ctx, int sprn, int gprn); +void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn); void spr_read_xer(DisasContext *ctx, int gprn, int sprn); void spr_write_xer(DisasContext *ctx, int sprn, int gprn); void spr_read_lr(DisasContext *ctx, int gprn, int sprn); --=20 2.31.1 From nobody Tue Apr 23 10:48:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637853258271884.4281269145051; Thu, 25 Nov 2021 07:14:18 -0800 (PST) Received: from localhost ([::1]:53686 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mqGS1-0003TA-6J for importer@patchew.org; Thu, 25 Nov 2021 10:14:17 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37298) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mqGMX-0002kc-V2; Thu, 25 Nov 2021 10:08:37 -0500 Received: from [2607:f8b0:4864:20::92d] (port=41578 helo=mail-ua1-x92d.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mqGMV-00021E-36; Thu, 25 Nov 2021 10:08:37 -0500 Received: by mail-ua1-x92d.google.com with SMTP id p37so12907286uae.8; Thu, 25 Nov 2021 07:08:34 -0800 (PST) Received: from rekt.ibmuc.com ([191.19.215.188]) by smtp.gmail.com with ESMTPSA id i27sm2081057uab.8.2021.11.25.07.08.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Nov 2021 07:08:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JJp0Tq3btpoN+1I5qz1E8NsCamjwSSIbZkAE2qBHSuM=; b=L+WvbzUw5UkvlZMryBTmC5LLZq+R9gWmkeoul/vzF5ZpWhgKLEisPYnsrnCeG23hYU 3t0p5liRAjjcpFfJ8l5F+aptHHsPoFbVf8SDm0w4bgX1CK3p2sSugFFt6mLN7WM13L2r lDY5Iq5qPGetC9WIuxB2O1sfqofVORp/sgmMJyQTaNRdY/Un6J5Jja+ylvtDXcieULhf 4um28OUovLlf6vTK7gyXkgAM+K7SRGto2XwjGDI9hRG+p7beRbSjOHrjLc7ICVGEjoSJ nlwuvH7vhsJFAGbmAykpm5uPszEWMjDrujs58/sbmtTjybxdMj3qw/nyLGSOfjmRJOv9 YmLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JJp0Tq3btpoN+1I5qz1E8NsCamjwSSIbZkAE2qBHSuM=; b=g2HJMDFKTw7PyQciJafnZbcLaOSrv8HG/XpeMP3hhuJxpyB3RUVctrdRwYALh+uY6m ZP7Ok3f1zVpZMLu6Uv/27IPeVIRIX9lu7tHKMhuCHynLkL+YXwyF8bZXaLTVBTx9tHGt qqxzUW5CadTQsTeZWc8O1O7/C0Q3GzAdmAOasNWpLTVDo60Tlrt7eKBG7Z0D5nZB5lyK 9TUx/ZF4vg0v/gMApfPeY0/jJ60YyQmwwqfrDr4901s/5mQSS/5FUJtIly8UL+MFNHGj cfABKyKy8Kdn3qXbEybAwihJf11x3lA3vQNYWrIAsKopIrQZTooRxdDVt9AxXvwh1tI8 Fkyg== X-Gm-Message-State: AOAM5337mqATFploa116OaaweXsdGaFe21sVzA3K9UgKb6kR+nEzJs0Q OjaeQsnQIPKpE/j/56If/9TE8ugR6J4= X-Google-Smtp-Source: ABdhPJyoPQb9TC3iWOER3ls3TbgDwzgJFYDdlGP2ZkMVY11Ywojenbrgv+tEtX8kX+AItB1DsazNwQ== X-Received: by 2002:a67:e44e:: with SMTP id n14mr10250479vsm.55.1637852913834; Thu, 25 Nov 2021 07:08:33 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v8 03/10] target/ppc: PMU: update counters on PMCs r/w Date: Thu, 25 Nov 2021 12:08:10 -0300 Message-Id: <20211125150817.573204-4-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211125150817.573204-1-danielhb413@gmail.com> References: <20211125150817.573204-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::92d (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::92d; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x92d.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1637853259131100001 Content-Type: text/plain; charset="utf-8" Calling pmu_update_cycles() on every PMC read/write operation ensures that the values being fetched are up to date with the current PMU state. In theory we can get away by just trapping PMCs reads, but we're going to trap PMC writes to deal with counter overflow logic later on. Let's put the required wiring for that and make our lives a bit easier in the next patches. Signed-off-by: Daniel Henrique Barboza Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 12 ++++++------ target/ppc/helper.h | 2 ++ target/ppc/power8-pmu-regs.c.inc | 29 +++++++++++++++++++++++++++-- target/ppc/power8-pmu.c | 14 ++++++++++++++ target/ppc/spr_tcg.h | 2 ++ 5 files changed, 51 insertions(+), 8 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index e0b6fe4057..a7f47ec322 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6833,27 +6833,27 @@ static void register_book3s_pmu_sup_sprs(CPUPPCStat= e *env) KVM_REG_PPC_MMCRA, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC1, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC2, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC3, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC4, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC5, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC6, 0x00000000); spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", SPR_NOACCESS, SPR_NOACCESS, diff --git a/target/ppc/helper.h b/target/ppc/helper.h index ea60a7493c..d7567f75b4 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -21,6 +21,8 @@ DEF_HELPER_1(hrfid, void, env) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) +DEF_HELPER_3(store_pmc, void, env, i32, i64) +DEF_HELPER_2(read_pmc, tl, env, i32) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.= c.inc index fbb8977641..f0c9cc343b 100644 --- a/target/ppc/power8-pmu-regs.c.inc +++ b/target/ppc/power8-pmu-regs.c.inc @@ -181,13 +181,23 @@ void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn= , int gprn) tcg_temp_free(masked_gprn); } =20 +void spr_read_PMC(DisasContext *ctx, int gprn, int sprn) +{ + TCGv_i32 t_sprn =3D tcg_const_i32(sprn); + + gen_icount_io_start(ctx); + gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn); + + tcg_temp_free_i32(t_sprn); +} + void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn) { if (!spr_groupA_read_allowed(ctx)) { return; } =20 - spr_read_ureg(ctx, gprn, sprn); + spr_read_PMC(ctx, gprn, sprn + 0x10); } =20 void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn) @@ -206,13 +216,23 @@ void spr_read_PMC56_ureg(DisasContext *ctx, int gprn,= int sprn) spr_read_PMC14_ureg(ctx, gprn, sprn); } =20 +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t_sprn =3D tcg_const_i32(sprn); + + gen_icount_io_start(ctx); + gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]); + + tcg_temp_free_i32(t_sprn); +} + void spr_write_PMC14_ureg(DisasContext *ctx, int sprn, int gprn) { if (!spr_groupA_write_allowed(ctx)) { return; } =20 - spr_write_ureg(ctx, sprn, gprn); + spr_write_PMC(ctx, sprn + 0x10, gprn); } =20 void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn) @@ -280,4 +300,9 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int g= prn) { spr_write_generic(ctx, sprn, gprn); } + +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn) +{ + spr_write_generic(ctx, sprn, gprn); +} #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 47932ded4f..5f2623aa25 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -145,6 +145,20 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong= value) } } =20 +target_ulong helper_read_pmc(CPUPPCState *env, uint32_t sprn) +{ + pmu_update_cycles(env); + + return env->spr[sprn]; +} + +void helper_store_pmc(CPUPPCState *env, uint32_t sprn, uint64_t value) +{ + pmu_update_cycles(env); + + env->spr[sprn] =3D value; +} + static void fire_PMC_interrupt(PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index eb1d0c2bf0..1e79a0522a 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -26,6 +26,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn); void spr_read_generic(DisasContext *ctx, int gprn, int sprn); void spr_write_generic(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn); +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn); void spr_read_xer(DisasContext *ctx, int gprn, int sprn); void spr_write_xer(DisasContext *ctx, int sprn, int gprn); void spr_read_lr(DisasContext *ctx, int gprn, int sprn); @@ -35,6 +36,7 @@ void spr_write_ctr(DisasContext *ctx, int sprn, int gprn); void spr_read_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_MMCR2_ureg(DisasContext *ctx, int gprn, int sprn); +void spr_read_PMC(DisasContext *ctx, int gprn, int sprn); void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_tbl(DisasContext *ctx, int gprn, int sprn); --=20 2.31.1 From nobody Tue Apr 23 10:48:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637853047305119.37551044074883; Thu, 25 Nov 2021 07:10:47 -0800 (PST) Received: from localhost ([::1]:45296 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mqGOb-0006CR-3e for importer@patchew.org; Thu, 25 Nov 2021 10:10:45 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37306) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mqGMZ-0002oQ-3X; Thu, 25 Nov 2021 10:08:39 -0500 Received: from [2607:f8b0:4864:20::92d] (port=36448 helo=mail-ua1-x92d.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mqGMX-00021R-6Z; Thu, 25 Nov 2021 10:08:38 -0500 Received: by mail-ua1-x92d.google.com with SMTP id r15so12966756uao.3; Thu, 25 Nov 2021 07:08:36 -0800 (PST) Received: from rekt.ibmuc.com ([191.19.215.188]) by smtp.gmail.com with ESMTPSA id i27sm2081057uab.8.2021.11.25.07.08.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Nov 2021 07:08:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pUIFlcKij/L6qpLI3KtedQbz+F43S5wU9u9virOCZ2w=; b=k9ciLPjcMWNm9ZyLHJo/P4Yxh5P/Qnsr10hCHWTCjLaBGDgp6JDVObzhsiSePlYCD7 ha9EG5N551Rkn5zN+elLNohCUrO6Ess2iBX3k6hdmgh4E55AkjxozX/kABu9Eq0hLzTh EnvvsqYmN1Mu697eFhHihbteiOq8mVuqL8a458uya4MXI2fca7rrqJSgxgc3enfrZlnE Oi4OVqGD2IoeMenwjl7xzUqf4stN7Bio7v1S8GWXC7QNzQWaGywhE4siaXV90ZbVLkT+ pwK1eflWxrSNu0XxXe87SSBPDagK+UTZ59s8nOj9ehpa1mAWpT3NgB4uqtjwd0ODZVYW YLsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pUIFlcKij/L6qpLI3KtedQbz+F43S5wU9u9virOCZ2w=; b=fu2nCe/guHqXkT9u2NIkaaEzikUQ8ZGesQRbnF0jV5eXJ323eFGjHEQyNZZg3ejhzA LJnfUgcjeR2CW9QRgIkHgypM3pCIUAeTltxBW5Xlb9ZeI+loyrw+SLMpP4pyb+536tqT ZNs1bhnnhxWqqWBTGKy/oJSVQnHQC9rWxjK8P7+TQIi1jpGnhNRG4A9maoDk1fpn4IWj LVNpaeY/eKEjtno7qFy0lRVg7UB8NTm5bih+JUBPGnObStFdbLMdOYKf9EdiJv6Jmw0F v/MQw/OhmZGdQfrXNx0rfGFilKMgIIwm3ATc9ZBB2KmlyuBle/Ieu99Qzmje7Sj3Hs3g h1Og== X-Gm-Message-State: AOAM531GRs4emQ6flP7TWEqGRJ5fQUaKyXhfpifC+HQ5QuBPazziT4a1 DIB+7Xm/AZV89nArCkwo2r0gZ0sV4cw= X-Google-Smtp-Source: ABdhPJxwMsS1kOSkvnM/1IRXNoDXf3T+gHRIq6H1LD7wm74Nd5N/GTW3nKi1OtoKEmoczU7Grl9USg== X-Received: by 2002:a05:6102:953:: with SMTP id a19mr10177328vsi.28.1637852916023; Thu, 25 Nov 2021 07:08:36 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v8 04/10] target/ppc: PMU: update counters on MMCR1 write Date: Thu, 25 Nov 2021 12:08:11 -0300 Message-Id: <20211125150817.573204-5-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211125150817.573204-1-danielhb413@gmail.com> References: <20211125150817.573204-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::92d (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::92d; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x92d.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1637853048181100001 Content-Type: text/plain; charset="utf-8" MMCR1 determines the events to be sampled by the PMU. Updating the counters at every MMCR1 write ensures that we're not sampling more or less events by looking only at MMCR0 and the PMCs. It is worth noticing that both the Book3S PowerPC PMU, and this IBM Power8+ PMU that we're modeling, also uses MMCRA, MMCR2 and MMCR3 to control the PMU. These three registers aren't being handled in this initial implementation, so for now we're controlling all the PMU aspects using MMCR0, MMCR1 and the PMCs. Signed-off-by: Daniel Henrique Barboza Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 2 +- target/ppc/helper.h | 1 + target/ppc/power8-pmu-regs.c.inc | 11 +++++++++++ target/ppc/power8-pmu.c | 7 +++++++ target/ppc/spr_tcg.h | 1 + 5 files changed, 21 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index a7f47ec322..2d72dde26d 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6825,7 +6825,7 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState = *env) KVM_REG_PPC_MMCR0, 0x80000000); spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_MMCR1, KVM_REG_PPC_MMCR1, 0x00000000); spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", SPR_NOACCESS, SPR_NOACCESS, diff --git a/target/ppc/helper.h b/target/ppc/helper.h index d7567f75b4..94b4690375 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -21,6 +21,7 @@ DEF_HELPER_1(hrfid, void, env) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) +DEF_HELPER_2(store_mmcr1, void, env, tl) DEF_HELPER_3(store_pmc, void, env, i32, i64) DEF_HELPER_2(read_pmc, tl, env, i32) #endif diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.= c.inc index f0c9cc343b..25b13ad564 100644 --- a/target/ppc/power8-pmu-regs.c.inc +++ b/target/ppc/power8-pmu-regs.c.inc @@ -255,6 +255,12 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int = gprn) { write_MMCR0_common(ctx, cpu_gpr[gprn]); } + +void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn) +{ + gen_icount_io_start(ctx); + gen_helper_store_mmcr1(cpu_env, cpu_gpr[gprn]); +} #else void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn) { @@ -301,6 +307,11 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int = gprn) spr_write_generic(ctx, sprn, gprn); } =20 +void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn) +{ + spr_write_generic(ctx, sprn, gprn); +} + void spr_write_PMC(DisasContext *ctx, int sprn, int gprn) { spr_write_generic(ctx, sprn, gprn); diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 5f2623aa25..acdaee7459 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -145,6 +145,13 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong= value) } } =20 +void helper_store_mmcr1(CPUPPCState *env, uint64_t value) +{ + pmu_update_cycles(env); + + env->spr[SPR_POWER_MMCR1] =3D value; +} + target_ulong helper_read_pmc(CPUPPCState *env, uint32_t sprn) { pmu_update_cycles(env); diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index 1e79a0522a..1d6521eedc 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -26,6 +26,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn); void spr_read_generic(DisasContext *ctx, int gprn, int sprn); void spr_write_generic(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn); +void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn); void spr_write_PMC(DisasContext *ctx, int sprn, int gprn); void spr_read_xer(DisasContext *ctx, int gprn, int sprn); void spr_write_xer(DisasContext *ctx, int sprn, int gprn); --=20 2.31.1 From nobody Tue Apr 23 10:48:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637853487333635.5324386685472; Thu, 25 Nov 2021 07:18:07 -0800 (PST) Received: from localhost ([::1]:33956 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mqGVi-0000pu-9w for importer@patchew.org; Thu, 25 Nov 2021 10:18:06 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37326) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mqGMc-00030D-RO; Thu, 25 Nov 2021 10:08:42 -0500 Received: from [2607:f8b0:4864:20::929] (port=34601 helo=mail-ua1-x929.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mqGMZ-00021p-No; Thu, 25 Nov 2021 10:08:42 -0500 Received: by mail-ua1-x929.google.com with SMTP id n6so12972156uak.1; Thu, 25 Nov 2021 07:08:39 -0800 (PST) Received: from rekt.ibmuc.com ([191.19.215.188]) by smtp.gmail.com with ESMTPSA id i27sm2081057uab.8.2021.11.25.07.08.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Nov 2021 07:08:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L15TyunQSPLpeyDwTDac2HcG6DjqdeVGyLe9GooXuGY=; b=dIMmzGYSdjQjsjv6AxqtX66pqqhAIjDR+N9mSOlcodba+GCInqYDgJZDdpym5L0q2c Eal0eym3wLd5eXNFEyotV440MZl5iWjCtcQ7v+yoAt2nT+IIf60uBdwd/7a8wNWfddID WDjMh9u/menOEA6wVaUqCuWD9OoT0QjZKzb5M23n5sxB+g15dwHPyasfUpBmFkCLI7by 2Pz+MRiHFCN2rruyhunbRe5BRKx8Ak3D9nuP8Bv0m64paU+hJF7uzRfs/4oaZ+PxY3bz vuqulR3ajsvD2L/rvUDkNINj6D9ydRi4dMzUCa+HhKe536NP8P0KPZ0ZeaXmppwdvfzo IkYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L15TyunQSPLpeyDwTDac2HcG6DjqdeVGyLe9GooXuGY=; b=I0RG/lGZQeVp0xPNHdX5kRe4DfoqZQfKmxFkkDtauITtanlZlLiuHxn/jYN3CjHdF6 D+i7JgS8Hyz61O8j3DLWmDVzNWkSO0LDKo+nPZtXtVejgZIOpGkfIeMZsMOkAgYkHAuk I1g0AukF0YQIaT6yF/HAMCZT9MrfmQ7tb4hYJjgp69XRd4WXdrGHPBc4uOCVn/kVIt4G gEaTHQuh7xy0DkhLh8Hgj9Uo9yeReq8g07zkH8IXPyy88fz+NHTDgicr0WlRBhbSEMFe tBUQZXM7WEYLpZTTLrNBvKcy6bVuf3LHhmnIWMzZdQul2ZRht58vsNDDbSJylTQ7ReIK 5usg== X-Gm-Message-State: AOAM531Ol2aykt58u8rFC7VS5236Tr12F3fy1tB4rxUU2GzEYTjFRTxh OME5613RQ2uIyeC/zGfpuW6ygxH8KIo= X-Google-Smtp-Source: ABdhPJz0zCJXVlbhRWas4ifNdZLffb84oPzxjq2E10kcx85V77f1hj8eIYJ2qJ4whsL5WKvdTveQ9g== X-Received: by 2002:a05:6102:5489:: with SMTP id bk9mr10395388vsb.37.1637852918336; Thu, 25 Nov 2021 07:08:38 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v8 05/10] target/ppc: enable PMU counter overflow with cycle events Date: Thu, 25 Nov 2021 12:08:12 -0300 Message-Id: <20211125150817.573204-6-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211125150817.573204-1-danielhb413@gmail.com> References: <20211125150817.573204-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::929 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::929; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x929.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1637853489157100001 Content-Type: text/plain; charset="utf-8" The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative conditions are enabled. This means that if the counter value overflows (i.e. exceeds 0x80000000) a performance monitor alert will occur. This alert can trigger an event-based exception (to be implemented in the next patches) if the MMCR0_EBE bit is set. For now, overflowing the counter when the PMC is counting cycles will just trigger a performance monitor alert. This is done by starting the overflow timer to expire in the moment the overflow would be occuring. The timer will call fire_PMC_interrupt() (via cpu_ppc_pmu_timer_cb) which will trigger the PMU alert and, if the conditions are met, an EBB exception. Signed-off-by: Daniel Henrique Barboza Reviewed-by: David Gibson --- target/ppc/cpu.h | 2 ++ target/ppc/power8-pmu.c | 80 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 9c732953f0..9b41b022e2 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -364,6 +364,8 @@ typedef enum { #define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */ #define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */ #define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */ +#define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */ +#define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */ /* MMCR0 userspace r/w mask */ #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE) /* MMCR2 userspace r/w mask */ diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index acdaee7459..01e0b9b8fc 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -23,6 +23,8 @@ =20 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) =20 +#define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL + static bool pmc_is_inactive(CPUPPCState *env, int sprn) { if (env->spr[SPR_POWER_MMCR0] & MMCR0_FC) { @@ -36,6 +38,15 @@ static bool pmc_is_inactive(CPUPPCState *env, int sprn) return env->spr[SPR_POWER_MMCR0] & MMCR0_FC56; } =20 +static bool pmc_has_overflow_enabled(CPUPPCState *env, int sprn) +{ + if (sprn =3D=3D SPR_POWER_PMC1) { + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE; + } + + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE; +} + /* * For PMCs 1-4, IBM POWER chips has support for an implementation * dependent event, 0x1E, that enables cycle counting. The Linux kernel @@ -123,6 +134,70 @@ static void pmu_update_cycles(CPUPPCState *env) env->pmu_base_time =3D now; } =20 +/* + * Helper function to retrieve the cycle overflow timer of the + * 'sprn' counter. Given that PMC5 doesn't have a timer, the + * amount of timers is less than the total counters and the PMC6 + * timer is the last of the array. + */ +static QEMUTimer *get_cyc_overflow_timer(CPUPPCState *env, int sprn) +{ + if (sprn =3D=3D SPR_POWER_PMC5) { + return NULL; + } + + if (sprn =3D=3D SPR_POWER_PMC6) { + return env->pmu_cyc_overflow_timers[PMU_TIMERS_NUM - 1]; + } + + return env->pmu_cyc_overflow_timers[sprn - SPR_POWER_PMC1]; +} + +static void pmc_update_overflow_timer(CPUPPCState *env, int sprn) +{ + QEMUTimer *pmc_overflow_timer; + int64_t timeout; + + /* PMC5 does not have an overflow timer */ + if (sprn =3D=3D SPR_POWER_PMC5) { + return; + } + + pmc_overflow_timer =3D get_cyc_overflow_timer(env, sprn); + + if (pmc_get_event(env, sprn) !=3D PMU_EVENT_CYCLES || + !pmc_has_overflow_enabled(env, sprn)) { + /* Overflow timer is not needed for this counter */ + timer_del(pmc_overflow_timer); + return; + } + + if (env->spr[sprn] >=3D PMC_COUNTER_NEGATIVE_VAL) { + timeout =3D 0; + } else { + timeout =3D PMC_COUNTER_NEGATIVE_VAL - env->spr[sprn]; + } + + /* + * Use timer_mod_anticipate() because an overflow timer might + * be already running for this PMC. + */ + timer_mod_anticipate(pmc_overflow_timer, env->pmu_base_time + timeout); +} + +static void pmu_update_overflow_timers(CPUPPCState *env) +{ + int sprn; + + /* + * Scroll through all PMCs and start counter overflow timers for + * PM_CYC events, if needed. + */ + for (sprn =3D SPR_POWER_PMC1; sprn <=3D SPR_POWER_PMC6; sprn++) { + pmc_update_overflow_timer(env, sprn); + } +} + void helper_store_mmcr0(CPUPPCState *env, target_ulong value) { target_ulong curr_value =3D env->spr[SPR_POWER_MMCR0]; @@ -143,6 +218,9 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong = value) (curr_FC !=3D new_FC)) { hreg_compute_hflags(env); } + + /* Update cycle overflow timers with the current MMCR0 state */ + pmu_update_overflow_timers(env); } =20 void helper_store_mmcr1(CPUPPCState *env, uint64_t value) @@ -164,6 +242,8 @@ void helper_store_pmc(CPUPPCState *env, uint32_t sprn, = uint64_t value) pmu_update_cycles(env); =20 env->spr[sprn] =3D value; + + pmc_update_overflow_timer(env, sprn); } =20 static void fire_PMC_interrupt(PowerPCCPU *cpu) --=20 2.31.1 From nobody Tue Apr 23 10:48:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637853236595268.207073804483; Thu, 25 Nov 2021 07:13:56 -0800 (PST) Received: from localhost ([::1]:52230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mqGRf-0002TW-4S for importer@patchew.org; Thu, 25 Nov 2021 10:13:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37354) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mqGMf-00036L-9r; Thu, 25 Nov 2021 10:08:45 -0500 Received: from [2607:f8b0:4864:20::933] (port=45933 helo=mail-ua1-x933.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mqGMc-000222-O8; Thu, 25 Nov 2021 10:08:45 -0500 Received: by mail-ua1-x933.google.com with SMTP id ay21so12881763uab.12; Thu, 25 Nov 2021 07:08:41 -0800 (PST) Received: from rekt.ibmuc.com ([191.19.215.188]) by smtp.gmail.com with ESMTPSA id i27sm2081057uab.8.2021.11.25.07.08.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Nov 2021 07:08:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WiBgOYsCCyrj24xlUrZfxtYyn1qT8pceu1C4TQlPVeE=; b=QWZw1xofejv+wS6aUDL6XGvEVWMcd1jEO8sKlABfYsn/+OCD95xUpYkU9YQ3bq/qPs ABe2ICCuNsYPcCvTjcPqR9oM/pn7BLWwYB00GFbbRUHPdyvv1geOB9V2GB+6v1acnVz6 fJlshz1strqzm6dlt/p1RjKThxQJ6SnLKnwY0jliqhun2d4cohBqyM/uOoCtBYBG+6g9 6OHPdUJGlnZoj0bezZUTF4yHbcCP2QTXKS7etnvzNuZFCNQ8F/EyiTqAbiauHVFnABvh zX+6FvYjDgh6Kc9ug+jLFuEp6KLcWFE4z+0nSDeEV6vUhhKj9WgRInusc/9Ul5pOnR3A XK4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WiBgOYsCCyrj24xlUrZfxtYyn1qT8pceu1C4TQlPVeE=; b=nc5gjHsQ7Ijui/LDpzuRGB5yt1HbMizXcYdyHxh6/UWSD39CGMY7g3vpE6nUQSEDw6 BN1cq9axCmCVXA7RaO3N0cofYr4JPK5shBvjY7II9fYKWMK6nM51bTEz+6956Ca12YhN FRQ05VGtcfP31kh/+8PbFTJO7g/jcpoHlhJ1ZAWSQHiA5bODFQgHt0lBUN5Krg7Ni07u F5dQwuuf1xkn9iYldz1bw4YAdKnEGeeG503tbxrZAsRiir8SwvhUQqYPywNRUepX6rWt kKSy2IzbkGEr5jwLh0wgwrbxLJexvv6swR3kcwSfqVdCrwEleByWE7GJnHlawX3DzOq7 TDQQ== X-Gm-Message-State: AOAM533Be60a3zFReTHujOAzrZ9X9I2x/1FXy2cL6Aw/mxDgMiuj+eM9 wpo7IVezQvm8uQMb7LlAHJN9WaaJu1g= X-Google-Smtp-Source: ABdhPJwQ/2e4sYHmIfTxAq5rd2NwFT0XX7mCoRhi1+fmpZJ58QrW/l+62T2mel5zb/Y+bpgySPFEtA== X-Received: by 2002:a67:d80c:: with SMTP id e12mr10337500vsj.18.1637852920404; Thu, 25 Nov 2021 07:08:40 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v8 06/10] target/ppc: enable PMU instruction count Date: Thu, 25 Nov 2021 12:08:13 -0300 Message-Id: <20211125150817.573204-7-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211125150817.573204-1-danielhb413@gmail.com> References: <20211125150817.573204-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::933 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::933; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x933.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1637853238251100001 Content-Type: text/plain; charset="utf-8" The PMU is already counting cycles by calculating time elapsed in nanoseconds. Counting instructions is a different matter and requires another approach. This patch adds the capability of counting completed instructions (Perf event PM_INST_CMPL) by counting the amount of instructions translated in each translation block right before exiting it. A new pmu_count_insns() helper in translation.c was added to do that. After verifying that the PMU is running (MMCR0_FC bit not set), call helper_insns_inc(). This new helper from power8-pmu.c will add the instructions to the relevant counters. It'll also be responsible for triggering counter negative overflows as it is already being done with cycles. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 1 + target/ppc/helper.h | 1 + target/ppc/helper_regs.c | 4 +++ target/ppc/power8-pmu-regs.c.inc | 6 +++++ target/ppc/power8-pmu.c | 38 ++++++++++++++++++++++++++ target/ppc/translate.c | 46 ++++++++++++++++++++++++++++++++ 6 files changed, 96 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 9b41b022e2..38cd2b5c43 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -656,6 +656,7 @@ enum { HFLAGS_PR =3D 14, /* MSR_PR */ HFLAGS_PMCC0 =3D 15, /* MMCR0 PMCC bit 0 */ HFLAGS_PMCC1 =3D 16, /* MMCR0 PMCC bit 1 */ + HFLAGS_MMCR0FC =3D 17, /* MMCR0 FC bit */ HFLAGS_VSX =3D 23, /* MSR_VSX if cpu has VSX */ HFLAGS_VR =3D 25, /* MSR_VR if cpu has VRE */ =20 diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 94b4690375..d8a23e054a 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -24,6 +24,7 @@ DEF_HELPER_2(store_mmcr0, void, env, tl) DEF_HELPER_2(store_mmcr1, void, env, tl) DEF_HELPER_3(store_pmc, void, env, i32, i64) DEF_HELPER_2(read_pmc, tl, env, i32) +DEF_HELPER_2(insns_inc, void, env, i32) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 99562edd57..875c2fdfc6 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -115,6 +115,10 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState = *env) if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC1) { hflags |=3D 1 << HFLAGS_PMCC1; } + if (env->spr[SPR_POWER_MMCR0] & MMCR0_FC) { + hflags |=3D 1 << HFLAGS_MMCR0FC; + } + =20 #ifndef CONFIG_USER_ONLY if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.= c.inc index 25b13ad564..580e4e41b2 100644 --- a/target/ppc/power8-pmu-regs.c.inc +++ b/target/ppc/power8-pmu-regs.c.inc @@ -113,6 +113,12 @@ static void write_MMCR0_common(DisasContext *ctx, TCGv= val) */ gen_icount_io_start(ctx); gen_helper_store_mmcr0(cpu_env, val); + + /* + * End the translation block because MMCR0 writes can change + * ctx->pmu_frozen. + */ + ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; } =20 void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn) diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 01e0b9b8fc..59d0def79d 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -112,6 +112,30 @@ static PMUEventType pmc_get_event(CPUPPCState *env, in= t sprn) return evt_type; } =20 +static bool pmu_increment_insns(CPUPPCState *env, uint32_t num_insns) +{ + bool overflow_triggered =3D false; + int sprn; + + /* PMC6 never counts instructions */ + for (sprn =3D SPR_POWER_PMC1; sprn <=3D SPR_POWER_PMC5; sprn++) { + if (pmc_get_event(env, sprn) !=3D PMU_EVENT_INSTRUCTIONS) { + continue; + } + + env->spr[sprn] +=3D num_insns; + + if (env->spr[sprn] >=3D PMC_COUNTER_NEGATIVE_VAL && + pmc_has_overflow_enabled(env, sprn)) { + + overflow_triggered =3D true; + env->spr[sprn] =3D PMC_COUNTER_NEGATIVE_VAL; + } + } + + return overflow_triggered; +} + static void pmu_update_cycles(CPUPPCState *env) { uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -258,6 +282,20 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu) return; } =20 +/* This helper assumes that the PMC is running. */ +void helper_insns_inc(CPUPPCState *env, uint32_t num_insns) +{ + bool overflow_triggered; + PowerPCCPU *cpu; + + overflow_triggered =3D pmu_increment_insns(env, num_insns); + + if (overflow_triggered) { + cpu =3D env_archcpu(env); + fire_PMC_interrupt(cpu); + } +} + static void cpu_ppc_pmu_timer_cb(void *opaque) { PowerPCCPU *cpu =3D opaque; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 9960df6e18..ccc83d0603 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -177,6 +177,7 @@ struct DisasContext { bool hr; bool mmcr0_pmcc0; bool mmcr0_pmcc1; + bool pmu_frozen; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; uint32_t flags; @@ -4170,6 +4171,31 @@ static inline void gen_update_cfar(DisasContext *ctx= , target_ulong nip) #endif } =20 +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +static void pmu_count_insns(DisasContext *ctx) +{ + /* Do not bother calling the helper if the PMU is frozen */ + if (ctx->pmu_frozen) { + return; + } + + /* + * The PMU insns_inc() helper stops the internal PMU timer if a + * counter overflows happens. In that case, if the guest is + * running with icount and we do not handle it beforehand, + * the helper can trigger a 'bad icount read'. + */ + gen_icount_io_start(ctx); + + gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); +} +#else +static void pmu_count_insns(DisasContext *ctx) +{ + return; +} +#endif + static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) { return translator_use_goto_tb(&ctx->base, dest); @@ -4180,6 +4206,14 @@ static void gen_lookup_and_goto_ptr(DisasContext *ct= x) if (unlikely(ctx->singlestep_enabled)) { gen_debug_exception(ctx); } else { + /* + * tcg_gen_lookup_and_goto_ptr will exit the TB if + * CF_NO_GOTO_PTR is set. Count insns now. + */ + if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { + pmu_count_insns(ctx); + } + tcg_gen_lookup_and_goto_ptr(); } } @@ -4191,6 +4225,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, tar= get_ulong dest) dest =3D (uint32_t) dest; } if (use_goto_tb(ctx, dest)) { + pmu_count_insns(ctx); tcg_gen_goto_tb(n); tcg_gen_movi_tl(cpu_nip, dest & ~3); tcg_gen_exit_tb(ctx->base.tb, n); @@ -8458,6 +8493,7 @@ static void ppc_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->hr =3D (hflags >> HFLAGS_HR) & 1; ctx->mmcr0_pmcc0 =3D (hflags >> HFLAGS_PMCC0) & 1; ctx->mmcr0_pmcc1 =3D (hflags >> HFLAGS_PMCC1) & 1; + ctx->pmu_frozen =3D (hflags >> HFLAGS_MMCR0FC) & 1; =20 ctx->singlestep_enabled =3D 0; if ((hflags >> HFLAGS_SE) & 1) { @@ -8564,6 +8600,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cs) switch (is_jmp) { case DISAS_TOO_MANY: if (use_goto_tb(ctx, nip)) { + pmu_count_insns(ctx); tcg_gen_goto_tb(0); gen_update_nip(ctx, nip); tcg_gen_exit_tb(ctx->base.tb, 0); @@ -8574,6 +8611,14 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase,= CPUState *cs) gen_update_nip(ctx, nip); /* fall through */ case DISAS_CHAIN: + /* + * tcg_gen_lookup_and_goto_ptr will exit the TB if + * CF_NO_GOTO_PTR is set. Count insns now. + */ + if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { + pmu_count_insns(ctx); + } + tcg_gen_lookup_and_goto_ptr(); break; =20 @@ -8581,6 +8626,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cs) gen_update_nip(ctx, nip); /* fall through */ case DISAS_EXIT: + pmu_count_insns(ctx); tcg_gen_exit_tb(NULL, 0); break; =20 --=20 2.31.1 From nobody Tue Apr 23 10:48:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637853480092490.10102266227534; Thu, 25 Nov 2021 07:18:00 -0800 (PST) Received: from localhost ([::1]:33298 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mqGVb-0000PJ-2B for importer@patchew.org; Thu, 25 Nov 2021 10:17:59 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37362) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mqGMf-00037Q-RE; Thu, 25 Nov 2021 10:08:45 -0500 Received: from [2607:f8b0:4864:20::92b] (port=34604 helo=mail-ua1-x92b.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mqGMd-00022F-PU; Thu, 25 Nov 2021 10:08:45 -0500 Received: by mail-ua1-x92b.google.com with SMTP id n6so12972541uak.1; Thu, 25 Nov 2021 07:08:43 -0800 (PST) Received: from rekt.ibmuc.com ([191.19.215.188]) by smtp.gmail.com with ESMTPSA id i27sm2081057uab.8.2021.11.25.07.08.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Nov 2021 07:08:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ASnNF0smJnq9DV9q0P1fSPtqI3ed2Y8rsHWBjOhfCLE=; b=NKh7dYcQHwIWhLdODPFVrfM8RTw38yFGeI9dcW8Ht2xobYiy7eENuivU8y6fEglGGA pm6pVv3CnkOmPYA0KaB758Y9mOsu8o9Zo5/FU+d51c0mwJ+6HT7r+2+BfDNuGrMBFwgi 1riAbvd+D9mGhVEQpOv8rAOPa5YkMgSuzANs8MGenG5ldeadRtH6hydtlKd5ADmRXd+T mOdn+8mEeD7NOKAc9QTe25OPR27ZBQUaM7Y7XlZGp4sc1xPKolg77uP7dS75MAqbnHZF ZCNjXhQ/aKPuU9ncaXImyPzTeHNOW97h99WdQjf+sLR87Y22JyeBPdl+Y0XtyHCnuxMI asVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ASnNF0smJnq9DV9q0P1fSPtqI3ed2Y8rsHWBjOhfCLE=; b=ZxK0SylhaUXgbPD12LOJbHZSHs5m9Gsmj1hoLG2WWKgdo2nFuVWcBW2G48/xVWx4sK ULL3Y464uflp49S1KrVzqGp2FsNUrH0piVe0Kbyupl2gFiDU9XX4WVCt0SG5SIKZ4Ifs lLxNVuV0iTBEJ289wLADhjCS1vz+Sr3e8ru0pzY5yzHYov/8ssgJ3xbUlSRr9ubbRsy2 cKFclCjPgoF+XxFxqJ0Hc+ijXiISFWY3Ca1i5fZgp4brpBZNQKlqFZuITxMO70DENRZZ SjndLiAKEdwIkxUC5QIWKOYljys6qsoNosUZbTOXeYLydyJmyw0cv1LNOKoylKOeFjmy TA/A== X-Gm-Message-State: AOAM530I0H/QkmPQNzT6OqDVZDwTUiMLJqI5QILu1BGccDosOsL2bifd Z0Iu98AJ7OUgwcthc5UjiVqh6cmaWM4= X-Google-Smtp-Source: ABdhPJzMv0HlxhKHDt2TOn8rlZ8RUnfp1W1zvP0RWZunp4q8ejPbZPNq+iq/pgybBnQixWvXaBInDg== X-Received: by 2002:a05:6102:a4c:: with SMTP id i12mr10088772vss.41.1637852922482; Thu, 25 Nov 2021 07:08:42 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v8 07/10] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event Date: Thu, 25 Nov 2021 12:08:14 -0300 Message-Id: <20211125150817.573204-8-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211125150817.573204-1-danielhb413@gmail.com> References: <20211125150817.573204-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::92b (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::92b; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x92b.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1637853481750100001 Content-Type: text/plain; charset="utf-8" PM_RUN_INST_CMPL, instructions completed with the run latch set, is the architected PowerISA v3.1 event defined with PMC4SEL =3D 0xFA. Implement it by checking for the CTRL RUN bit before incrementing the counter. To make this work properly we also need to force a new translation block each time SPR_CTRL is written. A small tweak in pmu_increment_insns() is then needed to only increment this event if the thread has the run latch. Signed-off-by: Daniel Henrique Barboza Reviewed-by: David Gibson --- target/ppc/cpu.h | 4 ++++ target/ppc/cpu_init.c | 2 +- target/ppc/power8-pmu.c | 24 ++++++++++++++++++++++-- target/ppc/spr_tcg.h | 1 + target/ppc/translate.c | 12 ++++++++++++ 5 files changed, 40 insertions(+), 3 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 38cd2b5c43..993884164f 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -304,6 +304,7 @@ typedef enum { PMU_EVENT_INACTIVE, PMU_EVENT_CYCLES, PMU_EVENT_INSTRUCTIONS, + PMU_EVENT_INSN_RUN_LATCH, } PMUEventType; =20 /*************************************************************************= ****/ @@ -389,6 +390,9 @@ typedef enum { #define MMCR1_PMC4SEL_START 56 #define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE) =20 +/* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */ +#define CTRL_RUN PPC_BIT(63) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 2d72dde26d..ecce4c7c1e 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6749,7 +6749,7 @@ static void register_book3s_ctrl_sprs(CPUPPCState *en= v) { spr_register(env, SPR_CTRL, "SPR_CTRL", SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_generic, + SPR_NOACCESS, &spr_write_CTRL, 0x00000000); spr_register(env, SPR_UCTRL, "SPR_UCTRL", &spr_read_ureg, SPR_NOACCESS, diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 59d0def79d..98797f0b2f 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -96,6 +96,15 @@ static PMUEventType pmc_get_event(CPUPPCState *env, int = sprn) evt_type =3D PMU_EVENT_CYCLES; } break; + case 0xFA: + /* + * PMC4SEL =3D 0xFA is the "instructions completed + * with run latch set" event. + */ + if (sprn =3D=3D SPR_POWER_PMC4) { + evt_type =3D PMU_EVENT_INSN_RUN_LATCH; + } + break; case 0xFE: /* * PMC1SEL =3D 0xFE is the architected PowerISA v3.1 @@ -119,11 +128,22 @@ static bool pmu_increment_insns(CPUPPCState *env, uin= t32_t num_insns) =20 /* PMC6 never counts instructions */ for (sprn =3D SPR_POWER_PMC1; sprn <=3D SPR_POWER_PMC5; sprn++) { - if (pmc_get_event(env, sprn) !=3D PMU_EVENT_INSTRUCTIONS) { + PMUEventType evt_type =3D pmc_get_event(env, sprn); + bool insn_event =3D evt_type =3D=3D PMU_EVENT_INSTRUCTIONS || + evt_type =3D=3D PMU_EVENT_INSN_RUN_LATCH; + + if (pmc_is_inactive(env, sprn) || !insn_event) { continue; } =20 - env->spr[sprn] +=3D num_insns; + if (evt_type =3D=3D PMU_EVENT_INSTRUCTIONS) { + env->spr[sprn] +=3D num_insns; + } + + if (evt_type =3D=3D PMU_EVENT_INSN_RUN_LATCH && + env->spr[SPR_CTRL] & CTRL_RUN) { + env->spr[sprn] +=3D num_insns; + } =20 if (env->spr[sprn] >=3D PMC_COUNTER_NEGATIVE_VAL && pmc_has_overflow_enabled(env, sprn)) { diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index 1d6521eedc..f98d97c0ba 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -28,6 +28,7 @@ void spr_write_generic(DisasContext *ctx, int sprn, int g= prn); void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn); void spr_write_PMC(DisasContext *ctx, int sprn, int gprn); +void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn); void spr_read_xer(DisasContext *ctx, int gprn, int sprn); void spr_write_xer(DisasContext *ctx, int sprn, int gprn); void spr_read_lr(DisasContext *ctx, int gprn, int sprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index ccc83d0603..d0e361a9d1 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -403,6 +403,18 @@ void spr_write_generic(DisasContext *ctx, int sprn, in= t gprn) spr_store_dump_spr(sprn); } =20 +void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) +{ + spr_write_generic(ctx, sprn, gprn); + + /* + * SPR_CTRL writes must force a new translation block, + * allowing the PMU to calculate the run latch events with + * more accuracy. + */ + ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; +} + #if !defined(CONFIG_USER_ONLY) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) { --=20 2.31.1 From nobody Tue Apr 23 10:48:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163785332037041.71383242550155; Thu, 25 Nov 2021 07:15:20 -0800 (PST) Received: from localhost ([::1]:55824 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mqGT0-0004uo-Lh for importer@patchew.org; Thu, 25 Nov 2021 10:15:18 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37392) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mqGMk-0003Nq-0i; Thu, 25 Nov 2021 10:08:50 -0500 Received: from [2607:f8b0:4864:20::929] (port=44605 helo=mail-ua1-x929.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mqGMg-00023q-7M; Thu, 25 Nov 2021 10:08:49 -0500 Received: by mail-ua1-x929.google.com with SMTP id p2so12867879uad.11; Thu, 25 Nov 2021 07:08:45 -0800 (PST) Received: from rekt.ibmuc.com ([191.19.215.188]) by smtp.gmail.com with ESMTPSA id i27sm2081057uab.8.2021.11.25.07.08.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Nov 2021 07:08:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LMMYRmFQnYNgkPtDchZ6nLq0mLdtchFnKluavIDwVCM=; b=Dcm/9IOnCGh0q+Z1K0Xr4+qJ4YVOGk4lJDKx519EaeasBYSwoXochvJ4i2fUBNmxFy sm+oqmFlZ2CJeSok/Ktr5RzCBBRtmQHvpQel6G7rJLhVle+50+Y1pRsVsVAoVbPBMrub Ex/YXiC9V+wX1LNFNLCyJ8N1YoVJYvUR7wwQvPEoiKGt0iULBuPIcz9vi2RX1ErSAcYw L7VHrZYGEqccQf5p8nPLBdx/PrqIy29+5uRevwEMPwvjyyQCR+/SHZIoEWiM1ozzbU+P NS3vBi+98GhAqukLFzTE/2lz9231icU4Av7FJ45W9SWhWoDtylszxc5BzZRAVd8UnADA 3/iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LMMYRmFQnYNgkPtDchZ6nLq0mLdtchFnKluavIDwVCM=; b=Qi/mXlE6p+GD5RiVh7Rs31EKhgA/P2QP7xcL3pQ5w2xcc5A/m/sJUYNbzGI1pqL08N /eRrBa1U4KW7cPjsJ1+At6ytQ281MLVfR8qdCiHglGZzE8WGbQra3u45K8eW+Lm8PnNq DRk0f6lZyX2CzLBSR7l/oo6GRQJQX6opnPJggFxN2FPvqgyqtJVTtNfrCms5XgdRgKK+ LspC58WIzCe7YCFm/Q9IPJfOFk2q11XW5PG58pJo1vPMmUfjG0o/f+qTH9+ZAL5Sohan +gKNz/g70Ytphp513zFg+g4vhRCzzGmBlIJx/uZO9YFxdPq7afdflj6GNSlMytYr05+j 0Epg== X-Gm-Message-State: AOAM533+c35+bqOxVd8Ad16+o0u1GRoSWVK0CY7Fa2bquo14B7mlH4M5 3u38YKUL+v4TcUu8Tf3lANHvodACql8= X-Google-Smtp-Source: ABdhPJxyfZl1981mRcL+nj5TbLbSX2USRfXc71QumAHbXuJIXpS9q3LXHRZfRiRA4CHJf0mXsNfgoA== X-Received: by 2002:a67:ab4c:: with SMTP id k12mr10097751vsh.73.1637852924833; Thu, 25 Nov 2021 07:08:44 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v8 08/10] PPC64/TCG: Implement 'rfebb' instruction Date: Thu, 25 Nov 2021 12:08:15 -0300 Message-Id: <20211125150817.573204-9-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211125150817.573204-1-danielhb413@gmail.com> References: <20211125150817.573204-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::929 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::929; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x929.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , richard.henderson@linaro.org, qemu-ppc@nongnu.org, clg@kaod.org, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1637853321840100003 Content-Type: text/plain; charset="utf-8" An Event-Based Branch (EBB) allows applications to change the NIA when a event-based exception occurs. Event-based exceptions are enabled by setting the Branch Event Status and Control Register (BESCR). If the event-based exception is enabled when the exception occurs, an EBB happens. The following operations happens during an EBB: - Global Enable (GE) bit of BESCR is set to 0; - bits 0-61 of the Event-Based Branch Return Register (EBBRR) are set to the the effective address of the NIA that would have executed if the EBB didn't happen; - Instruction fetch and execution will continue in the effective address contained in the Event-Based Branch Handler Register (EBBHR). The EBB Handler will process the event and then execute the Return From Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then redirects execution to the address pointed in EBBRR. This process is described in the PowerISA v3.1, Book II, Chapter 6 [1]. This patch implements the rfebb instruction. Descriptions of all relevant BESCR bits are also added - this patch is only using BESCR_GE, but the next patches will use the remaining bits. [1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf Reviewed-by: Matheus Ferst Signed-off-by: Daniel Henrique Barboza Reviewed-by: David Gibson --- target/ppc/cpu.h | 13 ++++++++++ target/ppc/excp_helper.c | 31 ++++++++++++++++++++++++ target/ppc/helper.h | 1 + target/ppc/insn32.decode | 5 ++++ target/ppc/translate.c | 2 ++ target/ppc/translate/branch-impl.c.inc | 33 ++++++++++++++++++++++++++ 6 files changed, 85 insertions(+) create mode 100644 target/ppc/translate/branch-impl.c.inc diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 993884164f..edb4488176 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -393,6 +393,19 @@ typedef enum { /* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */ #define CTRL_RUN PPC_BIT(63) =20 +/* EBB/BESCR bits */ +/* Global Enable */ +#define BESCR_GE PPC_BIT(0) +/* External Event-based Exception Enable */ +#define BESCR_EE PPC_BIT(30) +/* Performance Monitor Event-based Exception Enable */ +#define BESCR_PME PPC_BIT(31) +/* External Event-based Exception Occurred */ +#define BESCR_EEO PPC_BIT(62) +/* Performance Monitor Event-based Exception Occurred */ +#define BESCR_PMEO PPC_BIT(63) +#define BESCR_INVALID PPC_BITMASK(32, 33) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 17607adbe4..7ead32279c 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1250,6 +1250,37 @@ void helper_hrfid(CPUPPCState *env) } #endif =20 +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +void helper_rfebb(CPUPPCState *env, target_ulong s) +{ + target_ulong msr =3D env->msr; + + /* + * Handling of BESCR bits 32:33 according to PowerISA v3.1: + * + * "If BESCR 32:33 !=3D 0b00 the instruction is treated as if + * the instruction form were invalid." + */ + if (env->spr[SPR_BESCR] & BESCR_INVALID) { + raise_exception_err(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); + } + + env->nip =3D env->spr[SPR_EBBRR]; + + /* Switching to 32-bit ? Crop the nip */ + if (!msr_is_64bit(env, msr)) { + env->nip =3D (uint32_t)env->spr[SPR_EBBRR]; + } + + if (s) { + env->spr[SPR_BESCR] |=3D BESCR_GE; + } else { + env->spr[SPR_BESCR] &=3D ~BESCR_GE; + } +} +#endif + /*************************************************************************= ****/ /* Embedded PowerPC specific helpers */ void helper_40x_rfci(CPUPPCState *env) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index d8a23e054a..b0535b389b 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -18,6 +18,7 @@ DEF_HELPER_2(pminsn, void, env, i32) DEF_HELPER_1(rfid, void, env) DEF_HELPER_1(rfscv, void, env) DEF_HELPER_1(hrfid, void, env) +DEF_HELPER_2(rfebb, void, env, tl) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index e135b8aba4..6cad783dde 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -427,3 +427,8 @@ XXSPLTW 111100 ..... ---.. ..... 010100100 . . = @XX2 ## VSX Vector Load Special Value Instruction =20 LXVKQ 111100 ..... 11111 ..... 0101101000 . @X_uim5 + +### rfebb +&XL_s s:uint8_t +@XL_s ......-------------- s:1 .......... - &XL_s +RFEBB 010011-------------- . 0010010010 - @XL_s diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d0e361a9d1..d643a83a51 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7467,6 +7467,8 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d= , arg_PLS_D *a) =20 #include "translate/spe-impl.c.inc" =20 +#include "translate/branch-impl.c.inc" + /* Handles lfdp, lxsd, lxssp */ static void gen_dform39(DisasContext *ctx) { diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/= branch-impl.c.inc new file mode 100644 index 0000000000..29cfa11854 --- /dev/null +++ b/target/ppc/translate/branch-impl.c.inc @@ -0,0 +1,33 @@ +/* + * Power ISA decode for branch instructions + * + * Copyright IBM Corp. 2021 + * + * Authors: + * Daniel Henrique Barboza + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + +static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + + gen_icount_io_start(ctx); + gen_update_cfar(ctx, ctx->cia); + gen_helper_rfebb(cpu_env, cpu_gpr[arg->s]); + + ctx->base.is_jmp =3D DISAS_CHAIN; + + return true; +} +#else +static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) +{ + gen_invalid(ctx); + return true; +} +#endif --=20 2.31.1 From nobody Tue Apr 23 10:48:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637853280741438.45492871007866; Thu, 25 Nov 2021 07:14:40 -0800 (PST) Received: from localhost ([::1]:54862 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mqGSN-0004EY-LV for importer@patchew.org; Thu, 25 Nov 2021 10:14:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37396) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mqGMk-0003Q0-Gh; Thu, 25 Nov 2021 10:08:50 -0500 Received: from [2607:f8b0:4864:20::930] (port=44612 helo=mail-ua1-x930.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mqGMi-00024E-O2; Thu, 25 Nov 2021 10:08:50 -0500 Received: by mail-ua1-x930.google.com with SMTP id p2so12868198uad.11; Thu, 25 Nov 2021 07:08:48 -0800 (PST) Received: from rekt.ibmuc.com ([191.19.215.188]) by smtp.gmail.com with ESMTPSA id i27sm2081057uab.8.2021.11.25.07.08.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Nov 2021 07:08:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0omN+xJHnBlQIHF6mTkRJ6uMLE9dyTiQN5HDwhiyP2I=; b=BPpXQ09i6adPef4HRGFhiAIQsLbPxg7tTcwfxZNVn+doM5Buu6eQLPhyYpHGj5L8zR cq9TeatnyPNWE29Ya/InziXzh0PRatrxZ+yxGDhfwOVftYi+joXkDvCRNGDWCudVgC29 wLMWmVRB6FzbuC1VOsZK7WWqd9bWqVneokDK63kkDlnC88Vh4eN+ihf+Hdt6lcn6tDVd Cp6DWJEizTZ9ctDEFmae3IrIG+Q8K43iNAwM5Bgu8r33IMbtw6bgWonyi5s10soFqaUQ K0wOHDB48BnSQ+vj3sA452dIe7DiENW58uiAQOGPF1LzEGO03wNO+w0LKjstl+vXpn23 42EQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0omN+xJHnBlQIHF6mTkRJ6uMLE9dyTiQN5HDwhiyP2I=; b=TfQmKmAtn1SB7IvFvLnpfL4VM77zlOB3XgKgBFC4+jb9aNYaHxZV6vmCNmy/M2IoM1 g1Zzaomu3PkTz+NQNrAcWCRT4m3cTNqe9HJj0Jd2J8ksdkyJ71G9BfbdYbcn1AHen7j5 RCoUMv2xA9uTYewKbG8wPhs/eAsCHHrGmNzZEXDPnwztg6zZoH2UCsZgKeAB+tJfQ3A7 gP5lESEu/x4OyZ0GO3rbJFl4N66NAprxrDKj2vjZTyo45N5FiVAryiXMkLhjuXGOf/39 aGBTtAbUrulIT1i2XrUEdHpHXhzKhL99B4w0rF4O013D547O3A7g9EcpzlpeZ7vwn1Jp YSDA== X-Gm-Message-State: AOAM532ND6qkCDQd/PSPywiteR+Lz7jwJy7LO4OWRIiytiKNKIG/wUuN GCJ0pW4So/wsps9qBvKeo83HVj3I80w= X-Google-Smtp-Source: ABdhPJy+3HpJn/iVn1eUnmk+DtIhkNNH9ayzAEFQIa01wY7z2RiJq74Sd7VZ+k0r8BuAMlTSwS4BzA== X-Received: by 2002:ab0:2041:: with SMTP id g1mr26397936ual.131.1637852927347; Thu, 25 Nov 2021 07:08:47 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v8 09/10] target/ppc: PMU Event-Based exception support Date: Thu, 25 Nov 2021 12:08:16 -0300 Message-Id: <20211125150817.573204-10-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211125150817.573204-1-danielhb413@gmail.com> References: <20211125150817.573204-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::930 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::930; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x930.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Gustavo Romero , Gustavo Romero , Daniel Henrique Barboza , richard.henderson@linaro.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1637853282484100001 Content-Type: text/plain; charset="utf-8" From: Gustavo Romero Following up the rfebb implementation, this patch adds the EBB exception support that are triggered by Performance Monitor alerts. This exception occurs when an enabled PMU condition or event happens and both MMCR0_EBE and BESCR_PME are set. The supported PM alerts will consist of counter negative conditions of the PMU counters. This will be achieved by a timer mechanism that will predict when a counter becomes negative. The PMU timer callback will set the appropriate bits in MMCR0 and fire a PMC interrupt. The EBB exception code will then set the appropriate BESCR bits, set the next instruction pointer to the address pointed by the return register (SPR_EBBRR), and redirect execution to the handler (pointed by SPR_EBBHR). CC: Gustavo Romero Signed-off-by: Gustavo Romero Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 5 ++++- target/ppc/excp_helper.c | 29 +++++++++++++++++++++++++++++ target/ppc/power8-pmu.c | 35 +++++++++++++++++++++++++++++++++-- 3 files changed, 66 insertions(+), 3 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index edb4488176..28ae904d76 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -129,8 +129,10 @@ enum { /* ISA 3.00 additions */ POWERPC_EXCP_HVIRT =3D 101, POWERPC_EXCP_SYSCALL_VECTORED =3D 102, /* scv exception = */ + POWERPC_EXCP_EBB =3D 103, /* Event-based branch exception = */ + /* EOL = */ - POWERPC_EXCP_NB =3D 103, + POWERPC_EXCP_NB =3D 104, /* QEMU exceptions: special cases we want to stop translation = */ POWERPC_EXCP_SYSCALL_USER =3D 0x203, /* System call in user mode only = */ }; @@ -2453,6 +2455,7 @@ enum { PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */ PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt = */ PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt = */ + PPC_INTERRUPT_PMC, /* Hypervisor virtualization interrupt = */ }; =20 /* Processor Compatibility mask (PCR) */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 7ead32279c..a26d266fe6 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -799,6 +799,23 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int e= xcp_model, int excp) cpu_abort(cs, "Non maskable external exception " "is not implemented yet !\n"); break; + case POWERPC_EXCP_EBB: /* Event-based branch exception = */ + if ((env->spr[SPR_FSCR] & (1ull << FSCR_EBB)) && + (env->spr[SPR_BESCR] & BESCR_GE) && + (env->spr[SPR_BESCR] & BESCR_PME)) { + target_ulong nip; + + env->spr[SPR_BESCR] &=3D ~BESCR_GE; /* Clear GE */ + env->spr[SPR_BESCR] |=3D BESCR_PMEO; /* Set PMEO */ + env->spr[SPR_EBBRR] =3D env->nip; /* Save NIP for rfebb in= sn */ + nip =3D env->spr[SPR_EBBHR]; /* EBB handler */ + powerpc_set_excp_state(cpu, nip, env->msr); + } + /* + * This interrupt is handled by userspace. No need + * to proceed. + */ + return; default: excp_invalid: cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); @@ -1046,6 +1063,18 @@ static void ppc_hw_interrupt(CPUPPCState *env) powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_THERM); return; } + /* PMC -> Event-based branch exception */ + if (env->pending_interrupts & (1 << PPC_INTERRUPT_PMC)) { + /* + * Performance Monitor event-based exception can only + * occur in problem state. + */ + if (msr_pr =3D=3D 1) { + env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_PMC); + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EBB); + return; + } + } } =20 if (env->resume_as_sreset) { diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 98797f0b2f..330e0d2ae8 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -290,6 +290,15 @@ void helper_store_pmc(CPUPPCState *env, uint32_t sprn,= uint64_t value) pmc_update_overflow_timer(env, sprn); } =20 +static void pmu_delete_timers(CPUPPCState *env) +{ + int i; + + for (i =3D 0; i < PMU_TIMERS_NUM; i++) { + timer_del(env->pmu_cyc_overflow_timers[i]); + } +} + static void fire_PMC_interrupt(PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; @@ -298,8 +307,30 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu) return; } =20 - /* PMC interrupt not implemented yet */ - return; + pmu_update_cycles(env); + + if (env->spr[SPR_POWER_MMCR0] & MMCR0_FCECE) { + env->spr[SPR_POWER_MMCR0] &=3D ~MMCR0_FCECE; + env->spr[SPR_POWER_MMCR0] |=3D MMCR0_FC; + + /* Changing MMCR0_FC demands a new hflags compute */ + hreg_compute_hflags(env); + + /* + * Delete all pending timers if we need to freeze + * the PMC. We'll restart them when the PMC starts + * running again. + */ + pmu_delete_timers(env); + } + + if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE) { + env->spr[SPR_POWER_MMCR0] &=3D ~MMCR0_PMAE; + env->spr[SPR_POWER_MMCR0] |=3D MMCR0_PMAO; + } + + /* Fire the PMC hardware exception */ + ppc_set_irq(cpu, PPC_INTERRUPT_PMC, 1); } =20 /* This helper assumes that the PMC is running. */ --=20 2.31.1 From nobody Tue Apr 23 10:48:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637853693957761.0059719971607; Thu, 25 Nov 2021 07:21:33 -0800 (PST) Received: from localhost ([::1]:43572 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mqGZ2-0007NU-Cs for importer@patchew.org; Thu, 25 Nov 2021 10:21:32 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37426) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mqGMm-0003Yz-Nv; Thu, 25 Nov 2021 10:08:52 -0500 Received: from [2607:f8b0:4864:20::92b] (port=44608 helo=mail-ua1-x92b.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mqGMk-00024U-OU; Thu, 25 Nov 2021 10:08:52 -0500 Received: by mail-ua1-x92b.google.com with SMTP id p2so12868480uad.11; Thu, 25 Nov 2021 07:08:50 -0800 (PST) Received: from rekt.ibmuc.com ([191.19.215.188]) by smtp.gmail.com with ESMTPSA id i27sm2081057uab.8.2021.11.25.07.08.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Nov 2021 07:08:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wEhzjJ2tChIizKtHFKzSMHPFIqsyie4TVEusXUHYHu0=; b=aHRQSvR3uZOpdwAXuFXaXAS4XYu82M4H1IhsCwTg+cDcax+oNlYbMr0bEsWcC9IX9O LzMhUWbn0R/07nq3H+u96zBM6YNBnIk4YrqNzb0RHNftjroijnvrAGkvbStekkA9sNn1 aiMDFSaMFO/uLDDAwJmUfHIOjLCPpBMaEDzzWul0B7G0HGLWb2uoPVZqPAFq5lmYGwFU WmoTIrPCFq3M+LtD/kDJKJFg2qRwFrF69HxDcPa1GF82Z1cBuTIeuzc6U5AUAQiH7K9Z kXzoGT8kHcwUoYUso8gqUFzvW2+VXE3D5SQogaJyvzwcX1nOLEv2XUGW20sffCmO1VH3 XmnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wEhzjJ2tChIizKtHFKzSMHPFIqsyie4TVEusXUHYHu0=; b=bGhEyA5QV9Y8zlDktuX6KHTag7Tgn8MQI0EmPDOo2CKH58Yhzp+82Obqj+xnjYnye9 vS3i3pDedJZ8WdEo4cDNGHpatF5q6qKp0DPiAhvs2At0nhUzS6SXsedWpZ0YaWasmvpA 9KZZLydsbMAnuV/GnE54EUS9+hfqohasd3TtYZCOvqbW+BsIl0X8PodCZzONBOceZWXn xvQLTwLmj7c9gFRPTPtFjm/MQu+dAr85JuM5etZwO9Y/W9tKytsHx+EsyOVKwd4RlC7/ 3F4+IjEHPSelauTRq58G55SiCNaE0excC8ItSSSxCMlvLUoDqBcsvzB564HqQ/Rbs1nL NLaQ== X-Gm-Message-State: AOAM533rE3cz0z4ejWSkl9g/5Ub0fOaPKaI320Qci0EEHLf6cNaSU4L1 lnWPnsLc1hg7c7gxmbIMSFZRNxhOQ+g= X-Google-Smtp-Source: ABdhPJye7Hi1ij/ZPu/bNL6XIOv0cneWMnzDwRoIEoBS3SAxDRtzZoUhjVbNWhSQyZI9FHOix2hudg== X-Received: by 2002:a67:df90:: with SMTP id x16mr10168845vsk.52.1637852929445; Thu, 25 Nov 2021 07:08:49 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v8 10/10] target/ppc/excp_helper.c: EBB handling adjustments Date: Thu, 25 Nov 2021 12:08:17 -0300 Message-Id: <20211125150817.573204-11-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211125150817.573204-1-danielhb413@gmail.com> References: <20211125150817.573204-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::92b (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::92b; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x92b.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1637853694567100003 Content-Type: text/plain; charset="utf-8" The current logic is only considering event-based exceptions triggered by the performance monitor. This is true now, but we might want to add support for external event-based exceptions in the future. Let's make it a bit easier to do so by adding the bit logic that would happen in case we were dealing with an external event-based exception. While we're at it, add a few comments explaining why we're setting and clearing BESCR bits. Signed-off-by: Daniel Henrique Barboza Reviewed-by: David Gibson --- target/ppc/excp_helper.c | 45 ++++++++++++++++++++++++++++++++++------ 1 file changed, 39 insertions(+), 6 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index a26d266fe6..42e2fee9c8 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -801,14 +801,47 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int = excp_model, int excp) break; case POWERPC_EXCP_EBB: /* Event-based branch exception = */ if ((env->spr[SPR_FSCR] & (1ull << FSCR_EBB)) && - (env->spr[SPR_BESCR] & BESCR_GE) && - (env->spr[SPR_BESCR] & BESCR_PME)) { + (env->spr[SPR_BESCR] & BESCR_GE)) { target_ulong nip; =20 - env->spr[SPR_BESCR] &=3D ~BESCR_GE; /* Clear GE */ - env->spr[SPR_BESCR] |=3D BESCR_PMEO; /* Set PMEO */ - env->spr[SPR_EBBRR] =3D env->nip; /* Save NIP for rfebb in= sn */ - nip =3D env->spr[SPR_EBBHR]; /* EBB handler */ + /* + * If we have Performance Monitor Event-Based exception + * enabled (BESCR_PME) and a Performance Monitor alert + * occurred (MMCR0_PMAO), clear BESCR_PME and set BESCR_PMEO + * (Performance Monitor Event-Based Exception Occurred). + * + * Software is responsible for clearing both BESCR_PMEO and + * MMCR0_PMAO after the event has been handled. + */ + if ((env->spr[SPR_BESCR] & BESCR_PME) && + (env->spr[SPR_POWER_MMCR0] & MMCR0_PMAO)) { + env->spr[SPR_BESCR] &=3D ~BESCR_PME; + env->spr[SPR_BESCR] |=3D BESCR_PMEO; + } + + /* + * In the case of External Event-Based exceptions, do a + * similar logic with BESCR_EE and BESCR_EEO. BESCR_EEO must + * also be cleared by software. + * + * PowerISA 3.1 considers that we'll not have BESCR_PMEO and + * BESCR_EEO set at the same time. We can check for BESCR_PMEO + * being not set in step above to see if this exception was + * trigged by an external event. + */ + if (env->spr[SPR_BESCR] & BESCR_EE && + !(env->spr[SPR_BESCR] & BESCR_PMEO)) { + env->spr[SPR_BESCR] &=3D ~BESCR_EE; + env->spr[SPR_BESCR] |=3D BESCR_EEO; + } + + /* + * Clear BESCR_GE, save NIP for 'rfebb' and point the + * execution to the event handler (SPR_EBBHR) address. + */ + env->spr[SPR_BESCR] &=3D ~BESCR_GE; + env->spr[SPR_EBBRR] =3D env->nip; + nip =3D env->spr[SPR_EBBHR]; powerpc_set_excp_state(cpu, nip, env->msr); } /* --=20 2.31.1