From nobody Fri Apr 26 16:16:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637826792736288.1363055171977; Wed, 24 Nov 2021 23:53:12 -0800 (PST) Received: from localhost ([::1]:34226 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9Z9-0004nd-Mu for importer@patchew.org; Thu, 25 Nov 2021 02:53:11 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58796) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9N3-0001TW-1p; Thu, 25 Nov 2021 02:40:41 -0500 Received: from out28-51.mail.aliyun.com ([115.124.28.51]:42729) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9N0-0000rJ-1d; Thu, 25 Nov 2021 02:40:40 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LyzEfjn_1637826030) by smtp.aliyun-inc.com(10.147.40.44); Thu, 25 Nov 2021 15:40:31 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07596586|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.193991-0.000184048-0.805825; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047198; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.LyzEfjn_1637826030; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 01/22] target/riscv: Adjust pmpcfg access with mxl Date: Thu, 25 Nov 2021 15:39:30 +0800 Message-Id: <20211125073951.57678-2-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.51; envelope-from=zhiwei_liu@c-sky.com; helo=out28-51.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637826794136100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/csr.c | 18 ++++++++++++++++++ target/riscv/pmp.c | 12 ++++-------- 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9f41954894..ce20c3a970 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1407,9 +1407,22 @@ static RISCVException write_mseccfg(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 +static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index) +{ + if ((reg_index & 1) && (riscv_cpu_mxl(env) =3D=3D MXL_RV64)) { + return false; + } + return true; +} + static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) { + uint32_t reg_index =3D csrno - CSR_PMPCFG0; + + if (!check_pmp_reg_index(env, reg_index)) { + return RISCV_EXCP_ILLEGAL_INST; + } *val =3D pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); return RISCV_EXCP_NONE; } @@ -1417,6 +1430,11 @@ static RISCVException read_pmpcfg(CPURISCVState *env= , int csrno, static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val) { + uint32_t reg_index =3D csrno - CSR_PMPCFG0; + + if (!check_pmp_reg_index(env, reg_index)) { + return RISCV_EXCP_ILLEGAL_INST; + } pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); return RISCV_EXCP_NONE; } diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 54abf42583..81b61bb65c 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -463,16 +463,11 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t re= g_index, { int i; uint8_t cfg_val; + int pmpcfg_nums =3D 2 << riscv_cpu_mxl(env); =20 trace_pmpcfg_csr_write(env->mhartid, reg_index, val); =20 - if ((reg_index & 1) && (sizeof(target_ulong) =3D=3D 8)) { - qemu_log_mask(LOG_GUEST_ERROR, - "ignoring pmpcfg write - incorrect address\n"); - return; - } - - for (i =3D 0; i < sizeof(target_ulong); i++) { + for (i =3D 0; i < pmpcfg_nums; i++) { cfg_val =3D (val >> 8 * i) & 0xff; pmp_write_cfg(env, (reg_index * 4) + i, cfg_val); } @@ -490,8 +485,9 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32= _t reg_index) int i; target_ulong cfg_val =3D 0; target_ulong val =3D 0; + int pmpcfg_nums =3D 2 << riscv_cpu_mxl(env); =20 - for (i =3D 0; i < sizeof(target_ulong); i++) { + for (i =3D 0; i < pmpcfg_nums; i++) { val =3D pmp_read_cfg(env, (reg_index * 4) + i); cfg_val |=3D (val << (i * 8)); } --=20 2.25.1 From nobody Fri Apr 26 16:16:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637826783559481.83960761155276; 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MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=7; SR=0; TI=SMTPD_---.LyzsCDX_1637826061; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 02/22] target/riscv: Don't save pc when exception return Date: Thu, 25 Nov 2021 15:39:31 +0800 Message-Id: <20211125073951.57678-3-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.1; envelope-from=zhiwei_liu@c-sky.com; helo=out28-1.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637826785180100001 Content-Type: text/plain; charset="utf-8" As pc will be written by the xepc in exception return, just ignore pc in translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 4 ++-- target/riscv/insn_trans/trans_privileged.c.inc | 7 ++----- target/riscv/op_helper.c | 4 ++-- 3 files changed, 6 insertions(+), 9 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c7a5376227..c5098380dd 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -67,8 +67,8 @@ DEF_HELPER_2(csrr, tl, env, int) DEF_HELPER_3(csrw, void, env, int, tl) DEF_HELPER_4(csrrw, tl, env, int, tl, tl) #ifndef CONFIG_USER_ONLY -DEF_HELPER_2(sret, tl, env, tl) -DEF_HELPER_2(mret, tl, env, tl) +DEF_HELPER_1(sret, tl, env) +DEF_HELPER_1(mret, tl, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(tlb_flush, void, env) #endif diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index 75c6ef80a6..6077bbbf11 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -74,10 +74,8 @@ static bool trans_uret(DisasContext *ctx, arg_uret *a) static bool trans_sret(DisasContext *ctx, arg_sret *a) { #ifndef CONFIG_USER_ONLY - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - if (has_ext(ctx, RVS)) { - gen_helper_sret(cpu_pc, cpu_env, cpu_pc); + gen_helper_sret(cpu_pc, cpu_env); tcg_gen_exit_tb(NULL, 0); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; } else { @@ -92,8 +90,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - gen_helper_mret(cpu_pc, cpu_env, cpu_pc); + gen_helper_mret(cpu_pc, cpu_env); tcg_gen_exit_tb(NULL, 0); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; return true; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index ee7c24efe7..095d39671b 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -71,7 +71,7 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr, =20 #ifndef CONFIG_USER_ONLY =20 -target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) +target_ulong helper_sret(CPURISCVState *env) { uint64_t mstatus; target_ulong prev_priv, prev_virt; @@ -132,7 +132,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) return retpc; } =20 -target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) +target_ulong helper_mret(CPURISCVState *env) { if (!(env->priv >=3D PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); --=20 2.25.1 From nobody Fri Apr 26 16:16:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163782698076935.57600353184273; Wed, 24 Nov 2021 23:56:20 -0800 (PST) Received: from localhost ([::1]:40440 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9cB-0000kW-6o for importer@patchew.org; Thu, 25 Nov 2021 02:56:19 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59062) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9O2-0002KI-6l; Thu, 25 Nov 2021 02:41:42 -0500 Received: from out28-4.mail.aliyun.com ([115.124.28.4]:57365) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Nz-00018l-U0; Thu, 25 Nov 2021 02:41:41 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LyzYpCp_1637826093) by smtp.aliyun-inc.com(10.147.41.187); Thu, 25 Nov 2021 15:41:34 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.103833|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0320985-0.000647087-0.967254; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047207; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=7; SR=0; TI=SMTPD_---.LyzYpCp_1637826093; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 03/22] target/riscv: Sign extend pc for different XLEN Date: Thu, 25 Nov 2021 15:39:32 +0800 Message-Id: <20211125073951.57678-4-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.4; envelope-from=zhiwei_liu@c-sky.com; helo=out28-4.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637826982966100001 Content-Type: text/plain; charset="utf-8" When pc is written, it is sign-extended to fill the widest supported XLEN. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1d57bc97b5..a6a73ced9e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -150,16 +150,24 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64= in) tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); } =20 +static void gen_set_pc(DisasContext *ctx, target_ulong dest) +{ + if (get_xl(ctx) =3D=3D MXL_RV32) { + dest =3D (int32_t)dest; + } + tcg_gen_movi_tl(cpu_pc, dest); +} + static void generate_exception(DisasContext *ctx, int excp) { - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + gen_set_pc(ctx, ctx->base.pc_next); gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); ctx->base.is_jmp =3D DISAS_NORETURN; } =20 static void generate_exception_mtval(DisasContext *ctx, int excp) { - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + gen_set_pc(ctx, ctx->base.pc_next); tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); ctx->base.is_jmp =3D DISAS_NORETURN; @@ -179,10 +187,10 @@ static void gen_goto_tb(DisasContext *ctx, int n, tar= get_ulong dest) { if (translator_use_goto_tb(&ctx->base, dest)) { tcg_gen_goto_tb(n); - tcg_gen_movi_tl(cpu_pc, dest); + gen_set_pc(ctx, dest); tcg_gen_exit_tb(ctx->base.tb, n); } else { - tcg_gen_movi_tl(cpu_pc, dest); + gen_set_pc(ctx, dest); tcg_gen_lookup_and_goto_ptr(); } } --=20 2.25.1 From nobody Fri Apr 26 16:16:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163782747701124.00004216290108; Thu, 25 Nov 2021 00:04:37 -0800 (PST) Received: from localhost ([::1]:58076 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9k7-00054z-8h for importer@patchew.org; Thu, 25 Nov 2021 03:04:34 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59254) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9OY-0002eU-78; Thu, 25 Nov 2021 02:42:15 -0500 Received: from out28-169.mail.aliyun.com ([115.124.28.169]:49541) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9OV-0001Hj-CP; Thu, 25 Nov 2021 02:42:13 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lz-2.4X_1637826124) by smtp.aliyun-inc.com(10.147.44.118); Thu, 25 Nov 2021 15:42:05 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436731|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0150952-0.000473662-0.984431; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047199; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lz-2.4X_1637826124; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 04/22] target/riscv: Create xl field in env Date: Thu, 25 Nov 2021 15:39:33 +0800 Message-Id: <20211125073951.57678-5-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.169; envelope-from=zhiwei_liu@c-sky.com; helo=out28-169.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637827479039100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 3 +++ target/riscv/cpu_helper.c | 3 ++- target/riscv/csr.c | 2 ++ target/riscv/machine.c | 5 +++-- 5 files changed, 11 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f812998123..5c757ce33a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -377,6 +377,7 @@ static void riscv_cpu_reset(DeviceState *dev) /* mmte is supposed to have pm.current hardwired to 1 */ env->mmte |=3D (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); #endif + env->xl =3D riscv_cpu_mxl(env); cs->exception_index =3D RISCV_EXCP_NONE; env->load_res =3D -1; set_default_nan_mode(1, &env->fp_status); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0760c0af93..412339dbad 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -138,6 +138,7 @@ struct CPURISCVState { uint32_t misa_mxl_max; /* max mxl for this cpu */ uint32_t misa_ext; /* current extensions */ uint32_t misa_ext_mask; /* max ext for this cpu */ + uint32_t xl; /* current xlen */ =20 uint32_t features; =20 @@ -420,6 +421,8 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) } #endif =20 +RISCVMXL cpu_get_xl(CPURISCVState *env); + /* * A simplification for VLMAX * =3D (1 << LMUL) * VLEN / (8 * (1 << SEW)) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9eeed38c7e..b6cddf8648 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -35,7 +35,7 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } =20 -static RISCVMXL cpu_get_xl(CPURISCVState *env) +RISCVMXL cpu_get_xl(CPURISCVState *env) { #if defined(TARGET_RISCV32) return MXL_RV32; @@ -330,6 +330,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulon= g newpriv) } /* tlb_flush is unnecessary as mode is contained in mmu_idx */ env->priv =3D newpriv; + env->xl =3D cpu_get_xl(env); =20 /* * Clear the load reservation - otherwise a reservation placed in one diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ce20c3a970..d4ee897be2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -553,6 +553,7 @@ static RISCVException write_mstatus(CPURISCVState *env,= int csrno, mstatus =3D set_field(mstatus, MSTATUS64_UXL, MXL_RV64); } env->mstatus =3D mstatus; + env->xl =3D cpu_get_xl(env); =20 return RISCV_EXCP_NONE; } @@ -654,6 +655,7 @@ static RISCVException write_misa(CPURISCVState *env, in= t csrno, /* flush translation cache */ tb_flush(env_cpu(env)); env->misa_ext =3D val; + env->xl =3D riscv_cpu_mxl(env); return RISCV_EXCP_NONE; } =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ad8248ebfd..08ed603626 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -166,8 +166,8 @@ static const VMStateDescription vmstate_pointermasking = =3D { =20 const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", - .version_id =3D 3, - .minimum_version_id =3D 3, + .version_id =3D 4, + .minimum_version_id =3D 4, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), @@ -183,6 +183,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT32(env.misa_ext, RISCVCPU), VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), + VMSTATE_UINT32(env.xl, RISCVCPU), VMSTATE_UINT32(env.features, RISCVCPU), VMSTATE_UINTTL(env.priv, RISCVCPU), VMSTATE_UINTTL(env.virt, RISCVCPU), --=20 2.25.1 From nobody Fri Apr 26 16:16:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637827226593272.531690604608; Thu, 25 Nov 2021 00:00:26 -0800 (PST) Received: from localhost ([::1]:50412 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9g9-00082G-8m for importer@patchew.org; Thu, 25 Nov 2021 03:00:25 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59340) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9P6-0002lT-5O; Thu, 25 Nov 2021 02:42:48 -0500 Received: from out28-97.mail.aliyun.com ([115.124.28.97]:53383) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9P3-0001LD-MB; Thu, 25 Nov 2021 02:42:47 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lz-2.Pk_1637826156) by smtp.aliyun-inc.com(10.147.44.118); Thu, 25 Nov 2021 15:42:37 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1107497|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0260121-0.000895844-0.973092; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047199; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=7; SR=0; TI=SMTPD_---.Lz-2.Pk_1637826156; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 05/22] target/riscv: Ignore the pc bits above XLEN Date: Thu, 25 Nov 2021 15:39:34 +0800 Message-Id: <20211125073951.57678-6-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.97; envelope-from=zhiwei_liu@c-sky.com; helo=out28-97.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637827228330100001 Content-Type: text/plain; charset="utf-8" The read from PC for translation is in cpu_get_tb_cpu_state, before transla= tion. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b6cddf8648..9c3838bddf 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -71,7 +71,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, { uint32_t flags =3D 0; =20 - *pc =3D env->pc; + *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; *cs_base =3D 0; =20 if (riscv_has_ext(env, RVV)) { @@ -127,7 +127,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ul= ong *pc, } #endif =20 - flags =3D FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); =20 *pflags =3D flags; } --=20 2.25.1 From nobody Fri Apr 26 16:16:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637826663067281.9091205874622; Wed, 24 Nov 2021 23:51:03 -0800 (PST) Received: from localhost ([::1]:56482 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9X3-0000gB-Rm for importer@patchew.org; Thu, 25 Nov 2021 02:51:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59426) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Pa-00038o-Ns; Thu, 25 Nov 2021 02:43:18 -0500 Received: from out28-97.mail.aliyun.com ([115.124.28.97]:45933) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9PZ-0001ON-2n; Thu, 25 Nov 2021 02:43:18 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LyzDYQT_1637826188) by smtp.aliyun-inc.com(10.147.41.158); Thu, 25 Nov 2021 15:43:09 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07917368|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.385045-0.000545751-0.61441; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047194; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=7; SR=0; TI=SMTPD_---.LyzDYQT_1637826188; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 06/22] target/riscv: Extend pc for runtime pc write Date: Thu, 25 Nov 2021 15:39:35 +0800 Message-Id: <20211125073951.57678-7-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.97; envelope-from=zhiwei_liu@c-sky.com; helo=out28-97.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637826664930100001 Content-Type: text/plain; charset="utf-8" In some cases, we must restore the guest PC to the address of the start of the TB, such as when the instruction counter hits zero. So extend pc regist= er according to current xlen for these cases. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5c757ce33a..3e394d08e4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -319,7 +319,12 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - env->pc =3D value; + + if (env->xl =3D=3D MXL_RV32) { + env->pc =3D (int32_t)value; + } else { + env->pc =3D value; + } } =20 static void riscv_cpu_synchronize_from_tb(CPUState *cs, @@ -327,7 +332,13 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - env->pc =3D tb->pc; + RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); + + if (xl =3D=3D MXL_RV32) { + env->pc =3D (int32_t)tb->pc; + } else { + env->pc =3D tb->pc; + } } =20 static bool riscv_cpu_has_work(CPUState *cs) @@ -348,7 +359,12 @@ static bool riscv_cpu_has_work(CPUState *cs) void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, target_ulong *data) { - env->pc =3D data[0]; + RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); + if (xl =3D=3D MXL_RV32) { + env->pc =3D (int32_t)data[0]; + } else { + env->pc =3D data[0]; + } } =20 static void riscv_cpu_reset(DeviceState *dev) --=20 2.25.1 From nobody Fri Apr 26 16:16:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637826802201445.3353526537684; Wed, 24 Nov 2021 23:53:22 -0800 (PST) Received: from localhost ([::1]:34618 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9ZJ-00053b-5J for importer@patchew.org; Thu, 25 Nov 2021 02:53:21 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59552) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Q3-0003NU-Si; Thu, 25 Nov 2021 02:43:47 -0500 Received: from out28-123.mail.aliyun.com ([115.124.28.123]:53380) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Q1-0001qJ-IL; Thu, 25 Nov 2021 02:43:47 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LyytuoP_1637826219) by smtp.aliyun-inc.com(10.147.42.198); Thu, 25 Nov 2021 15:43:40 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436737|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0231685-0.000144035-0.976687; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047206; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=7; SR=0; TI=SMTPD_---.LyytuoP_1637826219; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 07/22] target/riscv: Use gdb xml according to max mxlen Date: Thu, 25 Nov 2021 15:39:36 +0800 Message-Id: <20211125073951.57678-8-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.123; envelope-from=zhiwei_liu@c-sky.com; helo=out28-123.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637826804004100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++ target/riscv/gdbstub.c | 71 +++++++++++++++++++++++++++++++----------- 2 files changed, 55 insertions(+), 19 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3e394d08e4..b6ca3fb883 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -421,6 +421,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) RISCVCPU *cpu =3D RISCV_CPU(dev); CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); + CPUClass *cc =3D CPU_CLASS(mcc); int priv_version =3D 0; Error *local_err =3D NULL; =20 @@ -471,9 +472,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) switch (env->misa_mxl_max) { #ifdef TARGET_RISCV64 case MXL_RV64: + cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; break; #endif case MXL_RV32: + cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; break; default: g_assert_not_reached(); diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 23429179e2..afc4c13171 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -24,11 +24,23 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArra= y *mem_buf, int n) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; + target_ulong tmp; =20 if (n < 32) { - return gdb_get_regl(mem_buf, env->gpr[n]); + tmp =3D env->gpr[n]; } else if (n =3D=3D 32) { - return gdb_get_regl(mem_buf, env->pc); + tmp =3D env->pc; + } else { + return 0; + } + + switch (env->misa_mxl_max) { + case MXL_RV32: + return gdb_get_reg32(mem_buf, tmp); + case MXL_RV64: + return gdb_get_reg64(mem_buf, tmp); + default: + g_assert_not_reached(); } return 0; } @@ -37,18 +49,32 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - - if (n =3D=3D 0) { - /* discard writes to x0 */ - return sizeof(target_ulong); - } else if (n < 32) { - env->gpr[n] =3D ldtul_p(mem_buf); - return sizeof(target_ulong); + int length =3D 0; + target_ulong tmp; + + switch (env->misa_mxl_max) { + case MXL_RV32: + tmp =3D (int32_t)ldl_p(mem_buf); + length =3D 4; + break; + case MXL_RV64: + if (env->xl < MXL_RV64) { + tmp =3D (int32_t)ldq_p(mem_buf); + } else { + tmp =3D ldq_p(mem_buf); + } + length =3D 8; + break; + default: + g_assert_not_reached(); + } + if (n > 0 && n < 32) { + env->gpr[n] =3D tmp; } else if (n =3D=3D 32) { - env->pc =3D ldtul_p(mem_buf); - return sizeof(target_ulong); + env->pc =3D tmp; } - return 0; + + return length; } =20 static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) @@ -198,13 +224,20 @@ void riscv_cpu_register_gdb_regs_for_features(CPUStat= e *cs) gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-32bit-fpu.xml", 0); } -#if defined(TARGET_RISCV32) - gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virt= ual, - 1, "riscv-32bit-virtual.xml", 0); -#elif defined(TARGET_RISCV64) - gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virt= ual, - 1, "riscv-64bit-virtual.xml", 0); -#endif + switch (env->misa_mxl_max) { + case MXL_RV32: + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, + riscv_gdb_set_virtual, + 1, "riscv-32bit-virtual.xml", 0); + break; + case MXL_RV64: + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, + riscv_gdb_set_virtual, + 1, "riscv-64bit-virtual.xml", 0); + break; + default: + g_assert_not_reached(); + } =20 gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_reg= s), --=20 2.25.1 From nobody Fri Apr 26 16:16:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637827526080288.05338955898344; Thu, 25 Nov 2021 00:05:26 -0800 (PST) Received: from localhost ([::1]:59736 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9ky-0006BV-Gc for importer@patchew.org; Thu, 25 Nov 2021 03:05:24 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59726) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Qg-0003iD-5V; Thu, 25 Nov 2021 02:44:30 -0500 Received: from out28-221.mail.aliyun.com ([115.124.28.221]:56231) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Qd-00023Z-5a; Thu, 25 Nov 2021 02:44:25 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LyzDZ7O_1637826251) by smtp.aliyun-inc.com(10.147.41.158); Thu, 25 Nov 2021 15:44:12 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.2472512|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0241832-0.00194606-0.973871; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047198; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=7; SR=0; TI=SMTPD_---.LyzDZ7O_1637826251; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 08/22] target/riscv: Relax debug check for pm write Date: Thu, 25 Nov 2021 15:39:37 +0800 Message-Id: <20211125073951.57678-9-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.221; envelope-from=zhiwei_liu@c-sky.com; helo=out28-221.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637827526527100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d4ee897be2..bfafd3bd96 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1465,6 +1465,9 @@ static bool check_pm_current_disabled(CPURISCVState *= env, int csrno) int csr_priv =3D get_field(csrno, 0x300); int pm_current; =20 + if (env->debugger) { + return false; + } /* * If priv lvls differ that means we're accessing csr from higher priv= lvl, * so allow the access --=20 2.25.1 From nobody Fri Apr 26 16:16:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637827245368668.7579236238026; Thu, 25 Nov 2021 00:00:45 -0800 (PST) Received: from localhost ([::1]:51832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9gS-0000dI-AE for importer@patchew.org; Thu, 25 Nov 2021 03:00:44 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9R6-0003zU-RK; Thu, 25 Nov 2021 02:44:52 -0500 Received: from out28-1.mail.aliyun.com ([115.124.28.1]:49295) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9R2-00027G-Bb; Thu, 25 Nov 2021 02:44:50 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lz-4IrF_1637826283) by smtp.aliyun-inc.com(10.147.42.241); Thu, 25 Nov 2021 15:44:43 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.09099696|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.00308482-0.000160068-0.996755; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047203; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=7; SR=0; TI=SMTPD_---.Lz-4IrF_1637826283; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 09/22] target/riscv: Adjust csr write mask with XLEN Date: Thu, 25 Nov 2021 15:39:38 +0800 Message-Id: <20211125073951.57678-10-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.1; envelope-from=zhiwei_liu@c-sky.com; helo=out28-1.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637827246337100001 Content-Type: text/plain; charset="utf-8" Write mask is representing the bits we care about. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/op_helper.c | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index e51dbc41c5..40c81421f2 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -486,7 +486,7 @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a) return do_csrw(ctx, a->csr, src); } =20 - TCGv mask =3D tcg_constant_tl(-1); + TCGv mask =3D tcg_constant_tl(get_xl(ctx) =3D=3D MXL_RV32 ? UINT32_MAX= : -1); return do_csrrw(ctx, a->rd, a->csr, src, mask); } =20 @@ -537,7 +537,7 @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi = *a) return do_csrw(ctx, a->csr, src); } =20 - TCGv mask =3D tcg_constant_tl(-1); + TCGv mask =3D tcg_constant_tl(get_xl(ctx) =3D=3D MXL_RV32 ? UINT32_MAX= : -1); return do_csrrw(ctx, a->rd, a->csr, src, mask); } =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 095d39671b..acfad598e1 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -50,7 +50,8 @@ target_ulong helper_csrr(CPURISCVState *env, int csr) =20 void helper_csrw(CPURISCVState *env, int csr, target_ulong src) { - RISCVException ret =3D riscv_csrrw(env, csr, NULL, src, -1); + target_ulong mask =3D env->xl =3D=3D MXL_RV32 ? UINT32_MAX : -1; + RISCVException ret =3D riscv_csrrw(env, csr, NULL, src, mask); =20 if (ret !=3D RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC()); --=20 2.25.1 From nobody Fri Apr 26 16:16:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637826993091709.3960008554934; Wed, 24 Nov 2021 23:56:33 -0800 (PST) Received: from localhost ([::1]:41420 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9cO-0001QH-3u for importer@patchew.org; Thu, 25 Nov 2021 02:56:32 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59984) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Ra-0004JO-OR; Thu, 25 Nov 2021 02:45:22 -0500 Received: from out28-5.mail.aliyun.com ([115.124.28.5]:33075) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9RX-0002DJ-Sw; Thu, 25 Nov 2021 02:45:22 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LyzDZqT_1637826314) by smtp.aliyun-inc.com(10.147.41.158); Thu, 25 Nov 2021 15:45:15 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.087123-0.00284615-0.910031; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047199; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=7; SR=0; TI=SMTPD_---.LyzDZqT_1637826314; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 10/22] target/riscv: Create current pm fields in env Date: Thu, 25 Nov 2021 15:39:39 +0800 Message-Id: <20211125073951.57678-11-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.5; envelope-from=zhiwei_liu@c-sky.com; helo=out28-5.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637826994784100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 4 ++++ target/riscv/cpu_helper.c | 43 +++++++++++++++++++++++++++++++++++++++ target/riscv/csr.c | 19 +++++++++++++++++ target/riscv/machine.c | 10 +++++++++ 5 files changed, 77 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b6ca3fb883..61ef88752c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -394,6 +394,7 @@ static void riscv_cpu_reset(DeviceState *dev) env->mmte |=3D (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); #endif env->xl =3D riscv_cpu_mxl(env); + riscv_cpu_update_mask(env); cs->exception_index =3D RISCV_EXCP_NONE; env->load_res =3D -1; set_default_nan_mode(1, &env->fp_status); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 412339dbad..28006b782f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -251,6 +251,8 @@ struct CPURISCVState { target_ulong upmmask; target_ulong upmbase; #endif + target_ulong cur_pmmask; + target_ulong cur_pmbase; =20 float_status fp_status; =20 @@ -442,6 +444,8 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, ta= rget_ulong vtype) void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags); =20 +void riscv_cpu_update_mask(CPURISCVState *env); + RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask= ); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9c3838bddf..d74199b49b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -132,6 +132,48 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_u= long *pc, *pflags =3D flags; } =20 +void riscv_cpu_update_mask(CPURISCVState *env) +{ + target_ulong mask =3D -1, base =3D 0; + /* + * TODO: Current RVJ spec does not specify + * how the extension interacts with XLEN. + */ +#ifndef CONFIG_USER_ONLY + if (riscv_has_ext(env, RVJ)) { + switch (env->priv) { + case PRV_M: + if (env->mmte & M_PM_ENABLE) { + mask =3D env->mpmmask; + base =3D env->mpmbase; + } + break; + case PRV_S: + if (env->mmte & S_PM_ENABLE) { + mask =3D env->spmmask; + base =3D env->spmbase; + } + break; + case PRV_U: + if (env->mmte & U_PM_ENABLE) { + mask =3D env->upmmask; + base =3D env->upmbase; + } + break; + default: + g_assert_not_reached(); + } + } +#endif + if (env->xl =3D=3D MXL_RV32) { + env->cur_pmmask =3D mask & UINT32_MAX; + env->cur_pmbase =3D base & UINT32_MAX; + } else { + env->cur_pmmask =3D mask; + env->cur_pmbase =3D base; + } +} + #ifndef CONFIG_USER_ONLY static int riscv_cpu_local_irq_pending(CPURISCVState *env) { @@ -331,6 +373,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulon= g newpriv) /* tlb_flush is unnecessary as mode is contained in mmu_idx */ env->priv =3D newpriv; env->xl =3D cpu_get_xl(env); + riscv_cpu_update_mask(env); =20 /* * Clear the load reservation - otherwise a reservation placed in one diff --git a/target/riscv/csr.c b/target/riscv/csr.c index bfafd3bd96..68da5d2173 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1516,6 +1516,7 @@ static RISCVException write_mmte(CPURISCVState *env, = int csrno, /* hardwiring pm.instruction bit to 0, since it's not supported yet */ wpri_val &=3D ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); env->mmte =3D wpri_val | PM_EXT_DIRTY; + riscv_cpu_update_mask(env); =20 /* Set XS and SD bits, since PM CSRs are dirty */ mstatus =3D env->mstatus | MSTATUS_XS; @@ -1591,6 +1592,9 @@ static RISCVException write_mpmmask(CPURISCVState *en= v, int csrno, uint64_t mstatus; =20 env->mpmmask =3D val; + if ((env->priv =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE)) { + env->cur_pmmask =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1616,6 +1620,9 @@ static RISCVException write_spmmask(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } env->spmmask =3D val; + if ((env->priv =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE)) { + env->cur_pmmask =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1641,6 +1648,9 @@ static RISCVException write_upmmask(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } env->upmmask =3D val; + if ((env->priv =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE)) { + env->cur_pmmask =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1662,6 +1672,9 @@ static RISCVException write_mpmbase(CPURISCVState *en= v, int csrno, uint64_t mstatus; =20 env->mpmbase =3D val; + if ((env->priv =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE)) { + env->cur_pmbase =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1687,6 +1700,9 @@ static RISCVException write_spmbase(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } env->spmbase =3D val; + if ((env->priv =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE)) { + env->cur_pmbase =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1712,6 +1728,9 @@ static RISCVException write_upmbase(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } env->upmbase =3D val; + if ((env->priv =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE)) { + env->cur_pmbase =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 08ed603626..10a0f34f37 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -164,10 +164,20 @@ static const VMStateDescription vmstate_pointermaskin= g =3D { } }; =20 +static int riscv_cpu_post_load(void *opaque, int version_id) +{ + RISCVCPU *cpu =3D opaque; + CPURISCVState *env =3D &cpu->env; + + riscv_cpu_update_mask(env); + return 0; +} + const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", .version_id =3D 4, .minimum_version_id =3D 4, + .post_load =3D riscv_cpu_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), --=20 2.25.1 From nobody Fri Apr 26 16:16:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637827841445823.4733044182447; Thu, 25 Nov 2021 00:10:41 -0800 (PST) Received: from localhost ([::1]:40494 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9q3-0003yq-SR for importer@patchew.org; Thu, 25 Nov 2021 03:10:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60034) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9S9-0004uk-0s; Thu, 25 Nov 2021 02:45:57 -0500 Received: from out28-195.mail.aliyun.com ([115.124.28.195]:41844) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9S5-0002LK-KS; Thu, 25 Nov 2021 02:45:56 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LyytwBx_1637826346) by smtp.aliyun-inc.com(10.147.42.198); Thu, 25 Nov 2021 15:45:47 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07449317|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0061735-0.00216247-0.991664; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047193; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=7; SR=0; TI=SMTPD_---.LyytwBx_1637826346; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 11/22] target/riscv: Alloc tcg global for cur_pm[mask|base] Date: Thu, 25 Nov 2021 15:39:40 +0800 Message-Id: <20211125073951.57678-12-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.195; envelope-from=zhiwei_liu@c-sky.com; helo=out28-195.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637827843219100001 Content-Type: text/plain; charset="utf-8" Replace the array of pm_mask/pm_base with scalar variables. Remove the cached array value in DisasContext. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 32 ++++++++------------------------ 1 file changed, 8 insertions(+), 24 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a6a73ced9e..6cb74c6355 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -37,8 +37,8 @@ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions= */ static TCGv load_res; static TCGv load_val; /* globals for PM CSRs */ -static TCGv pm_mask[4]; -static TCGv pm_base[4]; +static TCGv pm_mask; +static TCGv pm_base; =20 #include "exec/gen-icount.h" =20 @@ -88,8 +88,6 @@ typedef struct DisasContext { TCGv temp[4]; /* PointerMasking extension */ bool pm_enabled; - TCGv pm_mask; - TCGv pm_base; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -297,8 +295,8 @@ static TCGv gen_pm_adjust_address(DisasContext *s, TCGv= src) return src; } else { temp =3D temp_new(s); - tcg_gen_andc_tl(temp, src, s->pm_mask); - tcg_gen_or_tl(temp, temp, s->pm_base); + tcg_gen_andc_tl(temp, src, pm_mask); + tcg_gen_or_tl(temp, temp, pm_base); return temp; } } @@ -647,10 +645,6 @@ static void riscv_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->ntemp =3D 0; memset(ctx->temp, 0, sizeof(ctx->temp)); ctx->pm_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); - int priv =3D tb_flags & TB_FLAGS_PRIV_MMU_MASK; - ctx->pm_mask =3D pm_mask[priv]; - ctx->pm_base =3D pm_base[priv]; - ctx->zero =3D tcg_constant_tl(0); } =20 @@ -763,19 +757,9 @@ void riscv_translate_init(void) "load_res"); load_val =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_= val), "load_val"); -#ifndef CONFIG_USER_ONLY /* Assign PM CSRs to tcg globals */ - pm_mask[PRV_U] =3D - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmma= sk"); - pm_base[PRV_U] =3D - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmba= se"); - pm_mask[PRV_S] =3D - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmma= sk"); - pm_base[PRV_S] =3D - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmba= se"); - pm_mask[PRV_M] =3D - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmma= sk"); - pm_base[PRV_M] =3D - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmba= se"); -#endif + pm_mask =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pm= mask), + "pmmask"); + pm_base =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pm= base), + "pmbase"); } --=20 2.25.1 From nobody Fri Apr 26 16:16:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637827209516521.2333593908533; Thu, 25 Nov 2021 00:00:09 -0800 (PST) Received: from localhost ([::1]:49206 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9fs-0006zT-B2 for importer@patchew.org; Thu, 25 Nov 2021 03:00:08 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60146) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Sf-0005M8-7b; Thu, 25 Nov 2021 02:46:29 -0500 Received: from out28-76.mail.aliyun.com ([115.124.28.76]:43193) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Sa-00030e-PM; Thu, 25 Nov 2021 02:46:28 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lyzz6.6_1637826377) by smtp.aliyun-inc.com(10.147.41.120); Thu, 25 Nov 2021 15:46:18 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0116271-0.000182734-0.98819; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047211; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=7; SR=0; TI=SMTPD_---.Lyzz6.6_1637826377; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 12/22] target/riscv: Calculate address according to XLEN Date: Thu, 25 Nov 2021 15:39:41 +0800 Message-Id: <20211125073951.57678-13-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.76; envelope-from=zhiwei_liu@c-sky.com; helo=out28-76.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637827211527100001 Content-Type: text/plain; charset="utf-8" Define one common function to compute a canonical address from a register plus offset. Merge gen_pm_adjust_address into this function. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 9 +++------ target/riscv/insn_trans/trans_rvd.c.inc | 19 ++--------------- target/riscv/insn_trans/trans_rvf.c.inc | 19 ++--------------- target/riscv/insn_trans/trans_rvi.c.inc | 18 ++--------------- target/riscv/translate.c | 27 ++++++++++++------------- 5 files changed, 22 insertions(+), 70 deletions(-) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index 40fe132b04..1f64b8d332 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -20,12 +20,11 @@ =20 static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) { - TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); + TCGv src1 =3D get_address(ctx, a->rs1, 0); =20 if (a->rl) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - src1 =3D gen_pm_adjust_address(ctx, src1); tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop); if (a->aq) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -44,8 +43,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemO= p mop) TCGLabel *l1 =3D gen_new_label(); TCGLabel *l2 =3D gen_new_label(); =20 - src1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); - src1 =3D gen_pm_adjust_address(ctx, src1); + src1 =3D get_address(ctx, a->rs1, 0); tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); =20 /* @@ -83,10 +81,9 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, MemOp mop) { TCGv dest =3D dest_gpr(ctx, a->rd); - TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src1 =3D get_address(ctx, a->rs1, 0); TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 - src1 =3D gen_pm_adjust_address(ctx, src1); func(dest, src1, src2, ctx->mem_idx, mop); =20 gen_set_gpr(ctx, a->rd, dest); diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 64fb0046f7..88a491375c 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -25,14 +25,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - + addr =3D get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEQ); =20 mark_fs_dirty(ctx); @@ -46,16 +39,8 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - + addr =3D get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEQ); - return true; } =20 diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index b5459249c4..0aac87f7db 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -31,14 +31,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - + addr =3D get_address(ctx, a->rs1, a->imm); dest =3D cpu_fpr[a->rd]; tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL); gen_nanbox_s(dest, dest); @@ -54,16 +47,8 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - if (a->imm) { - TCGv temp =3D tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - + addr =3D get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL); - return true; } =20 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 40c81421f2..cb73a2f1ee 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -137,14 +137,7 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) { TCGv dest =3D dest_gpr(ctx, a->rd); - TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); + TCGv addr =3D get_address(ctx, a->rs1, a->imm); =20 tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop); gen_set_gpr(ctx, a->rd, dest); @@ -178,16 +171,9 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a) =20 static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) { - TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv addr =3D get_address(ctx, a->rs1, a->imm); TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); return true; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6cb74c6355..fd75f7c4bc 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -284,21 +284,20 @@ static void gen_jal(DisasContext *ctx, int rd, target= _ulong imm) ctx->base.is_jmp =3D DISAS_NORETURN; } =20 -/* - * Generates address adjustment for PointerMasking - */ -static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src) -{ - TCGv temp; - if (!s->pm_enabled) { - /* Load unmodified address */ - return src; - } else { - temp =3D temp_new(s); - tcg_gen_andc_tl(temp, src, pm_mask); - tcg_gen_or_tl(temp, temp, pm_base); - return temp; +/* Compute a canonical address from a register plus offset. */ +static TCGv get_address(DisasContext *ctx, int rs1, int imm) +{ + TCGv addr =3D temp_new(ctx); + TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); + + tcg_gen_addi_tl(addr, src1, imm); + if (ctx->pm_enabled) { + tcg_gen_and_tl(addr, addr, pm_mask); + tcg_gen_or_tl(addr, addr, pm_base); + } else if (get_xl(ctx) =3D=3D MXL_RV32) { + tcg_gen_ext32u_tl(addr, addr); } + return addr; } =20 #ifndef CONFIG_USER_ONLY --=20 2.25.1 From nobody Fri Apr 26 16:16:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637828013918456.22124633716373; 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MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=7; SR=0; TI=SMTPD_---.Lyzlo32_1637826409; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 13/22] target/riscv: Split pm_enabled into mask and base Date: Thu, 25 Nov 2021 15:39:42 +0800 Message-Id: <20211125073951.57678-14-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.171; envelope-from=zhiwei_liu@c-sky.com; helo=out28-171.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637828014518100001 Content-Type: text/plain; charset="utf-8" Use cached cur_pmmask and cur_pmbase to infer the current PM mode. This may decrease the TCG IR by one when pm_enabled is true and pm_base_enabled is false. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 3 ++- target/riscv/cpu_helper.c | 24 ++++++------------------ target/riscv/translate.c | 12 ++++++++---- 3 files changed, 16 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 28006b782f..3986a2164d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -412,7 +412,8 @@ FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ FIELD(TB_FLAGS, XL, 13, 2) /* If PointerMasking should be applied */ -FIELD(TB_FLAGS, PM_ENABLED, 15, 1) +FIELD(TB_FLAGS, PM_MASK_ENABLED, 15, 1) +FIELD(TB_FLAGS, PM_BASE_ENABLED, 16, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d74199b49b..91b84be48f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -107,27 +107,15 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_= ulong *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, get_field(env->mstatus_hs, MSTATUS_FS)); } - if (riscv_has_ext(env, RVJ)) { - int priv =3D flags & TB_FLAGS_PRIV_MMU_MASK; - bool pm_enabled =3D false; - switch (priv) { - case PRV_U: - pm_enabled =3D env->mmte & U_PM_ENABLE; - break; - case PRV_S: - pm_enabled =3D env->mmte & S_PM_ENABLE; - break; - case PRV_M: - pm_enabled =3D env->mmte & M_PM_ENABLE; - break; - default: - g_assert_not_reached(); - } - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled); - } #endif =20 flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); + if (env->cur_pmmask < (env->xl =3D=3D MXL_RV32 ? UINT32_MAX : UINT64_M= AX)) { + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); + } + if (env->cur_pmbase !=3D 0) { + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); + } =20 *pflags =3D flags; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index fd75f7c4bc..10c16e759d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -87,7 +87,8 @@ typedef struct DisasContext { /* Space for 3 operands plus 1 extra for address computation. */ TCGv temp[4]; /* PointerMasking extension */ - bool pm_enabled; + bool pm_mask_enabled; + bool pm_base_enabled; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -291,12 +292,14 @@ static TCGv get_address(DisasContext *ctx, int rs1, i= nt imm) TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_addi_tl(addr, src1, imm); - if (ctx->pm_enabled) { + if (ctx->pm_mask_enabled) { tcg_gen_and_tl(addr, addr, pm_mask); - tcg_gen_or_tl(addr, addr, pm_base); } else if (get_xl(ctx) =3D=3D MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } + if (ctx->pm_base_enabled) { + tcg_gen_or_tl(addr, addr, pm_base); + } return addr; } =20 @@ -643,7 +646,8 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->cs =3D cs; ctx->ntemp =3D 0; memset(ctx->temp, 0, sizeof(ctx->temp)); - ctx->pm_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); + ctx->pm_mask_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLE= D); + ctx->pm_base_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLE= D); ctx->zero =3D tcg_constant_tl(0); } =20 --=20 2.25.1 From nobody Fri Apr 26 16:16:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637828018474765.3447996613961; Thu, 25 Nov 2021 00:13:38 -0800 (PST) Received: from localhost ([::1]:49168 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9su-0001ZN-UX for importer@patchew.org; Thu, 25 Nov 2021 03:13:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60336) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Tj-0006CR-VS; Thu, 25 Nov 2021 02:47:36 -0500 Received: from out28-73.mail.aliyun.com ([115.124.28.73]:38938) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Th-0004pL-MW; Thu, 25 Nov 2021 02:47:35 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LyzsecB_1637826441) by smtp.aliyun-inc.com(10.147.41.138); Thu, 25 Nov 2021 15:47:27 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436477|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0599752-0.000428917-0.939596; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047193; MF=zhiwei_liu@c-sky.com; NM=1; PH=DU; RN=8; RT=7; SR=0; TI=SMTPD_---.LyzsecB_1637826441; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 14/22] target/riscv: Split out the vill from vtype Date: Thu, 25 Nov 2021 15:39:43 +0800 Message-Id: <20211125073951.57678-15-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.73; envelope-from=zhiwei_liu@c-sky.com; helo=out28-73.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637828019427100001 Content-Type: text/plain; charset="utf-8" We need not specially process vtype when XLEN changes. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 3 +-- target/riscv/csr.c | 13 ++++++++++++- target/riscv/machine.c | 5 +++-- target/riscv/vector_helper.c | 3 ++- 5 files changed, 19 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3986a2164d..1e56405243 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -119,6 +119,7 @@ struct CPURISCVState { target_ulong vl; target_ulong vstart; target_ulong vtype; + bool vill; =20 target_ulong pc; target_ulong load_res; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 91b84be48f..7945f687b4 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -77,8 +77,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, if (riscv_has_ext(env, RVV)) { uint32_t vlmax =3D vext_get_vlmax(env_archcpu(env), env->vtype); bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl); - flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, - FIELD_EX64(env->vtype, VTYPE, VILL)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, FIELD_EX64(env->vtype, VTYPE, VSEW)); flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 68da5d2173..3f284090fc 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -286,7 +286,18 @@ static RISCVException write_fcsr(CPURISCVState *env, i= nt csrno, static RISCVException read_vtype(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->vtype; + uint64_t vill; + switch (env->xl) { + case MXL_RV32: + vill =3D (uint32_t)env->vill << 31; + break; + case MXL_RV64: + vill =3D (uint64_t)env->vill << 63; + break; + default: + g_assert_not_reached(); + } + *val =3D (target_ulong)vill | env->vtype; return RISCV_EXCP_NONE; } =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 10a0f34f37..cf71a5ad33 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -124,8 +124,8 @@ static bool vector_needed(void *opaque) =20 static const VMStateDescription vmstate_vector =3D { .name =3D "cpu/vector", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .needed =3D vector_needed, .fields =3D (VMStateField[]) { VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64= ), @@ -134,6 +134,7 @@ static const VMStateDescription vmstate_vector =3D { VMSTATE_UINTTL(env.vl, RISCVCPU), VMSTATE_UINTTL(env.vstart, RISCVCPU), VMSTATE_UINTTL(env.vtype, RISCVCPU), + VMSTATE_BOOL(env.vill, RISCVCPU), VMSTATE_END_OF_LIST() } }; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 12c31aa4b4..b02ccefa4d 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -38,7 +38,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ul= ong s1, =20 if ((sew > cpu->cfg.elen) || vill || (ediv !=3D 0) || (reserved !=3D 0= )) { /* only set vill bit. */ - env->vtype =3D FIELD_DP64(0, VTYPE, VILL, 1); + env->vill =3D 1; + env->vtype =3D 0; env->vl =3D 0; env->vstart =3D 0; return 0; --=20 2.25.1 From nobody Fri Apr 26 16:16:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637828219654714.5084975557866; Thu, 25 Nov 2021 00:16:59 -0800 (PST) Received: from localhost ([::1]:56516 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9w9-0006YW-Jq for importer@patchew.org; Thu, 25 Nov 2021 03:16:57 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60440) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9UR-0006kj-Pf; Thu, 25 Nov 2021 02:48:21 -0500 Received: from out28-122.mail.aliyun.com ([115.124.28.122]:53848) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9UC-0005c6-RN; Thu, 25 Nov 2021 02:48:17 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lyyv4YS_1637826479) by smtp.aliyun-inc.com(10.147.41.178); Thu, 25 Nov 2021 15:48:00 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.09694179|-1; CH=green; DM=|CONTINUE|false|; DS=||; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047203; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=7; SR=0; TI=SMTPD_---.Lyyv4YS_1637826479; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 15/22] target/riscv: Fix RESERVED field length in VTYPE Date: Thu, 25 Nov 2021 15:39:44 +0800 Message-Id: <20211125073951.57678-16-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.122; envelope-from=zhiwei_liu@c-sky.com; helo=out28-122.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637828221716100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1e56405243..2cee98f152 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -105,7 +105,7 @@ typedef struct CPURISCVState CPURISCVState; FIELD(VTYPE, VLMUL, 0, 2) FIELD(VTYPE, VSEW, 2, 3) FIELD(VTYPE, VEDIV, 5, 2) -FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) +FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8) FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) =20 struct CPURISCVState { --=20 2.25.1 From nobody Fri Apr 26 16:16:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637828221931261.71337587710036; Thu, 25 Nov 2021 00:17:01 -0800 (PST) Received: from localhost ([::1]:56540 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9wB-0006Zd-E7 for importer@patchew.org; Thu, 25 Nov 2021 03:16:59 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60498) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Ul-0007Xc-G1; Thu, 25 Nov 2021 02:48:39 -0500 Received: from out28-100.mail.aliyun.com ([115.124.28.100]:36500) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Ui-0005fM-Tq; Thu, 25 Nov 2021 02:48:39 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LyzHnPN_1637826510) by smtp.aliyun-inc.com(10.147.41.143); Thu, 25 Nov 2021 15:48:31 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.08302086|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0349596-0.00207493-0.962965; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047213; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=7; SR=0; TI=SMTPD_---.LyzHnPN_1637826510; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 16/22] target/riscv: Adjust vsetvl according to XLEN Date: Thu, 25 Nov 2021 15:39:45 +0800 Message-Id: <20211125073951.57678-17-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.100; envelope-from=zhiwei_liu@c-sky.com; helo=out28-100.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637828223628100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 5 +++++ target/riscv/vector_helper.c | 7 +++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2cee98f152..ef1d87af38 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -427,6 +427,11 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *en= v) =20 RISCVMXL cpu_get_xl(CPURISCVState *env); =20 +static inline int riscv_cpu_xlen(CPURISCVState *env) +{ + return 16 << env->xl; +} + /* * A simplification for VLMAX * =3D (1 << LMUL) * VLEN / (8 * (1 << SEW)) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index b02ccefa4d..e9d49cf105 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -33,8 +33,11 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_u= long s1, RISCVCPU *cpu =3D env_archcpu(env); uint16_t sew =3D 8 << FIELD_EX64(s2, VTYPE, VSEW); uint8_t ediv =3D FIELD_EX64(s2, VTYPE, VEDIV); - bool vill =3D FIELD_EX64(s2, VTYPE, VILL); - target_ulong reserved =3D FIELD_EX64(s2, VTYPE, RESERVED); + int xlen =3D riscv_cpu_xlen(env); + bool vill =3D (s2 >> (xlen - 1)) & 0x1; + target_ulong reserved =3D s2 & + MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, + xlen - 1 - R_VTYPE_RESERVED_SH= IFT); =20 if ((sew > cpu->cfg.elen) || vill || (ediv !=3D 0) || (reserved !=3D 0= )) { /* only set vill bit. */ --=20 2.25.1 From nobody Fri Apr 26 16:16:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637827633919686.7812398900028; Thu, 25 Nov 2021 00:07:13 -0800 (PST) Received: from localhost ([::1]:34450 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9mi-0008ER-RT for importer@patchew.org; Thu, 25 Nov 2021 03:07:12 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60624) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9VH-0000IM-Am; Thu, 25 Nov 2021 02:49:12 -0500 Received: from out28-98.mail.aliyun.com ([115.124.28.98]:48632) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9VD-0005iO-VY; Thu, 25 Nov 2021 02:49:10 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lz-1h4A_1637826542) by smtp.aliyun-inc.com(10.147.44.129); Thu, 25 Nov 2021 15:49:03 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1607588|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0730665-0.000540345-0.926393; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047187; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=7; SR=0; TI=SMTPD_---.Lz-1h4A_1637826542; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 17/22] target/riscv: Remove VILL field in VTYPE Date: Thu, 25 Nov 2021 15:39:46 +0800 Message-Id: <20211125073951.57678-18-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.98; envelope-from=zhiwei_liu@c-sky.com; helo=out28-98.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637827635121100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Acked-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ef1d87af38..347428ffdc 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -106,7 +106,6 @@ FIELD(VTYPE, VLMUL, 0, 2) FIELD(VTYPE, VSEW, 2, 3) FIELD(VTYPE, VEDIV, 5, 2) FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8) -FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) =20 struct CPURISCVState { target_ulong gpr[32]; --=20 2.25.1 From nobody Fri Apr 26 16:16:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637827575704292.14341534511505; Thu, 25 Nov 2021 00:06:15 -0800 (PST) Received: from localhost ([::1]:32808 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9lm-00073Y-NB for importer@patchew.org; Thu, 25 Nov 2021 03:06:14 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60770) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Vq-0000bG-KJ; Thu, 25 Nov 2021 02:49:48 -0500 Received: from out28-97.mail.aliyun.com ([115.124.28.97]:39281) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Vo-0005mP-AK; Thu, 25 Nov 2021 02:49:46 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LyzElOy_1637826573) by smtp.aliyun-inc.com(10.147.40.44); Thu, 25 Nov 2021 15:49:37 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.2155209|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0184311-7.11308e-05-0.981498; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047213; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=7; SR=0; TI=SMTPD_---.LyzElOy_1637826573; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 18/22] target/riscv: Ajdust vector atomic check with XLEN Date: Thu, 25 Nov 2021 15:39:47 +0800 Message-Id: <20211125073951.57678-19-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.97; envelope-from=zhiwei_liu@c-sky.com; helo=out28-97.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637827576543100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 17ee3babef..aacb97d280 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -739,7 +739,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a) (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) && vext_check_reg(s, a->rd, false) && vext_check_reg(s, a->rs2, false) && - ((1 << s->sew) <=3D sizeof(target_ulong)) && + /* TODO: RV128 could allow 128-bit atomics */ + ((1 << s->sew) <=3D (get_xl(s) =3D=3D MXL_RV32 ? 4 : 8)) && ((1 << s->sew) >=3D 4)); } =20 --=20 2.25.1 From nobody Fri Apr 26 16:16:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637828403765105.3086312103145; Thu, 25 Nov 2021 00:20:03 -0800 (PST) Received: from localhost ([::1]:36212 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9z8-0003hA-MG for importer@patchew.org; Thu, 25 Nov 2021 03:20:02 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60884) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9WL-0000wE-AD; Thu, 25 Nov 2021 02:50:17 -0500 Received: from out28-170.mail.aliyun.com ([115.124.28.170]:37883) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9WJ-0005r0-In; Thu, 25 Nov 2021 02:50:17 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LyzaPxs_1637826608) by smtp.aliyun-inc.com(10.147.42.16); Thu, 25 Nov 2021 15:50:10 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1589927|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0508009-0.000453744-0.948745; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047194; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=7; SR=0; TI=SMTPD_---.LyzaPxs_1637826608; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 19/22] target/riscv: Fix check range for first fault only Date: Thu, 25 Nov 2021 15:39:48 +0800 Message-Id: <20211125073951.57678-20-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.170; envelope-from=zhiwei_liu@c-sky.com; helo=out28-170.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637828405624100001 Content-Type: text/plain; charset="utf-8" Only check the range that has passed the address translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index e9d49cf105..e3ac70da01 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -631,12 +631,12 @@ vext_ldff(void *vd, void *v0, target_ulong base, cpu_mmu_index(env, false)); if (host) { #ifdef CONFIG_USER_ONLY - if (page_check_range(addr, nf * msz, PAGE_READ) < 0) { + if (page_check_range(addr, offset, PAGE_READ) < 0) { vl =3D i; goto ProbeSuccess; } #else - probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD); + probe_pages(env, addr, offset, ra, MMU_DATA_LOAD); #endif } else { vl =3D i; --=20 2.25.1 From nobody Fri Apr 26 16:16:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637827915348175.10200939209176; Thu, 25 Nov 2021 00:11:55 -0800 (PST) Received: from localhost ([::1]:43394 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9rG-00061q-8C for importer@patchew.org; Thu, 25 Nov 2021 03:11:54 -0500 Received: from eggs.gnu.org ([209.51.188.92]:32830) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9XD-0001vM-D8; Thu, 25 Nov 2021 02:51:11 -0500 Received: from out28-169.mail.aliyun.com ([115.124.28.169]:50552) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Wx-0005zn-2C; Thu, 25 Nov 2021 02:51:11 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lz-2Sqw_1637826641) by smtp.aliyun-inc.com(10.147.40.233); Thu, 25 Nov 2021 15:50:42 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07444089|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.00425706-0.00051316-0.99523; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047209; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=7; SR=0; TI=SMTPD_---.Lz-2Sqw_1637826641; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 20/22] target/riscv: Adjust vector address with mask Date: Thu, 25 Nov 2021 15:39:49 +0800 Message-Id: <20211125073951.57678-21-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.169; envelope-from=zhiwei_liu@c-sky.com; helo=out28-169.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637827916158100001 Content-Type: text/plain; charset="utf-8" The mask comes from the pointer masking extension, or the max value corresponding to XLEN bits. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index e3ac70da01..c3976cc3d4 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -116,6 +116,11 @@ static inline uint32_t vext_maxsz(uint32_t desc) return simd_maxsz(desc) << vext_lmul(desc); } =20 +static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong ad= dr) +{ + return (addr & env->cur_pmmask) | env->cur_pmbase; +} + /* * This function checks watchpoint before real load operation. * @@ -133,12 +138,12 @@ static void probe_pages(CPURISCVState *env, target_ul= ong addr, target_ulong pagelen =3D -(addr | TARGET_PAGE_MASK); target_ulong curlen =3D MIN(pagelen, len); =20 - probe_access(env, addr, curlen, access_type, + probe_access(env, adjust_addr(env, addr), curlen, access_type, cpu_mmu_index(env, false), ra); if (len > curlen) { addr +=3D curlen; curlen =3D len - curlen; - probe_access(env, addr, curlen, access_type, + probe_access(env, adjust_addr(env, addr), curlen, access_type, cpu_mmu_index(env, false), ra); } } @@ -299,7 +304,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, } while (k < nf) { target_ulong addr =3D base + stride * i + k * msz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra); k++; } } @@ -392,7 +397,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState= *env, uint32_t desc, k =3D 0; while (k < nf) { target_ulong addr =3D base + (i * nf + k) * msz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra); k++; } } @@ -529,7 +534,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, } while (k < nf) { abi_ptr addr =3D get_index_addr(base, i, vs2) + k * msz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra); k++; } } @@ -619,7 +624,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, if (!vm && !vext_elem_mask(v0, mlen, i)) { continue; } - addr =3D base + nf * i * msz; + addr =3D adjust_addr(env, base + nf * i * msz); if (i =3D=3D 0) { probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD); } else { @@ -646,7 +651,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, break; } remain -=3D offset; - addr +=3D offset; + addr =3D adjust_addr(env, addr + offset); } } } @@ -662,7 +667,7 @@ ProbeSuccess: } while (k < nf) { target_ulong addr =3D base + (i * nf + k) * msz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra); k++; } } @@ -801,7 +806,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong bas= e, continue; } addr =3D get_index_addr(base, i, vs2); - noatomic_op(vs3, addr, wd, i, env, ra); + noatomic_op(vs3, adjust_addr(env, addr), wd, i, env, ra); } clear_elem(vs3, env->vl, env->vl * esz, vlmax * esz); } --=20 2.25.1 From nobody Fri Apr 26 16:16:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637828437920698.6223017801224; Thu, 25 Nov 2021 00:20:37 -0800 (PST) Received: from localhost ([::1]:37464 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9zg-0004Xk-RJ for importer@patchew.org; Thu, 25 Nov 2021 03:20:36 -0500 Received: from eggs.gnu.org ([209.51.188.92]:32862) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Xb-0003Je-UE; Thu, 25 Nov 2021 02:51:36 -0500 Received: from out28-172.mail.aliyun.com ([115.124.28.172]:46201) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9XU-00063x-QO; Thu, 25 Nov 2021 02:51:35 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LyzuCJ9_1637826673) by smtp.aliyun-inc.com(10.147.42.135); Thu, 25 Nov 2021 15:51:13 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07609297|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.411451-0.000991827-0.587557; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047202; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.LyzuCJ9_1637826673; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 21/22] target/riscv: Adjust scalar reg in vector with XLEN Date: Thu, 25 Nov 2021 15:39:50 +0800 Message-Id: <20211125073951.57678-22-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.172; envelope-from=zhiwei_liu@c-sky.com; helo=out28-172.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637828438530100001 Content-Type: text/plain; charset="utf-8" When sew <=3D 32bits, not need to extend scalar reg. When sew > 32bits, if xlen is less that sew, we should sign extend the scalar register, except explicitly specified by the spec. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvv.c.inc | 44 ++++++++++++++++++------- 1 file changed, 32 insertions(+), 12 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index aacb97d280..411b5414b2 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -833,7 +833,7 @@ typedef void gen_helper_opivx(TCGv_ptr, TCGv_ptr, TCGv,= TCGv_ptr, TCGv_env, TCGv_i32); =20 static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t = vm, - gen_helper_opivx *fn, DisasContext *s) + gen_helper_opivx *fn, DisasContext *s, DisasExtend= ext) { TCGv_ptr dest, src2, mask; TCGv src1; @@ -846,7 +846,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint= 32_t vs2, uint32_t vm, dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); - src1 =3D get_gpr(s, rs1, EXT_NONE); + src1 =3D get_gpr(s, rs1, ext); =20 data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, vm); @@ -895,7 +895,7 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn= *gvec_fn, tcg_temp_free_i64(src1); return true; } - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, EXT_SIGN); } =20 /* OPIVX with GVEC IR */ @@ -1128,7 +1128,7 @@ static bool do_opivx_widen(DisasContext *s, arg_rmrr = *a, gen_helper_opivx *fn) { if (opivx_widen_check(s, a)) { - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, EXT_SIGN); } return false; } @@ -1213,7 +1213,7 @@ static bool do_opiwx_widen(DisasContext *s, arg_rmrr = *a, gen_helper_opivx *fn) { if (opiwx_widen_check(s, a)) { - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, EXT_SIGN); } return false; } @@ -1312,7 +1312,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ }; \ \ - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\ + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \ + fns[s->sew], s, EXT_SIGN); \ } \ return false; \ } @@ -1386,7 +1387,7 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVe= cGen2sFn32 *gvec_fn, tcg_temp_free_i32(src1); return true; } - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, EXT_SIGN); } =20 #define GEN_OPIVX_GVEC_SHIFT_TRANS(NAME, SUF) \ @@ -1472,7 +1473,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_h, \ gen_helper_##NAME##_w, \ }; \ - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\ + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \ + fns[s->sew], s, EXT_SIGN); \ } \ return false; \ } @@ -2670,6 +2672,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_= x *a) /* This instruction ignores LMUL and vector register groups */ int maxsz =3D s->vlen >> 3; TCGv_i64 t1; + TCGv src1 =3D get_gpr(s, a->rs1, EXT_ZERO); TCGLabel *over =3D gen_new_label(); =20 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); @@ -2679,7 +2682,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_= x *a) } =20 t1 =3D tcg_temp_new_i64(); - tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]); + tcg_gen_extu_tl_i64(t1, src1); vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); done: @@ -2748,12 +2751,28 @@ static bool slideup_check(DisasContext *s, arg_rmrr= *a) (a->rd !=3D a->rs2)); } =20 +/* OPIVXU without GVEC IR */ +#define GEN_OPIVXU_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + static gen_helper_opivx * const fns[4] =3D { = \ + gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ + }; \ + \ + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \ + fns[s->sew], s, EXT_ZERO); \ + } \ + return false; \ +} + GEN_OPIVX_TRANS(vslideup_vx, slideup_check) -GEN_OPIVX_TRANS(vslide1up_vx, slideup_check) +GEN_OPIVXU_TRANS(vslide1up_vx, slideup_check) GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check) =20 GEN_OPIVX_TRANS(vslidedown_vx, opivx_check) -GEN_OPIVX_TRANS(vslide1down_vx, opivx_check) +GEN_OPIVXU_TRANS(vslide1down_vx, opivx_check) GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check) =20 /* Vector Register Gather Instruction */ @@ -2803,7 +2822,8 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rm= rr *a) gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h, gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d }; - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s); + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, + fns[s->sew], s, EXT_SIGN); } return true; } --=20 2.25.1 From nobody Fri Apr 26 16:16:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637828080292593.7963761561655; Thu, 25 Nov 2021 00:14:40 -0800 (PST) Received: from localhost ([::1]:51320 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mq9tv-00030s-Aq for importer@patchew.org; Thu, 25 Nov 2021 03:14:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:32940) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Xz-0004FQ-Ve; Thu, 25 Nov 2021 02:52:02 -0500 Received: from out28-99.mail.aliyun.com ([115.124.28.99]:46803) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mq9Xt-0006Bi-H3; Thu, 25 Nov 2021 02:51:59 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lz-CM2L_1637826704) by smtp.aliyun-inc.com(10.147.41.137); Thu, 25 Nov 2021 15:51:45 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1217717|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0284492-2.96291e-05-0.971521; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047206; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=7; SR=0; TI=SMTPD_---.Lz-CM2L_1637826704; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 22/22] target/riscv: Enable uxl field write Date: Thu, 25 Nov 2021 15:39:51 +0800 Message-Id: <20211125073951.57678-23-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com> References: <20211125073951.57678-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.99; envelope-from=zhiwei_liu@c-sky.com; helo=out28-99.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637828082631100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 2 ++ target/riscv/csr.c | 8 +++++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 9913fa9f77..5106f0e769 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -413,6 +413,8 @@ typedef enum { #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ #define SSTATUS_MXR 0x00080000 =20 +#define SSTATUS64_UXL 0x0000000300000000ULL + #define SSTATUS32_SD 0x80000000 #define SSTATUS64_SD 0x8000000000000000ULL =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 3f284090fc..735d9a7825 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -553,15 +553,14 @@ static RISCVException write_mstatus(CPURISCVState *en= v, int csrno, * RV32: MPV and GVA are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. */ - mask |=3D MSTATUS_MPV | MSTATUS_GVA; + mask |=3D MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL; } =20 mstatus =3D (mstatus & ~mask) | (val & mask); =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { - /* SXL and UXL fields are for now read only */ + /* SXL fields are for now read only */ mstatus =3D set_field(mstatus, MSTATUS64_SXL, MXL_RV64); - mstatus =3D set_field(mstatus, MSTATUS64_UXL, MXL_RV64); } env->mstatus =3D mstatus; env->xl =3D cpu_get_xl(env); @@ -842,6 +841,9 @@ static RISCVException write_sstatus(CPURISCVState *env,= int csrno, target_ulong val) { target_ulong mask =3D (sstatus_v1_10_mask); + if (env->xl !=3D MXL_RV32) { + mask |=3D SSTATUS64_UXL; + } target_ulong newval =3D (env->mstatus & ~mask) | (val & mask); return write_mstatus(env, CSR_MSTATUS, newval); } --=20 2.25.1