From nobody Fri Apr 19 16:53:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail(p=none dis=none) header.from=xilinx.com ARC-Seal: i=2; a=rsa-sha256; t=1637665097; cv=pass; d=zohomail.com; s=zohoarc; b=NfvtXGUcZ03rQfvk+QGgeRRnVvu4NRCG5dLdbYd1ojFHcD8UvRdalIOLiE4v13A6caiaSsjqz1GOfbWziwy9kmoyhHeNjDqB3b56nXd6GmhC5+fIHV9wfRWIjTEjUkXHm9BzbLgj5wGSwUWVkSS48j/pvLr6pEbT7MIDPUJUaOk= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637665097; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bHo1qfGWn/w/LlJlLvjC07l6l+caTraPyEZ7WMzvu2M=; b=DNdiUuRnXEpziNI+qZ1cSDIZbiJAFncFfHnxEnAZ9KvSfjU03+g3f7a0/ozMZodC1Y1S3Dzyi+Om+hsoULPXh3H/6lJveL/OtmTht9kA9fVZtMqpWxrcLdjkRsZWQSFW4771+e8guiO7AFhEbyVfTnF9Jg4AoPIXa2SGe+ahzwE= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163766509701468.26312900283745; Tue, 23 Nov 2021 02:58:17 -0800 (PST) Received: from localhost ([::1]:46098 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mpTV8-0001KC-Cx for importer@patchew.org; Tue, 23 Nov 2021 05:58:14 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36028) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpTS9-0006jV-E1 for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:55:09 -0500 Received: from mail-bn1nam07on2083.outbound.protection.outlook.com ([40.107.212.83]:55760 helo=NAM02-BN1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpTS4-0003JX-9o for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:55:08 -0500 Received: from DM6PR06CA0098.namprd06.prod.outlook.com (2603:10b6:5:336::31) by DM6PR02MB4331.namprd02.prod.outlook.com (2603:10b6:5:27::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.24; Tue, 23 Nov 2021 10:34:33 +0000 Received: from DM3NAM02FT019.eop-nam02.prod.protection.outlook.com (2603:10b6:5:336:cafe::fb) by DM6PR06CA0098.outlook.office365.com (2603:10b6:5:336::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.21 via Frontend Transport; Tue, 23 Nov 2021 10:34:33 +0000 Received: from xsj-pvapexch01.xlnx.xilinx.com (149.199.62.198) by DM3NAM02FT019.mail.protection.outlook.com (10.13.4.191) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4713.19 via Frontend Transport; Tue, 23 Nov 2021 10:34:33 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 23 Nov 2021 02:34:32 -0800 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 23 Nov 2021 02:34:32 -0800 Received: from [10.23.120.28] (port=57995 helo=debian.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mpT8B-000GX6-Qe; Tue, 23 Nov 2021 02:34:32 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=L7zmZ+3I3OBZFR5yEpLLCqEomk5dbfdesIhkNdABWHvrmhoPssqLlz+63IoiWWBiEMkmNE5XZ+wcgTxCBrf3mU6KiV25AJt0uB0j4AuLhiEGUrEIhwvrCM5pKHozA8N58bdYWfLt3EcUamIIM3fDOuLkpKHB5OzCxl6dblsRPWmdjnrPABrYYcxlzcEfI39UL6Xl8klLo/5adErnBQGr4WyWdka1bp3m1vUtQXDvjYBLi1CyhvFB4kshnpLRgGW4f83eAAMt7/kjODMqgLCngp/Lyp3fL1DtYoTwEzhgm1OSybeaWplE344bhH5ybXMimo1um5NDhAL0ouqJMIr7kA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=bHo1qfGWn/w/LlJlLvjC07l6l+caTraPyEZ7WMzvu2M=; b=jJBAgQRHNV0oH7lhd7wAWC672rhhRZRrrnGcRSwlfDXk3BJ+lIqXZ8fvcCGzbG7g9pV/chkZpAqQnweMvCjzhPzrPdXHUxTpndm12a9O/FUit3itDlZDtVrxMt8LuzHQxPH4BW8vBQ715Q22ZI0DdsqTN8tbp1vXbvNVv5Sq8FkKjsjpbBqGILvHXwxXqgnGX34Ye8vonTc/NW/xZOLQms4sS+kxRSJHVx+SU/nTIOKRdfB4bhCw70EByaejic/IbBE0iir/OZPljWz9kuiwYrabfEF1A9EvLpoxep7H+F056NLTDt4Wu2vlbEOwzduGNXG7RYRkqNGLkslXz35tBg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=nongnu.org smtp.mailfrom=xilinx.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bHo1qfGWn/w/LlJlLvjC07l6l+caTraPyEZ7WMzvu2M=; b=XcKNC+UXIbSE3x5cIHtcmNpTNfx5orb2dyKppLQxaAB/BXin2fMBGCEWc6rNrh4ZpyDaC0CvOye19Jv/d01lUUKafE+QSbgu7g7FgZwi+XsVCmFj3CWpnBw9yAFTwpcIdNW46FuEa0WqM0nRbhcD7WbZ0Z5aEsoYav1NgKlsTHM= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch01.xlnx.xilinx.com; From: Francisco Iglesias To: Subject: [PATCH v2 01/10] hw/misc: Add a model of Versal's PMC SLCR Date: Tue, 23 Nov 2021 10:34:19 +0000 Message-ID: <20211123103428.8765-2-francisco.iglesias@xilinx.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20211123103428.8765-1-francisco.iglesias@xilinx.com> References: <20211123103428.8765-1-francisco.iglesias@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 04919e06-eef0-4785-a14b-08d9ae6cd6de X-MS-TrafficTypeDiagnostic: DM6PR02MB4331: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MNe1frtl16PZEqwslHudDdLXTPcg2SQsM8txVy8l0caCpXnu02mh4mUw44b6xw+EWXFgccT9czDWKbHEahRCbA764+Izwu9dtuKHUP/pf7Pdxxi+jVEsXLocfh4vZzW7o5ynm046en+X0T6VXyKhkejpwh9FND/e5TLPFQXHQuUmjrW3bOePcoQPKNYo503VmmIfsh6F+z7xxEveXwMMNs5110NXN26sy61fzZrz4hM37Qi/RI01LeBcZ9vA+yeOdDnsxCPqIvxsuuyeSOFxdTxRCjSDQXX9D0PYmyqIlJHGRbQJJpYZpavxUeHDi2HmtdCUeL1a81XIwXxYYYzwNp/bXbhZP19BqJ1RGU+w+k+ziy07H8Dlv59AP7ca0/48lL8CfVnlaohqN1ZHDXraE8Rn43nPTy62SVqdLLsXaQeHcm3gNJ7+o1ocjsQHQJBf0cbjMJnn0jy3RUqsziarGX//vkSLr/Vu7P8TvXbTTR2d0z0I/PZDbPW5nyjvzfz4xkd/FqEfPvlzLptJ8F+xMZhY1KRurEWwEE4hkZuBqU2OUZ4AxDgTpWdmomkINHFDKZOkEb/LzaYnOB8h8PNOmTJeDxq7Veh4axqRk/TIc4QGu79LDkdH85XJLfDGIyUL9Kao33W+ChbevamQ8Unbyinvobe5EO1SB67ud2qyNFNOBtOpt/0FVP0dwLjOO1i0TgyLjKd/JPFU0uIvusUQv6o5/c2HDZLnEcwKLv9h3kiCQexBVGfRCksOGlWaV9YU49TIo5Oj8NwUoo0G0++owA== X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch01.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(36840700001)(46966006)(36860700001)(9786002)(36756003)(6916009)(356005)(7636003)(5660300002)(30864003)(83380400001)(7696005)(2906002)(4326008)(36906005)(54906003)(26005)(426003)(336012)(1076003)(508600001)(47076005)(8936002)(6666004)(8676002)(70586007)(44832011)(70206006)(2616005)(316002)(186003)(82310400004)(102446001)(559001)(579004)(309714004); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2021 10:34:33.3341 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 04919e06-eef0-4785-a14b-08d9ae6cd6de X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT019.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB4331 Received-SPF: pass client-ip=40.107.212.83; envelope-from=figlesia@xilinx.com; helo=NAM02-BN1-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, peter.maydell@linaro.org, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1637665098381100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a model of Versal's PMC SLCR (system-level control registers). Signed-off-by: Francisco Iglesias Signed-off-by: Edgar E. Iglesias Acked-by: Edgar E. Iglesias --- hw/misc/meson.build | 5 +- hw/misc/xlnx-versal-pmc-iou-slcr.c | 1445 ++++++++++++++++++++++++= ++++ include/hw/misc/xlnx-versal-pmc-iou-slcr.h | 51 + 3 files changed, 1500 insertions(+), 1 deletion(-) create mode 100644 hw/misc/xlnx-versal-pmc-iou-slcr.c create mode 100644 include/hw/misc/xlnx-versal-pmc-iou-slcr.h diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 3f41a3a5b2..e82628a618 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -84,7 +84,10 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files( )) softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) -softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-xra= mc.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( + 'xlnx-versal-xramc.c', + 'xlnx-versal-pmc-iou-slcr.c', +)) softmmu_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_= syscfg.c')) softmmu_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_= syscfg.c')) softmmu_ss.add(when: 'CONFIG_STM32F4XX_EXTI', if_true: files('stm32f4xx_ex= ti.c')) diff --git a/hw/misc/xlnx-versal-pmc-iou-slcr.c b/hw/misc/xlnx-versal-pmc-i= ou-slcr.c new file mode 100644 index 0000000000..1d141b4013 --- /dev/null +++ b/hw/misc/xlnx-versal-pmc-iou-slcr.c @@ -0,0 +1,1445 @@ +/* + * QEMU model of Versal's PMC IOU SLCR (system level control registers) + * + * Copyright (c) 2021 Xilinx Inc. + * Written by Edgar E. Iglesias + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/register.h" +#include "hw/irq.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" +#include "hw/misc/xlnx-versal-pmc-iou-slcr.h" + +#ifndef XILINX_VERSAL_PMC_IOU_SLCR_ERR_DEBUG +#define XILINX_VERSAL_PMC_IOU_SLCR_ERR_DEBUG 0 +#endif + +REG32(MIO_PIN_0, 0x0) + FIELD(MIO_PIN_0, L3_SEL, 7, 3) + FIELD(MIO_PIN_0, L2_SEL, 5, 2) + FIELD(MIO_PIN_0, L1_SEL, 3, 2) + FIELD(MIO_PIN_0, L0_SEL, 1, 2) +REG32(MIO_PIN_1, 0x4) + FIELD(MIO_PIN_1, L3_SEL, 7, 3) + FIELD(MIO_PIN_1, L2_SEL, 5, 2) + FIELD(MIO_PIN_1, L1_SEL, 3, 2) + FIELD(MIO_PIN_1, L0_SEL, 1, 2) +REG32(MIO_PIN_2, 0x8) + FIELD(MIO_PIN_2, L3_SEL, 7, 3) + FIELD(MIO_PIN_2, L2_SEL, 5, 2) + FIELD(MIO_PIN_2, L1_SEL, 3, 2) + FIELD(MIO_PIN_2, L0_SEL, 1, 2) +REG32(MIO_PIN_3, 0xc) + FIELD(MIO_PIN_3, L3_SEL, 7, 3) + FIELD(MIO_PIN_3, L2_SEL, 5, 2) + FIELD(MIO_PIN_3, L1_SEL, 3, 2) + FIELD(MIO_PIN_3, L0_SEL, 1, 2) +REG32(MIO_PIN_4, 0x10) + FIELD(MIO_PIN_4, L3_SEL, 7, 3) + FIELD(MIO_PIN_4, L2_SEL, 5, 2) + FIELD(MIO_PIN_4, L1_SEL, 3, 2) + FIELD(MIO_PIN_4, L0_SEL, 1, 2) +REG32(MIO_PIN_5, 0x14) + FIELD(MIO_PIN_5, L3_SEL, 7, 3) + FIELD(MIO_PIN_5, L2_SEL, 5, 2) + FIELD(MIO_PIN_5, L1_SEL, 3, 2) + FIELD(MIO_PIN_5, L0_SEL, 1, 2) +REG32(MIO_PIN_6, 0x18) + FIELD(MIO_PIN_6, L3_SEL, 7, 3) + FIELD(MIO_PIN_6, L2_SEL, 5, 2) + FIELD(MIO_PIN_6, L1_SEL, 3, 2) + FIELD(MIO_PIN_6, L0_SEL, 1, 2) +REG32(MIO_PIN_7, 0x1c) + FIELD(MIO_PIN_7, L3_SEL, 7, 3) + FIELD(MIO_PIN_7, L2_SEL, 5, 2) + FIELD(MIO_PIN_7, L1_SEL, 3, 2) + FIELD(MIO_PIN_7, L0_SEL, 1, 2) +REG32(MIO_PIN_8, 0x20) + FIELD(MIO_PIN_8, L3_SEL, 7, 3) + FIELD(MIO_PIN_8, L2_SEL, 5, 2) + FIELD(MIO_PIN_8, L1_SEL, 3, 2) + FIELD(MIO_PIN_8, L0_SEL, 1, 2) +REG32(MIO_PIN_9, 0x24) + FIELD(MIO_PIN_9, L3_SEL, 7, 3) + FIELD(MIO_PIN_9, L2_SEL, 5, 2) + FIELD(MIO_PIN_9, L1_SEL, 3, 2) + FIELD(MIO_PIN_9, L0_SEL, 1, 2) +REG32(MIO_PIN_10, 0x28) + FIELD(MIO_PIN_10, L3_SEL, 7, 3) + FIELD(MIO_PIN_10, L2_SEL, 5, 2) + FIELD(MIO_PIN_10, L1_SEL, 3, 2) + FIELD(MIO_PIN_10, L0_SEL, 1, 2) +REG32(MIO_PIN_11, 0x2c) + FIELD(MIO_PIN_11, L3_SEL, 7, 3) + FIELD(MIO_PIN_11, L2_SEL, 5, 2) + FIELD(MIO_PIN_11, L1_SEL, 3, 2) + FIELD(MIO_PIN_11, L0_SEL, 1, 2) +REG32(MIO_PIN_12, 0x30) + FIELD(MIO_PIN_12, L3_SEL, 7, 3) + FIELD(MIO_PIN_12, L2_SEL, 5, 2) + FIELD(MIO_PIN_12, L1_SEL, 3, 2) + FIELD(MIO_PIN_12, L0_SEL, 1, 2) +REG32(MIO_PIN_13, 0x34) + FIELD(MIO_PIN_13, L3_SEL, 7, 3) + FIELD(MIO_PIN_13, L2_SEL, 5, 2) + FIELD(MIO_PIN_13, L1_SEL, 3, 2) + FIELD(MIO_PIN_13, L0_SEL, 1, 2) +REG32(MIO_PIN_14, 0x38) + FIELD(MIO_PIN_14, L3_SEL, 7, 3) + FIELD(MIO_PIN_14, L2_SEL, 5, 2) + FIELD(MIO_PIN_14, L1_SEL, 3, 2) + FIELD(MIO_PIN_14, L0_SEL, 1, 2) +REG32(MIO_PIN_15, 0x3c) + FIELD(MIO_PIN_15, L3_SEL, 7, 3) + FIELD(MIO_PIN_15, L2_SEL, 5, 2) + FIELD(MIO_PIN_15, L1_SEL, 3, 2) + FIELD(MIO_PIN_15, L0_SEL, 1, 2) +REG32(MIO_PIN_16, 0x40) + FIELD(MIO_PIN_16, L3_SEL, 7, 3) + FIELD(MIO_PIN_16, L2_SEL, 5, 2) + FIELD(MIO_PIN_16, L1_SEL, 3, 2) + FIELD(MIO_PIN_16, L0_SEL, 1, 2) +REG32(MIO_PIN_17, 0x44) + FIELD(MIO_PIN_17, L3_SEL, 7, 3) + FIELD(MIO_PIN_17, L2_SEL, 5, 2) + FIELD(MIO_PIN_17, L1_SEL, 3, 2) + FIELD(MIO_PIN_17, L0_SEL, 1, 2) +REG32(MIO_PIN_18, 0x48) + FIELD(MIO_PIN_18, L3_SEL, 7, 3) + FIELD(MIO_PIN_18, L2_SEL, 5, 2) + FIELD(MIO_PIN_18, L1_SEL, 3, 2) + FIELD(MIO_PIN_18, L0_SEL, 1, 2) +REG32(MIO_PIN_19, 0x4c) + FIELD(MIO_PIN_19, L3_SEL, 7, 3) + FIELD(MIO_PIN_19, L2_SEL, 5, 2) + FIELD(MIO_PIN_19, L1_SEL, 3, 2) + FIELD(MIO_PIN_19, L0_SEL, 1, 2) +REG32(MIO_PIN_20, 0x50) + FIELD(MIO_PIN_20, L3_SEL, 7, 3) + FIELD(MIO_PIN_20, L2_SEL, 5, 2) + FIELD(MIO_PIN_20, L1_SEL, 3, 2) + FIELD(MIO_PIN_20, L0_SEL, 1, 2) +REG32(MIO_PIN_21, 0x54) + FIELD(MIO_PIN_21, L3_SEL, 7, 3) + FIELD(MIO_PIN_21, L2_SEL, 5, 2) + FIELD(MIO_PIN_21, L1_SEL, 3, 2) + FIELD(MIO_PIN_21, L0_SEL, 1, 2) +REG32(MIO_PIN_22, 0x58) + FIELD(MIO_PIN_22, L3_SEL, 7, 3) + FIELD(MIO_PIN_22, L2_SEL, 5, 2) + FIELD(MIO_PIN_22, L1_SEL, 3, 2) + FIELD(MIO_PIN_22, L0_SEL, 1, 2) +REG32(MIO_PIN_23, 0x5c) + FIELD(MIO_PIN_23, L3_SEL, 7, 3) + FIELD(MIO_PIN_23, L2_SEL, 5, 2) + FIELD(MIO_PIN_23, L1_SEL, 3, 2) + FIELD(MIO_PIN_23, L0_SEL, 1, 2) +REG32(MIO_PIN_24, 0x60) + FIELD(MIO_PIN_24, L3_SEL, 7, 3) + FIELD(MIO_PIN_24, L2_SEL, 5, 2) + FIELD(MIO_PIN_24, L1_SEL, 3, 2) + FIELD(MIO_PIN_24, L0_SEL, 1, 2) +REG32(MIO_PIN_25, 0x64) + FIELD(MIO_PIN_25, L3_SEL, 7, 3) + FIELD(MIO_PIN_25, L2_SEL, 5, 2) + FIELD(MIO_PIN_25, L1_SEL, 3, 2) + FIELD(MIO_PIN_25, L0_SEL, 1, 2) +REG32(MIO_PIN_26, 0x68) + FIELD(MIO_PIN_26, L3_SEL, 7, 3) + FIELD(MIO_PIN_26, L2_SEL, 5, 2) + FIELD(MIO_PIN_26, L1_SEL, 3, 2) + FIELD(MIO_PIN_26, L0_SEL, 1, 2) +REG32(MIO_PIN_27, 0x6c) + FIELD(MIO_PIN_27, L3_SEL, 7, 3) + FIELD(MIO_PIN_27, L2_SEL, 5, 2) + FIELD(MIO_PIN_27, L1_SEL, 3, 2) + FIELD(MIO_PIN_27, L0_SEL, 1, 2) +REG32(MIO_PIN_28, 0x70) + FIELD(MIO_PIN_28, L3_SEL, 7, 3) + FIELD(MIO_PIN_28, L2_SEL, 5, 2) + FIELD(MIO_PIN_28, L1_SEL, 3, 2) + FIELD(MIO_PIN_28, L0_SEL, 1, 2) +REG32(MIO_PIN_29, 0x74) + FIELD(MIO_PIN_29, L3_SEL, 7, 3) + FIELD(MIO_PIN_29, L2_SEL, 5, 2) + FIELD(MIO_PIN_29, L1_SEL, 3, 2) + FIELD(MIO_PIN_29, L0_SEL, 1, 2) +REG32(MIO_PIN_30, 0x78) + FIELD(MIO_PIN_30, L3_SEL, 7, 3) + FIELD(MIO_PIN_30, L2_SEL, 5, 2) + FIELD(MIO_PIN_30, L1_SEL, 3, 2) + FIELD(MIO_PIN_30, L0_SEL, 1, 2) +REG32(MIO_PIN_31, 0x7c) + FIELD(MIO_PIN_31, L3_SEL, 7, 3) + FIELD(MIO_PIN_31, L2_SEL, 5, 2) + FIELD(MIO_PIN_31, L1_SEL, 3, 2) + FIELD(MIO_PIN_31, L0_SEL, 1, 2) +REG32(MIO_PIN_32, 0x80) + FIELD(MIO_PIN_32, L3_SEL, 7, 3) + FIELD(MIO_PIN_32, L2_SEL, 5, 2) + FIELD(MIO_PIN_32, L1_SEL, 3, 2) + FIELD(MIO_PIN_32, L0_SEL, 1, 2) +REG32(MIO_PIN_33, 0x84) + FIELD(MIO_PIN_33, L3_SEL, 7, 3) + FIELD(MIO_PIN_33, L2_SEL, 5, 2) + FIELD(MIO_PIN_33, L1_SEL, 3, 2) + FIELD(MIO_PIN_33, L0_SEL, 1, 2) +REG32(MIO_PIN_34, 0x88) + FIELD(MIO_PIN_34, L3_SEL, 7, 3) + FIELD(MIO_PIN_34, L2_SEL, 5, 2) + FIELD(MIO_PIN_34, L1_SEL, 3, 2) + FIELD(MIO_PIN_34, L0_SEL, 1, 2) +REG32(MIO_PIN_35, 0x8c) + FIELD(MIO_PIN_35, L3_SEL, 7, 3) + FIELD(MIO_PIN_35, L2_SEL, 5, 2) + FIELD(MIO_PIN_35, L1_SEL, 3, 2) + FIELD(MIO_PIN_35, L0_SEL, 1, 2) +REG32(MIO_PIN_36, 0x90) + FIELD(MIO_PIN_36, L3_SEL, 7, 3) + FIELD(MIO_PIN_36, L2_SEL, 5, 2) + FIELD(MIO_PIN_36, L1_SEL, 3, 2) + FIELD(MIO_PIN_36, L0_SEL, 1, 2) +REG32(MIO_PIN_37, 0x94) + FIELD(MIO_PIN_37, L3_SEL, 7, 3) + FIELD(MIO_PIN_37, L2_SEL, 5, 2) + FIELD(MIO_PIN_37, L1_SEL, 3, 2) + FIELD(MIO_PIN_37, L0_SEL, 1, 2) +REG32(MIO_PIN_38, 0x98) + FIELD(MIO_PIN_38, L3_SEL, 7, 3) + FIELD(MIO_PIN_38, L2_SEL, 5, 2) + FIELD(MIO_PIN_38, L1_SEL, 3, 2) + FIELD(MIO_PIN_38, L0_SEL, 1, 2) +REG32(MIO_PIN_39, 0x9c) + FIELD(MIO_PIN_39, L3_SEL, 7, 3) + FIELD(MIO_PIN_39, L2_SEL, 5, 2) + FIELD(MIO_PIN_39, L1_SEL, 3, 2) + FIELD(MIO_PIN_39, L0_SEL, 1, 2) +REG32(MIO_PIN_40, 0xa0) + FIELD(MIO_PIN_40, L3_SEL, 7, 3) + FIELD(MIO_PIN_40, L2_SEL, 5, 2) + FIELD(MIO_PIN_40, L1_SEL, 3, 2) + FIELD(MIO_PIN_40, L0_SEL, 1, 2) +REG32(MIO_PIN_41, 0xa4) + FIELD(MIO_PIN_41, L3_SEL, 7, 3) + FIELD(MIO_PIN_41, L2_SEL, 5, 2) + FIELD(MIO_PIN_41, L1_SEL, 3, 2) + FIELD(MIO_PIN_41, L0_SEL, 1, 2) +REG32(MIO_PIN_42, 0xa8) + FIELD(MIO_PIN_42, L3_SEL, 7, 3) + FIELD(MIO_PIN_42, L2_SEL, 5, 2) + FIELD(MIO_PIN_42, L1_SEL, 3, 2) + FIELD(MIO_PIN_42, L0_SEL, 1, 2) +REG32(MIO_PIN_43, 0xac) + FIELD(MIO_PIN_43, L3_SEL, 7, 3) + FIELD(MIO_PIN_43, L2_SEL, 5, 2) + FIELD(MIO_PIN_43, L1_SEL, 3, 2) + FIELD(MIO_PIN_43, L0_SEL, 1, 2) +REG32(MIO_PIN_44, 0xb0) + FIELD(MIO_PIN_44, L3_SEL, 7, 3) + FIELD(MIO_PIN_44, L2_SEL, 5, 2) + FIELD(MIO_PIN_44, L1_SEL, 3, 2) + FIELD(MIO_PIN_44, L0_SEL, 1, 2) +REG32(MIO_PIN_45, 0xb4) + FIELD(MIO_PIN_45, L3_SEL, 7, 3) + FIELD(MIO_PIN_45, L2_SEL, 5, 2) + FIELD(MIO_PIN_45, L1_SEL, 3, 2) + FIELD(MIO_PIN_45, L0_SEL, 1, 2) +REG32(MIO_PIN_46, 0xb8) + FIELD(MIO_PIN_46, L3_SEL, 7, 3) + FIELD(MIO_PIN_46, L2_SEL, 5, 2) + FIELD(MIO_PIN_46, L1_SEL, 3, 2) + FIELD(MIO_PIN_46, L0_SEL, 1, 2) +REG32(MIO_PIN_47, 0xbc) + FIELD(MIO_PIN_47, L3_SEL, 7, 3) + FIELD(MIO_PIN_47, L2_SEL, 5, 2) + FIELD(MIO_PIN_47, L1_SEL, 3, 2) + FIELD(MIO_PIN_47, L0_SEL, 1, 2) +REG32(MIO_PIN_48, 0xc0) + FIELD(MIO_PIN_48, L3_SEL, 7, 3) + FIELD(MIO_PIN_48, L2_SEL, 5, 2) + FIELD(MIO_PIN_48, L1_SEL, 3, 2) + FIELD(MIO_PIN_48, L0_SEL, 1, 2) +REG32(MIO_PIN_49, 0xc4) + FIELD(MIO_PIN_49, L3_SEL, 7, 3) + FIELD(MIO_PIN_49, L2_SEL, 5, 2) + FIELD(MIO_PIN_49, L1_SEL, 3, 2) + FIELD(MIO_PIN_49, L0_SEL, 1, 2) +REG32(MIO_PIN_50, 0xc8) + FIELD(MIO_PIN_50, L3_SEL, 7, 3) + FIELD(MIO_PIN_50, L2_SEL, 5, 2) + FIELD(MIO_PIN_50, L1_SEL, 3, 2) + FIELD(MIO_PIN_50, L0_SEL, 1, 2) +REG32(MIO_PIN_51, 0xcc) + FIELD(MIO_PIN_51, L3_SEL, 7, 3) + FIELD(MIO_PIN_51, L2_SEL, 5, 2) + FIELD(MIO_PIN_51, L1_SEL, 3, 2) + FIELD(MIO_PIN_51, L0_SEL, 1, 2) +REG32(BNK0_EN_RX, 0x100) + FIELD(BNK0_EN_RX, BNK0_EN_RX, 0, 26) +REG32(BNK0_SEL_RX0, 0x104) +REG32(BNK0_SEL_RX1, 0x108) + FIELD(BNK0_SEL_RX1, BNK0_SEL_RX, 0, 20) +REG32(BNK0_EN_RX_SCHMITT_HYST, 0x10c) + FIELD(BNK0_EN_RX_SCHMITT_HYST, BNK0_EN_RX_SCHMITT_HYST, 0, 26) +REG32(BNK0_EN_WK_PD, 0x110) + FIELD(BNK0_EN_WK_PD, BNK0_EN_WK_PD, 0, 26) +REG32(BNK0_EN_WK_PU, 0x114) + FIELD(BNK0_EN_WK_PU, BNK0_EN_WK_PU, 0, 26) +REG32(BNK0_SEL_DRV0, 0x118) +REG32(BNK0_SEL_DRV1, 0x11c) + FIELD(BNK0_SEL_DRV1, BNK0_SEL_DRV, 0, 20) +REG32(BNK0_SEL_SLEW, 0x120) + FIELD(BNK0_SEL_SLEW, BNK0_SEL_SLEW, 0, 26) +REG32(BNK0_EN_DFT_OPT_INV, 0x124) + FIELD(BNK0_EN_DFT_OPT_INV, BNK0_EN_DFT_OPT_INV, 0, 26) +REG32(BNK0_EN_PAD2PAD_LOOPBACK, 0x128) + FIELD(BNK0_EN_PAD2PAD_LOOPBACK, BNK0_EN_PAD2PAD_LOOPBACK, 0, 13) +REG32(BNK0_RX_SPARE0, 0x12c) +REG32(BNK0_RX_SPARE1, 0x130) + FIELD(BNK0_RX_SPARE1, BNK0_RX_SPARE, 0, 20) +REG32(BNK0_TX_SPARE0, 0x134) +REG32(BNK0_TX_SPARE1, 0x138) + FIELD(BNK0_TX_SPARE1, BNK0_TX_SPARE, 0, 20) +REG32(BNK0_SEL_EN1P8, 0x13c) + FIELD(BNK0_SEL_EN1P8, BNK0_SEL_EN1P8, 0, 1) +REG32(BNK0_EN_B_POR_DETECT, 0x140) + FIELD(BNK0_EN_B_POR_DETECT, BNK0_EN_B_POR_DETECT, 0, 1) +REG32(BNK0_LPF_BYP_POR_DETECT, 0x144) + FIELD(BNK0_LPF_BYP_POR_DETECT, BNK0_LPF_BYP_POR_DETECT, 0, 1) +REG32(BNK0_EN_LATCH, 0x148) + FIELD(BNK0_EN_LATCH, BNK0_EN_LATCH, 0, 1) +REG32(BNK0_VBG_LPF_BYP_B, 0x14c) + FIELD(BNK0_VBG_LPF_BYP_B, BNK0_VBG_LPF_BYP_B, 0, 1) +REG32(BNK0_EN_AMP_B, 0x150) + FIELD(BNK0_EN_AMP_B, BNK0_EN_AMP_B, 0, 2) +REG32(BNK0_SPARE_BIAS, 0x154) + FIELD(BNK0_SPARE_BIAS, BNK0_SPARE_BIAS, 0, 4) +REG32(BNK0_DRIVER_BIAS, 0x158) + FIELD(BNK0_DRIVER_BIAS, BNK0_DRIVER_BIAS, 0, 15) +REG32(BNK0_VMODE, 0x15c) + FIELD(BNK0_VMODE, BNK0_VMODE, 0, 1) +REG32(BNK0_SEL_AUX_IO_RX, 0x160) + FIELD(BNK0_SEL_AUX_IO_RX, BNK0_SEL_AUX_IO_RX, 0, 26) +REG32(BNK0_EN_TX_HS_MODE, 0x164) + FIELD(BNK0_EN_TX_HS_MODE, BNK0_EN_TX_HS_MODE, 0, 26) +REG32(MIO_MST_TRI0, 0x200) + FIELD(MIO_MST_TRI0, PIN_25_TRI, 25, 1) + FIELD(MIO_MST_TRI0, PIN_24_TRI, 24, 1) + FIELD(MIO_MST_TRI0, PIN_23_TRI, 23, 1) + FIELD(MIO_MST_TRI0, PIN_22_TRI, 22, 1) + FIELD(MIO_MST_TRI0, PIN_21_TRI, 21, 1) + FIELD(MIO_MST_TRI0, PIN_20_TRI, 20, 1) + FIELD(MIO_MST_TRI0, PIN_19_TRI, 19, 1) + FIELD(MIO_MST_TRI0, PIN_18_TRI, 18, 1) + FIELD(MIO_MST_TRI0, PIN_17_TRI, 17, 1) + FIELD(MIO_MST_TRI0, PIN_16_TRI, 16, 1) + FIELD(MIO_MST_TRI0, PIN_15_TRI, 15, 1) + FIELD(MIO_MST_TRI0, PIN_14_TRI, 14, 1) + FIELD(MIO_MST_TRI0, PIN_13_TRI, 13, 1) + FIELD(MIO_MST_TRI0, PIN_12_TRI, 12, 1) + FIELD(MIO_MST_TRI0, PIN_11_TRI, 11, 1) + FIELD(MIO_MST_TRI0, PIN_10_TRI, 10, 1) + FIELD(MIO_MST_TRI0, PIN_09_TRI, 9, 1) + FIELD(MIO_MST_TRI0, PIN_08_TRI, 8, 1) + FIELD(MIO_MST_TRI0, PIN_07_TRI, 7, 1) + FIELD(MIO_MST_TRI0, PIN_06_TRI, 6, 1) + FIELD(MIO_MST_TRI0, PIN_05_TRI, 5, 1) + FIELD(MIO_MST_TRI0, PIN_04_TRI, 4, 1) + FIELD(MIO_MST_TRI0, PIN_03_TRI, 3, 1) + FIELD(MIO_MST_TRI0, PIN_02_TRI, 2, 1) + FIELD(MIO_MST_TRI0, PIN_01_TRI, 1, 1) + FIELD(MIO_MST_TRI0, PIN_00_TRI, 0, 1) +REG32(MIO_MST_TRI1, 0x204) + FIELD(MIO_MST_TRI1, PIN_51_TRI, 25, 1) + FIELD(MIO_MST_TRI1, PIN_50_TRI, 24, 1) + FIELD(MIO_MST_TRI1, PIN_49_TRI, 23, 1) + FIELD(MIO_MST_TRI1, PIN_48_TRI, 22, 1) + FIELD(MIO_MST_TRI1, PIN_47_TRI, 21, 1) + FIELD(MIO_MST_TRI1, PIN_46_TRI, 20, 1) + FIELD(MIO_MST_TRI1, PIN_45_TRI, 19, 1) + FIELD(MIO_MST_TRI1, PIN_44_TRI, 18, 1) + FIELD(MIO_MST_TRI1, PIN_43_TRI, 17, 1) + FIELD(MIO_MST_TRI1, PIN_42_TRI, 16, 1) + FIELD(MIO_MST_TRI1, PIN_41_TRI, 15, 1) + FIELD(MIO_MST_TRI1, PIN_40_TRI, 14, 1) + FIELD(MIO_MST_TRI1, PIN_39_TRI, 13, 1) + FIELD(MIO_MST_TRI1, PIN_38_TRI, 12, 1) + FIELD(MIO_MST_TRI1, PIN_37_TRI, 11, 1) + FIELD(MIO_MST_TRI1, PIN_36_TRI, 10, 1) + FIELD(MIO_MST_TRI1, PIN_35_TRI, 9, 1) + FIELD(MIO_MST_TRI1, PIN_34_TRI, 8, 1) + FIELD(MIO_MST_TRI1, PIN_33_TRI, 7, 1) + FIELD(MIO_MST_TRI1, PIN_32_TRI, 6, 1) + FIELD(MIO_MST_TRI1, PIN_31_TRI, 5, 1) + FIELD(MIO_MST_TRI1, PIN_30_TRI, 4, 1) + FIELD(MIO_MST_TRI1, PIN_29_TRI, 3, 1) + FIELD(MIO_MST_TRI1, PIN_28_TRI, 2, 1) + FIELD(MIO_MST_TRI1, PIN_27_TRI, 1, 1) + FIELD(MIO_MST_TRI1, PIN_26_TRI, 0, 1) +REG32(BNK1_EN_RX, 0x300) + FIELD(BNK1_EN_RX, BNK1_EN_RX, 0, 26) +REG32(BNK1_SEL_RX0, 0x304) +REG32(BNK1_SEL_RX1, 0x308) + FIELD(BNK1_SEL_RX1, BNK1_SEL_RX, 0, 20) +REG32(BNK1_EN_RX_SCHMITT_HYST, 0x30c) + FIELD(BNK1_EN_RX_SCHMITT_HYST, BNK1_EN_RX_SCHMITT_HYST, 0, 26) +REG32(BNK1_EN_WK_PD, 0x310) + FIELD(BNK1_EN_WK_PD, BNK1_EN_WK_PD, 0, 26) +REG32(BNK1_EN_WK_PU, 0x314) + FIELD(BNK1_EN_WK_PU, BNK1_EN_WK_PU, 0, 26) +REG32(BNK1_SEL_DRV0, 0x318) +REG32(BNK1_SEL_DRV1, 0x31c) + FIELD(BNK1_SEL_DRV1, BNK1_SEL_DRV, 0, 20) +REG32(BNK1_SEL_SLEW, 0x320) + FIELD(BNK1_SEL_SLEW, BNK1_SEL_SLEW, 0, 26) +REG32(BNK1_EN_DFT_OPT_INV, 0x324) + FIELD(BNK1_EN_DFT_OPT_INV, BNK1_EN_DFT_OPT_INV, 0, 26) +REG32(BNK1_EN_PAD2PAD_LOOPBACK, 0x328) + FIELD(BNK1_EN_PAD2PAD_LOOPBACK, BNK1_EN_PAD2PAD_LOOPBACK, 0, 13) +REG32(BNK1_RX_SPARE0, 0x32c) +REG32(BNK1_RX_SPARE1, 0x330) + FIELD(BNK1_RX_SPARE1, BNK1_RX_SPARE, 0, 20) +REG32(BNK1_TX_SPARE0, 0x334) +REG32(BNK1_TX_SPARE1, 0x338) + FIELD(BNK1_TX_SPARE1, BNK1_TX_SPARE, 0, 20) +REG32(BNK1_SEL_EN1P8, 0x33c) + FIELD(BNK1_SEL_EN1P8, BNK1_SEL_EN1P8, 0, 1) +REG32(BNK1_EN_B_POR_DETECT, 0x340) + FIELD(BNK1_EN_B_POR_DETECT, BNK1_EN_B_POR_DETECT, 0, 1) +REG32(BNK1_LPF_BYP_POR_DETECT, 0x344) + FIELD(BNK1_LPF_BYP_POR_DETECT, BNK1_LPF_BYP_POR_DETECT, 0, 1) +REG32(BNK1_EN_LATCH, 0x348) + FIELD(BNK1_EN_LATCH, BNK1_EN_LATCH, 0, 1) +REG32(BNK1_VBG_LPF_BYP_B, 0x34c) + FIELD(BNK1_VBG_LPF_BYP_B, BNK1_VBG_LPF_BYP_B, 0, 1) +REG32(BNK1_EN_AMP_B, 0x350) + FIELD(BNK1_EN_AMP_B, BNK1_EN_AMP_B, 0, 2) +REG32(BNK1_SPARE_BIAS, 0x354) + FIELD(BNK1_SPARE_BIAS, BNK1_SPARE_BIAS, 0, 4) +REG32(BNK1_DRIVER_BIAS, 0x358) + FIELD(BNK1_DRIVER_BIAS, BNK1_DRIVER_BIAS, 0, 15) +REG32(BNK1_VMODE, 0x35c) + FIELD(BNK1_VMODE, BNK1_VMODE, 0, 1) +REG32(BNK1_SEL_AUX_IO_RX, 0x360) + FIELD(BNK1_SEL_AUX_IO_RX, BNK1_SEL_AUX_IO_RX, 0, 26) +REG32(BNK1_EN_TX_HS_MODE, 0x364) + FIELD(BNK1_EN_TX_HS_MODE, BNK1_EN_TX_HS_MODE, 0, 26) +REG32(SD0_CLK_CTRL, 0x400) + FIELD(SD0_CLK_CTRL, SDIO0_FBCLK_SEL, 2, 1) + FIELD(SD0_CLK_CTRL, SDIO0_RX_SRC_SEL, 0, 2) +REG32(SD0_CTRL_REG, 0x404) + FIELD(SD0_CTRL_REG, SD0_EMMC_SEL, 0, 1) +REG32(SD0_CONFIG_REG1, 0x410) + FIELD(SD0_CONFIG_REG1, SD0_BASECLK, 7, 8) + FIELD(SD0_CONFIG_REG1, SD0_TUNIGCOUNT, 1, 6) + FIELD(SD0_CONFIG_REG1, SD0_ASYNCWKPENA, 0, 1) +REG32(SD0_CONFIG_REG2, 0x414) + FIELD(SD0_CONFIG_REG2, SD0_SLOTTYPE, 12, 2) + FIELD(SD0_CONFIG_REG2, SD0_ASYCINTR, 11, 1) + FIELD(SD0_CONFIG_REG2, SD0_64BIT, 10, 1) + FIELD(SD0_CONFIG_REG2, SD0_1P8V, 9, 1) + FIELD(SD0_CONFIG_REG2, SD0_3P0V, 8, 1) + FIELD(SD0_CONFIG_REG2, SD0_3P3V, 7, 1) + FIELD(SD0_CONFIG_REG2, SD0_SUSPRES, 6, 1) + FIELD(SD0_CONFIG_REG2, SD0_SDMA, 5, 1) + FIELD(SD0_CONFIG_REG2, SD0_HIGHSPEED, 4, 1) + FIELD(SD0_CONFIG_REG2, SD0_ADMA2, 3, 1) + FIELD(SD0_CONFIG_REG2, SD0_8BIT, 2, 1) + FIELD(SD0_CONFIG_REG2, SD0_MAXBLK, 0, 2) +REG32(SD0_CONFIG_REG3, 0x418) + FIELD(SD0_CONFIG_REG3, SD0_TUNINGSDR50, 10, 1) + FIELD(SD0_CONFIG_REG3, SD0_RETUNETMR, 6, 4) + FIELD(SD0_CONFIG_REG3, SD0_DDRIVER, 5, 1) + FIELD(SD0_CONFIG_REG3, SD0_CDRIVER, 4, 1) + FIELD(SD0_CONFIG_REG3, SD0_ADRIVER, 3, 1) + FIELD(SD0_CONFIG_REG3, SD0_DDR50, 2, 1) + FIELD(SD0_CONFIG_REG3, SD0_SDR104, 1, 1) + FIELD(SD0_CONFIG_REG3, SD0_SDR50, 0, 1) +REG32(SD0_INITPRESET, 0x41c) + FIELD(SD0_INITPRESET, SD0_INITPRESET, 0, 13) +REG32(SD0_DSPPRESET, 0x420) + FIELD(SD0_DSPPRESET, SD0_DSPPRESET, 0, 13) +REG32(SD0_HSPDPRESET, 0x424) + FIELD(SD0_HSPDPRESET, SD0_HSPDPRESET, 0, 13) +REG32(SD0_SDR12PRESET, 0x428) + FIELD(SD0_SDR12PRESET, SD0_SDR12PRESET, 0, 13) +REG32(SD0_SDR25PRESET, 0x42c) + FIELD(SD0_SDR25PRESET, SD0_SDR25PRESET, 0, 13) +REG32(SD0_SDR50PRSET, 0x430) + FIELD(SD0_SDR50PRSET, SD0_SDR50PRESET, 0, 13) +REG32(SD0_SDR104PRST, 0x434) + FIELD(SD0_SDR104PRST, SD0_SDR104PRESET, 0, 13) +REG32(SD0_DDR50PRESET, 0x438) + FIELD(SD0_DDR50PRESET, SD0_DDR50PRESET, 0, 13) +REG32(SD0_MAXCUR1P8, 0x43c) + FIELD(SD0_MAXCUR1P8, SD0_MAXCUR1P8, 0, 8) +REG32(SD0_MAXCUR3P0, 0x440) + FIELD(SD0_MAXCUR3P0, SD0_MAXCUR3P0, 0, 8) +REG32(SD0_MAXCUR3P3, 0x444) + FIELD(SD0_MAXCUR3P3, SD0_MAXCUR3P3, 0, 8) +REG32(SD0_DLL_CTRL, 0x448) + FIELD(SD0_DLL_CTRL, SD0_CLKSTABLE_CFG, 9, 1) + FIELD(SD0_DLL_CTRL, SD0_DLL_CFG, 5, 4) + FIELD(SD0_DLL_CTRL, SD0_DLL_PSDONE, 4, 1) + FIELD(SD0_DLL_CTRL, SD0_DLL_OVF, 3, 1) + FIELD(SD0_DLL_CTRL, SD0_DLL_RST, 2, 1) + FIELD(SD0_DLL_CTRL, SD0_DLL_TESTMODE, 1, 1) + FIELD(SD0_DLL_CTRL, SD0_DLL_LOCK, 0, 1) +REG32(SD0_CDN_CTRL, 0x44c) + FIELD(SD0_CDN_CTRL, SD0_CDN_CTRL, 0, 1) +REG32(SD0_DLL_TEST, 0x450) + FIELD(SD0_DLL_TEST, DLL_DIV, 16, 8) + FIELD(SD0_DLL_TEST, DLL_TX_SEL, 9, 7) + FIELD(SD0_DLL_TEST, DLL_RX_SEL, 0, 9) +REG32(SD0_RX_TUNING_SEL, 0x454) + FIELD(SD0_RX_TUNING_SEL, SD0_RX_SEL, 0, 9) +REG32(SD0_DLL_DIV_MAP0, 0x458) + FIELD(SD0_DLL_DIV_MAP0, DIV_3, 24, 8) + FIELD(SD0_DLL_DIV_MAP0, DIV_2, 16, 8) + FIELD(SD0_DLL_DIV_MAP0, DIV_1, 8, 8) + FIELD(SD0_DLL_DIV_MAP0, DIV_0, 0, 8) +REG32(SD0_DLL_DIV_MAP1, 0x45c) + FIELD(SD0_DLL_DIV_MAP1, DIV_7, 24, 8) + FIELD(SD0_DLL_DIV_MAP1, DIV_6, 16, 8) + FIELD(SD0_DLL_DIV_MAP1, DIV_5, 8, 8) + FIELD(SD0_DLL_DIV_MAP1, DIV_4, 0, 8) +REG32(SD0_IOU_COHERENT_CTRL, 0x460) + FIELD(SD0_IOU_COHERENT_CTRL, SD0_AXI_COH, 0, 4) +REG32(SD0_IOU_INTERCONNECT_ROUTE, 0x464) + FIELD(SD0_IOU_INTERCONNECT_ROUTE, SD0, 0, 1) +REG32(SD0_IOU_RAM, 0x468) + FIELD(SD0_IOU_RAM, EMASA0, 6, 1) + FIELD(SD0_IOU_RAM, EMAB0, 3, 3) + FIELD(SD0_IOU_RAM, EMAA0, 0, 3) +REG32(SD0_IOU_INTERCONNECT_QOS, 0x46c) + FIELD(SD0_IOU_INTERCONNECT_QOS, SD0_QOS, 0, 4) +REG32(SD1_CLK_CTRL, 0x480) + FIELD(SD1_CLK_CTRL, SDIO1_FBCLK_SEL, 1, 1) + FIELD(SD1_CLK_CTRL, SDIO1_RX_SRC_SEL, 0, 1) +REG32(SD1_CTRL_REG, 0x484) + FIELD(SD1_CTRL_REG, SD1_EMMC_SEL, 0, 1) +REG32(SD1_CONFIG_REG1, 0x490) + FIELD(SD1_CONFIG_REG1, SD1_BASECLK, 7, 8) + FIELD(SD1_CONFIG_REG1, SD1_TUNIGCOUNT, 1, 6) + FIELD(SD1_CONFIG_REG1, SD1_ASYNCWKPENA, 0, 1) +REG32(SD1_CONFIG_REG2, 0x494) + FIELD(SD1_CONFIG_REG2, SD1_SLOTTYPE, 12, 2) + FIELD(SD1_CONFIG_REG2, SD1_ASYCINTR, 11, 1) + FIELD(SD1_CONFIG_REG2, SD1_64BIT, 10, 1) + FIELD(SD1_CONFIG_REG2, SD1_1P8V, 9, 1) + FIELD(SD1_CONFIG_REG2, SD1_3P0V, 8, 1) + FIELD(SD1_CONFIG_REG2, SD1_3P3V, 7, 1) + FIELD(SD1_CONFIG_REG2, SD1_SUSPRES, 6, 1) + FIELD(SD1_CONFIG_REG2, SD1_SDMA, 5, 1) + FIELD(SD1_CONFIG_REG2, SD1_HIGHSPEED, 4, 1) + FIELD(SD1_CONFIG_REG2, SD1_ADMA2, 3, 1) + FIELD(SD1_CONFIG_REG2, SD1_8BIT, 2, 1) + FIELD(SD1_CONFIG_REG2, SD1_MAXBLK, 0, 2) +REG32(SD1_CONFIG_REG3, 0x498) + FIELD(SD1_CONFIG_REG3, SD1_TUNINGSDR50, 10, 1) + FIELD(SD1_CONFIG_REG3, SD1_RETUNETMR, 6, 4) + FIELD(SD1_CONFIG_REG3, SD1_DDRIVER, 5, 1) + FIELD(SD1_CONFIG_REG3, SD1_CDRIVER, 4, 1) + FIELD(SD1_CONFIG_REG3, SD1_ADRIVER, 3, 1) + FIELD(SD1_CONFIG_REG3, SD1_DDR50, 2, 1) + FIELD(SD1_CONFIG_REG3, SD1_SDR104, 1, 1) + FIELD(SD1_CONFIG_REG3, SD1_SDR50, 0, 1) +REG32(SD1_INITPRESET, 0x49c) + FIELD(SD1_INITPRESET, SD1_INITPRESET, 0, 13) +REG32(SD1_DSPPRESET, 0x4a0) + FIELD(SD1_DSPPRESET, SD1_DSPPRESET, 0, 13) +REG32(SD1_HSPDPRESET, 0x4a4) + FIELD(SD1_HSPDPRESET, SD1_HSPDPRESET, 0, 13) +REG32(SD1_SDR12PRESET, 0x4a8) + FIELD(SD1_SDR12PRESET, SD1_SDR12PRESET, 0, 13) +REG32(SD1_SDR25PRESET, 0x4ac) + FIELD(SD1_SDR25PRESET, SD1_SDR25PRESET, 0, 13) +REG32(SD1_SDR50PRSET, 0x4b0) + FIELD(SD1_SDR50PRSET, SD1_SDR50PRESET, 0, 13) +REG32(SD1_SDR104PRST, 0x4b4) + FIELD(SD1_SDR104PRST, SD1_SDR104PRESET, 0, 13) +REG32(SD1_DDR50PRESET, 0x4b8) + FIELD(SD1_DDR50PRESET, SD1_DDR50PRESET, 0, 13) +REG32(SD1_MAXCUR1P8, 0x4bc) + FIELD(SD1_MAXCUR1P8, SD1_MAXCUR1P8, 0, 8) +REG32(SD1_MAXCUR3P0, 0x4c0) + FIELD(SD1_MAXCUR3P0, SD1_MAXCUR3P0, 0, 8) +REG32(SD1_MAXCUR3P3, 0x4c4) + FIELD(SD1_MAXCUR3P3, SD1_MAXCUR3P3, 0, 8) +REG32(SD1_DLL_CTRL, 0x4c8) + FIELD(SD1_DLL_CTRL, SD1_CLKSTABLE_CFG, 9, 1) + FIELD(SD1_DLL_CTRL, SD1_DLL_CFG, 5, 4) + FIELD(SD1_DLL_CTRL, SD1_DLL_PSDONE, 4, 1) + FIELD(SD1_DLL_CTRL, SD1_DLL_OVF, 3, 1) + FIELD(SD1_DLL_CTRL, SD1_DLL_RST, 2, 1) + FIELD(SD1_DLL_CTRL, SD1_DLL_TESTMODE, 1, 1) + FIELD(SD1_DLL_CTRL, SD1_DLL_LOCK, 0, 1) +REG32(SD1_CDN_CTRL, 0x4cc) + FIELD(SD1_CDN_CTRL, SD1_CDN_CTRL, 0, 1) +REG32(SD1_DLL_TEST, 0x4d0) + FIELD(SD1_DLL_TEST, DLL_DIV, 16, 8) + FIELD(SD1_DLL_TEST, DLL_TX_SEL, 9, 7) + FIELD(SD1_DLL_TEST, DLL_RX_SEL, 0, 9) +REG32(SD1_RX_TUNING_SEL, 0x4d4) + FIELD(SD1_RX_TUNING_SEL, SD1_RX_SEL, 0, 9) +REG32(SD1_DLL_DIV_MAP0, 0x4d8) + FIELD(SD1_DLL_DIV_MAP0, DIV_3, 24, 8) + FIELD(SD1_DLL_DIV_MAP0, DIV_2, 16, 8) + FIELD(SD1_DLL_DIV_MAP0, DIV_1, 8, 8) + FIELD(SD1_DLL_DIV_MAP0, DIV_0, 0, 8) +REG32(SD1_DLL_DIV_MAP1, 0x4dc) + FIELD(SD1_DLL_DIV_MAP1, DIV_7, 24, 8) + FIELD(SD1_DLL_DIV_MAP1, DIV_6, 16, 8) + FIELD(SD1_DLL_DIV_MAP1, DIV_5, 8, 8) + FIELD(SD1_DLL_DIV_MAP1, DIV_4, 0, 8) +REG32(SD1_IOU_COHERENT_CTRL, 0x4e0) + FIELD(SD1_IOU_COHERENT_CTRL, SD1_AXI_COH, 0, 4) +REG32(SD1_IOU_INTERCONNECT_ROUTE, 0x4e4) + FIELD(SD1_IOU_INTERCONNECT_ROUTE, SD1, 0, 1) +REG32(SD1_IOU_RAM, 0x4e8) + FIELD(SD1_IOU_RAM, EMASA0, 6, 1) + FIELD(SD1_IOU_RAM, EMAB0, 3, 3) + FIELD(SD1_IOU_RAM, EMAA0, 0, 3) +REG32(SD1_IOU_INTERCONNECT_QOS, 0x4ec) + FIELD(SD1_IOU_INTERCONNECT_QOS, SD1_QOS, 0, 4) +REG32(OSPI_QSPI_IOU_AXI_MUX_SEL, 0x504) + FIELD(OSPI_QSPI_IOU_AXI_MUX_SEL, OSPI_MUX_SEL, 1, 1) + FIELD(OSPI_QSPI_IOU_AXI_MUX_SEL, QSPI_OSPI_MUX_SEL, 0, 1) +REG32(QSPI_IOU_COHERENT_CTRL, 0x508) + FIELD(QSPI_IOU_COHERENT_CTRL, QSPI_AXI_COH, 0, 4) +REG32(QSPI_IOU_INTERCONNECT_ROUTE, 0x50c) + FIELD(QSPI_IOU_INTERCONNECT_ROUTE, QSPI, 0, 1) +REG32(QSPI_IOU_RAM, 0x510) + FIELD(QSPI_IOU_RAM, EMASA1, 13, 1) + FIELD(QSPI_IOU_RAM, EMAB1, 10, 3) + FIELD(QSPI_IOU_RAM, EMAA1, 7, 3) + FIELD(QSPI_IOU_RAM, EMASA0, 6, 1) + FIELD(QSPI_IOU_RAM, EMAB0, 3, 3) + FIELD(QSPI_IOU_RAM, EMAA0, 0, 3) +REG32(QSPI_IOU_INTERCONNECT_QOS, 0x514) + FIELD(QSPI_IOU_INTERCONNECT_QOS, QSPI_QOS, 0, 4) +REG32(OSPI_IOU_COHERENT_CTRL, 0x530) + FIELD(OSPI_IOU_COHERENT_CTRL, OSPI_AXI_COH, 0, 4) +REG32(OSPI_IOU_INTERCONNECT_ROUTE, 0x534) + FIELD(OSPI_IOU_INTERCONNECT_ROUTE, OSPI, 0, 1) +REG32(OSPI_IOU_RAM, 0x538) + FIELD(OSPI_IOU_RAM, EMAS0, 5, 1) + FIELD(OSPI_IOU_RAM, EMAW0, 3, 2) + FIELD(OSPI_IOU_RAM, EMA0, 0, 3) +REG32(OSPI_IOU_INTERCONNECT_QOS, 0x53c) + FIELD(OSPI_IOU_INTERCONNECT_QOS, OSPI_QOS, 0, 4) +REG32(OSPI_REFCLK_DLY_CTRL, 0x540) + FIELD(OSPI_REFCLK_DLY_CTRL, DLY1, 3, 2) + FIELD(OSPI_REFCLK_DLY_CTRL, DLY0, 0, 3) +REG32(CUR_PWR_ST, 0x600) + FIELD(CUR_PWR_ST, U2PMU, 0, 2) +REG32(CONNECT_ST, 0x604) + FIELD(CONNECT_ST, U2PMU, 0, 1) +REG32(PW_STATE_REQ, 0x608) + FIELD(PW_STATE_REQ, BIT_1_0, 0, 2) +REG32(HOST_U2_PORT_DISABLE, 0x60c) + FIELD(HOST_U2_PORT_DISABLE, BIT_0, 0, 1) +REG32(DBG_U2PMU, 0x610) +REG32(DBG_U2PMU_EXT1, 0x614) +REG32(DBG_U2PMU_EXT2, 0x618) + FIELD(DBG_U2PMU_EXT2, BIT_67_64, 0, 4) +REG32(PME_GEN_U2PMU, 0x61c) + FIELD(PME_GEN_U2PMU, BIT_0, 0, 1) +REG32(PWR_CONFIG_USB2, 0x620) + FIELD(PWR_CONFIG_USB2, STRAP, 0, 30) +REG32(PHY_HUB, 0x624) + FIELD(PHY_HUB, VBUS_CTRL, 1, 1) + FIELD(PHY_HUB, OVER_CURRENT, 0, 1) +REG32(CTRL, 0x700) + FIELD(CTRL, SLVERR_ENABLE, 0, 1) +REG32(ISR, 0x800) + FIELD(ISR, ADDR_DECODE_ERR, 0, 1) +REG32(IMR, 0x804) + FIELD(IMR, ADDR_DECODE_ERR, 0, 1) +REG32(IER, 0x808) + FIELD(IER, ADDR_DECODE_ERR, 0, 1) +REG32(IDR, 0x80c) + FIELD(IDR, ADDR_DECODE_ERR, 0, 1) +REG32(ITR, 0x810) + FIELD(ITR, ADDR_DECODE_ERR, 0, 1) +REG32(PARITY_ISR, 0x814) + FIELD(PARITY_ISR, PERR_AXI_SD1_IOU, 12, 1) + FIELD(PARITY_ISR, PERR_AXI_SD0_IOU, 11, 1) + FIELD(PARITY_ISR, PERR_AXI_QSPI_IOU, 10, 1) + FIELD(PARITY_ISR, PERR_AXI_OSPI_IOU, 9, 1) + FIELD(PARITY_ISR, PERR_IOU_SD1, 8, 1) + FIELD(PARITY_ISR, PERR_IOU_SD0, 7, 1) + FIELD(PARITY_ISR, PERR_IOU_QSPI1, 6, 1) + FIELD(PARITY_ISR, PERR_IOUSLCR_SECURE_APB, 5, 1) + FIELD(PARITY_ISR, PERR_IOUSLCR_APB, 4, 1) + FIELD(PARITY_ISR, PERR_QSPI0_APB, 3, 1) + FIELD(PARITY_ISR, PERR_OSPI_APB, 2, 1) + FIELD(PARITY_ISR, PERR_I2C_APB, 1, 1) + FIELD(PARITY_ISR, PERR_GPIO_APB, 0, 1) +REG32(PARITY_IMR, 0x818) + FIELD(PARITY_IMR, PERR_AXI_SD1_IOU, 12, 1) + FIELD(PARITY_IMR, PERR_AXI_SD0_IOU, 11, 1) + FIELD(PARITY_IMR, PERR_AXI_QSPI_IOU, 10, 1) + FIELD(PARITY_IMR, PERR_AXI_OSPI_IOU, 9, 1) + FIELD(PARITY_IMR, PERR_IOU_SD1, 8, 1) + FIELD(PARITY_IMR, PERR_IOU_SD0, 7, 1) + FIELD(PARITY_IMR, PERR_IOU_QSPI1, 6, 1) + FIELD(PARITY_IMR, PERR_IOUSLCR_SECURE_APB, 5, 1) + FIELD(PARITY_IMR, PERR_IOUSLCR_APB, 4, 1) + FIELD(PARITY_IMR, PERR_QSPI0_APB, 3, 1) + FIELD(PARITY_IMR, PERR_OSPI_APB, 2, 1) + FIELD(PARITY_IMR, PERR_I2C_APB, 1, 1) + FIELD(PARITY_IMR, PERR_GPIO_APB, 0, 1) +REG32(PARITY_IER, 0x81c) + FIELD(PARITY_IER, PERR_AXI_SD1_IOU, 12, 1) + FIELD(PARITY_IER, PERR_AXI_SD0_IOU, 11, 1) + FIELD(PARITY_IER, PERR_AXI_QSPI_IOU, 10, 1) + FIELD(PARITY_IER, PERR_AXI_OSPI_IOU, 9, 1) + FIELD(PARITY_IER, PERR_IOU_SD1, 8, 1) + FIELD(PARITY_IER, PERR_IOU_SD0, 7, 1) + FIELD(PARITY_IER, PERR_IOU_QSPI1, 6, 1) + FIELD(PARITY_IER, PERR_IOUSLCR_SECURE_APB, 5, 1) + FIELD(PARITY_IER, PERR_IOUSLCR_APB, 4, 1) + FIELD(PARITY_IER, PERR_QSPI0_APB, 3, 1) + FIELD(PARITY_IER, PERR_OSPI_APB, 2, 1) + FIELD(PARITY_IER, PERR_I2C_APB, 1, 1) + FIELD(PARITY_IER, PERR_GPIO_APB, 0, 1) +REG32(PARITY_IDR, 0x820) + FIELD(PARITY_IDR, PERR_AXI_SD1_IOU, 12, 1) + FIELD(PARITY_IDR, PERR_AXI_SD0_IOU, 11, 1) + FIELD(PARITY_IDR, PERR_AXI_QSPI_IOU, 10, 1) + FIELD(PARITY_IDR, PERR_AXI_OSPI_IOU, 9, 1) + FIELD(PARITY_IDR, PERR_IOU_SD1, 8, 1) + FIELD(PARITY_IDR, PERR_IOU_SD0, 7, 1) + FIELD(PARITY_IDR, PERR_IOU_QSPI1, 6, 1) + FIELD(PARITY_IDR, PERR_IOUSLCR_SECURE_APB, 5, 1) + FIELD(PARITY_IDR, PERR_IOUSLCR_APB, 4, 1) + FIELD(PARITY_IDR, PERR_QSPI0_APB, 3, 1) + FIELD(PARITY_IDR, PERR_OSPI_APB, 2, 1) + FIELD(PARITY_IDR, PERR_I2C_APB, 1, 1) + FIELD(PARITY_IDR, PERR_GPIO_APB, 0, 1) +REG32(PARITY_ITR, 0x824) + FIELD(PARITY_ITR, PERR_AXI_SD1_IOU, 12, 1) + FIELD(PARITY_ITR, PERR_AXI_SD0_IOU, 11, 1) + FIELD(PARITY_ITR, PERR_AXI_QSPI_IOU, 10, 1) + FIELD(PARITY_ITR, PERR_AXI_OSPI_IOU, 9, 1) + FIELD(PARITY_ITR, PERR_IOU_SD1, 8, 1) + FIELD(PARITY_ITR, PERR_IOU_SD0, 7, 1) + FIELD(PARITY_ITR, PERR_IOU_QSPI1, 6, 1) + FIELD(PARITY_ITR, PERR_IOUSLCR_SECURE_APB, 5, 1) + FIELD(PARITY_ITR, PERR_IOUSLCR_APB, 4, 1) + FIELD(PARITY_ITR, PERR_QSPI0_APB, 3, 1) + FIELD(PARITY_ITR, PERR_OSPI_APB, 2, 1) + FIELD(PARITY_ITR, PERR_I2C_APB, 1, 1) + FIELD(PARITY_ITR, PERR_GPIO_APB, 0, 1) +REG32(WPROT0, 0x828) + FIELD(WPROT0, ACTIVE, 0, 1) + +static void parity_imr_update_irq(XlnxVersalPmcIouSlcr *s) +{ + bool pending =3D s->regs[R_PARITY_ISR] & ~s->regs[R_PARITY_IMR]; + qemu_set_irq(s->irq_parity_imr, pending); +} + +static void parity_isr_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s =3D XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + parity_imr_update_irq(s); +} + +static uint64_t parity_ier_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s =3D XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_PARITY_IMR] &=3D ~val; + parity_imr_update_irq(s); + return 0; +} + +static uint64_t parity_idr_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s =3D XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_PARITY_IMR] |=3D val; + parity_imr_update_irq(s); + return 0; +} + +static uint64_t parity_itr_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s =3D XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_PARITY_ISR] |=3D val; + parity_imr_update_irq(s); + return 0; +} + +static void imr_update_irq(XlnxVersalPmcIouSlcr *s) +{ + bool pending =3D s->regs[R_ISR] & ~s->regs[R_IMR]; + qemu_set_irq(s->irq_imr, pending); +} + +static void isr_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s =3D XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + imr_update_irq(s); +} + +static uint64_t ier_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s =3D XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_IMR] &=3D ~val; + imr_update_irq(s); + return 0; +} + +static uint64_t idr_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s =3D XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_IMR] |=3D val; + imr_update_irq(s); + return 0; +} + +static uint64_t itr_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s =3D XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_ISR] |=3D val; + imr_update_irq(s); + return 0; +} + +static uint64_t sd0_ctrl_reg_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s =3D XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + uint32_t prev =3D ARRAY_FIELD_EX32(s->regs, SD0_CTRL_REG, SD0_EMMC_SEL= ); + + if (prev !=3D (val64 & R_SD0_CTRL_REG_SD0_EMMC_SEL_MASK)) { + qemu_set_irq(s->sd_emmc_sel[0], !!val64); + } + + return val64; +} + +static uint64_t sd1_ctrl_reg_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s =3D XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + uint32_t prev =3D ARRAY_FIELD_EX32(s->regs, SD1_CTRL_REG, SD1_EMMC_SEL= ); + + if (prev !=3D (val64 & R_SD1_CTRL_REG_SD1_EMMC_SEL_MASK)) { + qemu_set_irq(s->sd_emmc_sel[1], !!val64); + } + + return val64; +} + +static uint64_t ospi_qspi_iou_axi_mux_sel_prew(RegisterInfo *reg, + uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s =3D XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + uint32_t val32 =3D (uint32_t) val64; + uint8_t ospi_mux_sel =3D FIELD_EX32(val32, OSPI_QSPI_IOU_AXI_MUX_SEL, + OSPI_MUX_SEL); + uint8_t qspi_ospi_mux_sel =3D FIELD_EX32(val32, OSPI_QSPI_IOU_AXI_MUX_= SEL, + QSPI_OSPI_MUX_SEL); + + if (ospi_mux_sel !=3D + ARRAY_FIELD_EX32(s->regs, OSPI_QSPI_IOU_AXI_MUX_SEL, OSPI_MUX_SEL)= ) { + qemu_set_irq(s->ospi_mux_sel, !!ospi_mux_sel); + } + + if (qspi_ospi_mux_sel !=3D + ARRAY_FIELD_EX32(s->regs, OSPI_QSPI_IOU_AXI_MUX_SEL, + QSPI_OSPI_MUX_SEL)) { + qemu_set_irq(s->qspi_ospi_mux_sel, !!qspi_ospi_mux_sel); + } + + return val64; +} + +static RegisterAccessInfo pmc_iou_slcr_regs_info[] =3D { + { .name =3D "MIO_PIN_0", .addr =3D A_MIO_PIN_0, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_1", .addr =3D A_MIO_PIN_1, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_2", .addr =3D A_MIO_PIN_2, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_3", .addr =3D A_MIO_PIN_3, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_4", .addr =3D A_MIO_PIN_4, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_5", .addr =3D A_MIO_PIN_5, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_6", .addr =3D A_MIO_PIN_6, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_7", .addr =3D A_MIO_PIN_7, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_8", .addr =3D A_MIO_PIN_8, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_9", .addr =3D A_MIO_PIN_9, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_10", .addr =3D A_MIO_PIN_10, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_11", .addr =3D A_MIO_PIN_11, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_12", .addr =3D A_MIO_PIN_12, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_13", .addr =3D A_MIO_PIN_13, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_14", .addr =3D A_MIO_PIN_14, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_15", .addr =3D A_MIO_PIN_15, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_16", .addr =3D A_MIO_PIN_16, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_17", .addr =3D A_MIO_PIN_17, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_18", .addr =3D A_MIO_PIN_18, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_19", .addr =3D A_MIO_PIN_19, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_20", .addr =3D A_MIO_PIN_20, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_21", .addr =3D A_MIO_PIN_21, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_22", .addr =3D A_MIO_PIN_22, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_23", .addr =3D A_MIO_PIN_23, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_24", .addr =3D A_MIO_PIN_24, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_25", .addr =3D A_MIO_PIN_25, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_26", .addr =3D A_MIO_PIN_26, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_27", .addr =3D A_MIO_PIN_27, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_28", .addr =3D A_MIO_PIN_28, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_29", .addr =3D A_MIO_PIN_29, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_30", .addr =3D A_MIO_PIN_30, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_31", .addr =3D A_MIO_PIN_31, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_32", .addr =3D A_MIO_PIN_32, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_33", .addr =3D A_MIO_PIN_33, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_34", .addr =3D A_MIO_PIN_34, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_35", .addr =3D A_MIO_PIN_35, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_36", .addr =3D A_MIO_PIN_36, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_37", .addr =3D A_MIO_PIN_37, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_38", .addr =3D A_MIO_PIN_38, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_39", .addr =3D A_MIO_PIN_39, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_40", .addr =3D A_MIO_PIN_40, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_41", .addr =3D A_MIO_PIN_41, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_42", .addr =3D A_MIO_PIN_42, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_43", .addr =3D A_MIO_PIN_43, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_44", .addr =3D A_MIO_PIN_44, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_45", .addr =3D A_MIO_PIN_45, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_46", .addr =3D A_MIO_PIN_46, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_47", .addr =3D A_MIO_PIN_47, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_48", .addr =3D A_MIO_PIN_48, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_49", .addr =3D A_MIO_PIN_49, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_50", .addr =3D A_MIO_PIN_50, + .rsvd =3D 0xfffffc01, + },{ .name =3D "MIO_PIN_51", .addr =3D A_MIO_PIN_51, + .rsvd =3D 0xfffffc01, + },{ .name =3D "BNK0_EN_RX", .addr =3D A_BNK0_EN_RX, + .reset =3D 0x3ffffff, + .rsvd =3D 0xfc000000, + },{ .name =3D "BNK0_SEL_RX0", .addr =3D A_BNK0_SEL_RX0, + .reset =3D 0xffffffff, + },{ .name =3D "BNK0_SEL_RX1", .addr =3D A_BNK0_SEL_RX1, + .reset =3D 0xfffff, + .rsvd =3D 0xfff00000, + },{ .name =3D "BNK0_EN_RX_SCHMITT_HYST", .addr =3D A_BNK0_EN_RX_SCHMI= TT_HYST, + .rsvd =3D 0xfc000000, + },{ .name =3D "BNK0_EN_WK_PD", .addr =3D A_BNK0_EN_WK_PD, + .rsvd =3D 0xfc000000, + },{ .name =3D "BNK0_EN_WK_PU", .addr =3D A_BNK0_EN_WK_PU, + .reset =3D 0x3ffffff, + .rsvd =3D 0xfc000000, + },{ .name =3D "BNK0_SEL_DRV0", .addr =3D A_BNK0_SEL_DRV0, + .reset =3D 0xffffffff, + },{ .name =3D "BNK0_SEL_DRV1", .addr =3D A_BNK0_SEL_DRV1, + .reset =3D 0xfffff, + .rsvd =3D 0xfff00000, + },{ .name =3D "BNK0_SEL_SLEW", .addr =3D A_BNK0_SEL_SLEW, + .rsvd =3D 0xfc000000, + },{ .name =3D "BNK0_EN_DFT_OPT_INV", .addr =3D A_BNK0_EN_DFT_OPT_INV, + .rsvd =3D 0xfc000000, + },{ .name =3D "BNK0_EN_PAD2PAD_LOOPBACK", + .addr =3D A_BNK0_EN_PAD2PAD_LOOPBACK, + .rsvd =3D 0xffffe000, + },{ .name =3D "BNK0_RX_SPARE0", .addr =3D A_BNK0_RX_SPARE0, + },{ .name =3D "BNK0_RX_SPARE1", .addr =3D A_BNK0_RX_SPARE1, + .rsvd =3D 0xfff00000, + },{ .name =3D "BNK0_TX_SPARE0", .addr =3D A_BNK0_TX_SPARE0, + },{ .name =3D "BNK0_TX_SPARE1", .addr =3D A_BNK0_TX_SPARE1, + .rsvd =3D 0xfff00000, + },{ .name =3D "BNK0_SEL_EN1P8", .addr =3D A_BNK0_SEL_EN1P8, + .rsvd =3D 0xfffffffe, + },{ .name =3D "BNK0_EN_B_POR_DETECT", .addr =3D A_BNK0_EN_B_POR_DETEC= T, + .rsvd =3D 0xfffffffe, + },{ .name =3D "BNK0_LPF_BYP_POR_DETECT", .addr =3D A_BNK0_LPF_BYP_POR= _DETECT, + .reset =3D 0x1, + .rsvd =3D 0xfffffffe, + },{ .name =3D "BNK0_EN_LATCH", .addr =3D A_BNK0_EN_LATCH, + .rsvd =3D 0xfffffffe, + },{ .name =3D "BNK0_VBG_LPF_BYP_B", .addr =3D A_BNK0_VBG_LPF_BYP_B, + .reset =3D 0x1, + .rsvd =3D 0xfffffffe, + },{ .name =3D "BNK0_EN_AMP_B", .addr =3D A_BNK0_EN_AMP_B, + .rsvd =3D 0xfffffffc, + },{ .name =3D "BNK0_SPARE_BIAS", .addr =3D A_BNK0_SPARE_BIAS, + .rsvd =3D 0xfffffff0, + },{ .name =3D "BNK0_DRIVER_BIAS", .addr =3D A_BNK0_DRIVER_BIAS, + .rsvd =3D 0xffff8000, + },{ .name =3D "BNK0_VMODE", .addr =3D A_BNK0_VMODE, + .rsvd =3D 0xfffffffe, + .ro =3D 0x1, + },{ .name =3D "BNK0_SEL_AUX_IO_RX", .addr =3D A_BNK0_SEL_AUX_IO_RX, + .rsvd =3D 0xfc000000, + },{ .name =3D "BNK0_EN_TX_HS_MODE", .addr =3D A_BNK0_EN_TX_HS_MODE, + .rsvd =3D 0xfc000000, + },{ .name =3D "MIO_MST_TRI0", .addr =3D A_MIO_MST_TRI0, + .reset =3D 0x3ffffff, + .rsvd =3D 0xfc000000, + },{ .name =3D "MIO_MST_TRI1", .addr =3D A_MIO_MST_TRI1, + .reset =3D 0x3ffffff, + .rsvd =3D 0xfc000000, + },{ .name =3D "BNK1_EN_RX", .addr =3D A_BNK1_EN_RX, + .reset =3D 0x3ffffff, + .rsvd =3D 0xfc000000, + },{ .name =3D "BNK1_SEL_RX0", .addr =3D A_BNK1_SEL_RX0, + .reset =3D 0xffffffff, + },{ .name =3D "BNK1_SEL_RX1", .addr =3D A_BNK1_SEL_RX1, + .reset =3D 0xfffff, + .rsvd =3D 0xfff00000, + },{ .name =3D "BNK1_EN_RX_SCHMITT_HYST", .addr =3D A_BNK1_EN_RX_SCHMI= TT_HYST, + .rsvd =3D 0xfc000000, + },{ .name =3D "BNK1_EN_WK_PD", .addr =3D A_BNK1_EN_WK_PD, + .rsvd =3D 0xfc000000, + },{ .name =3D "BNK1_EN_WK_PU", .addr =3D A_BNK1_EN_WK_PU, + .reset =3D 0x3ffffff, + .rsvd =3D 0xfc000000, + },{ .name =3D "BNK1_SEL_DRV0", .addr =3D A_BNK1_SEL_DRV0, + .reset =3D 0xffffffff, + },{ .name =3D "BNK1_SEL_DRV1", .addr =3D A_BNK1_SEL_DRV1, + .reset =3D 0xfffff, + .rsvd =3D 0xfff00000, + },{ .name =3D "BNK1_SEL_SLEW", .addr =3D A_BNK1_SEL_SLEW, + .rsvd =3D 0xfc000000, + },{ .name =3D "BNK1_EN_DFT_OPT_INV", .addr =3D A_BNK1_EN_DFT_OPT_INV, + .rsvd =3D 0xfc000000, + },{ .name =3D "BNK1_EN_PAD2PAD_LOOPBACK", + .addr =3D A_BNK1_EN_PAD2PAD_LOOPBACK, + .rsvd =3D 0xffffe000, + },{ .name =3D "BNK1_RX_SPARE0", .addr =3D A_BNK1_RX_SPARE0, + },{ .name =3D "BNK1_RX_SPARE1", .addr =3D A_BNK1_RX_SPARE1, + .rsvd =3D 0xfff00000, + },{ .name =3D "BNK1_TX_SPARE0", .addr =3D A_BNK1_TX_SPARE0, + },{ .name =3D "BNK1_TX_SPARE1", .addr =3D A_BNK1_TX_SPARE1, + .rsvd =3D 0xfff00000, + },{ .name =3D "BNK1_SEL_EN1P8", .addr =3D A_BNK1_SEL_EN1P8, + .rsvd =3D 0xfffffffe, + },{ .name =3D "BNK1_EN_B_POR_DETECT", .addr =3D A_BNK1_EN_B_POR_DETEC= T, + .rsvd =3D 0xfffffffe, + },{ .name =3D "BNK1_LPF_BYP_POR_DETECT", .addr =3D A_BNK1_LPF_BYP_POR= _DETECT, + .reset =3D 0x1, + .rsvd =3D 0xfffffffe, + },{ .name =3D "BNK1_EN_LATCH", .addr =3D A_BNK1_EN_LATCH, + .rsvd =3D 0xfffffffe, + },{ .name =3D "BNK1_VBG_LPF_BYP_B", .addr =3D A_BNK1_VBG_LPF_BYP_B, + .reset =3D 0x1, + .rsvd =3D 0xfffffffe, + },{ .name =3D "BNK1_EN_AMP_B", .addr =3D A_BNK1_EN_AMP_B, + .rsvd =3D 0xfffffffc, + },{ .name =3D "BNK1_SPARE_BIAS", .addr =3D A_BNK1_SPARE_BIAS, + .rsvd =3D 0xfffffff0, + },{ .name =3D "BNK1_DRIVER_BIAS", .addr =3D A_BNK1_DRIVER_BIAS, + .rsvd =3D 0xffff8000, + },{ .name =3D "BNK1_VMODE", .addr =3D A_BNK1_VMODE, + .rsvd =3D 0xfffffffe, + .ro =3D 0x1, + },{ .name =3D "BNK1_SEL_AUX_IO_RX", .addr =3D A_BNK1_SEL_AUX_IO_RX, + .rsvd =3D 0xfc000000, + },{ .name =3D "BNK1_EN_TX_HS_MODE", .addr =3D A_BNK1_EN_TX_HS_MODE, + .rsvd =3D 0xfc000000, + },{ .name =3D "SD0_CLK_CTRL", .addr =3D A_SD0_CLK_CTRL, + .rsvd =3D 0xfffffff8, + },{ .name =3D "SD0_CTRL_REG", .addr =3D A_SD0_CTRL_REG, + .rsvd =3D 0xfffffffe, + .pre_write =3D sd0_ctrl_reg_prew, + },{ .name =3D "SD0_CONFIG_REG1", .addr =3D A_SD0_CONFIG_REG1, + .reset =3D 0x3250, + .rsvd =3D 0xffff8000, + },{ .name =3D "SD0_CONFIG_REG2", .addr =3D A_SD0_CONFIG_REG2, + .reset =3D 0xffc, + .rsvd =3D 0xffffc000, + },{ .name =3D "SD0_CONFIG_REG3", .addr =3D A_SD0_CONFIG_REG3, + .reset =3D 0x407, + .rsvd =3D 0xfffff800, + },{ .name =3D "SD0_INITPRESET", .addr =3D A_SD0_INITPRESET, + .reset =3D 0x100, + .rsvd =3D 0xffffe000, + },{ .name =3D "SD0_DSPPRESET", .addr =3D A_SD0_DSPPRESET, + .reset =3D 0x4, + .rsvd =3D 0xffffe000, + },{ .name =3D "SD0_HSPDPRESET", .addr =3D A_SD0_HSPDPRESET, + .reset =3D 0x2, + .rsvd =3D 0xffffe000, + },{ .name =3D "SD0_SDR12PRESET", .addr =3D A_SD0_SDR12PRESET, + .reset =3D 0x4, + .rsvd =3D 0xffffe000, + },{ .name =3D "SD0_SDR25PRESET", .addr =3D A_SD0_SDR25PRESET, + .reset =3D 0x2, + .rsvd =3D 0xffffe000, + },{ .name =3D "SD0_SDR50PRSET", .addr =3D A_SD0_SDR50PRSET, + .reset =3D 0x1, + .rsvd =3D 0xffffe000, + },{ .name =3D "SD0_SDR104PRST", .addr =3D A_SD0_SDR104PRST, + .rsvd =3D 0xffffe000, + },{ .name =3D "SD0_DDR50PRESET", .addr =3D A_SD0_DDR50PRESET, + .reset =3D 0x2, + .rsvd =3D 0xffffe000, + },{ .name =3D "SD0_MAXCUR1P8", .addr =3D A_SD0_MAXCUR1P8, + .rsvd =3D 0xffffff00, + },{ .name =3D "SD0_MAXCUR3P0", .addr =3D A_SD0_MAXCUR3P0, + .rsvd =3D 0xffffff00, + },{ .name =3D "SD0_MAXCUR3P3", .addr =3D A_SD0_MAXCUR3P3, + .rsvd =3D 0xffffff00, + },{ .name =3D "SD0_DLL_CTRL", .addr =3D A_SD0_DLL_CTRL, + .reset =3D 0x1, + .rsvd =3D 0xfffffc00, + .ro =3D 0x19, + },{ .name =3D "SD0_CDN_CTRL", .addr =3D A_SD0_CDN_CTRL, + .rsvd =3D 0xfffffffe, + },{ .name =3D "SD0_DLL_TEST", .addr =3D A_SD0_DLL_TEST, + .rsvd =3D 0xff000000, + },{ .name =3D "SD0_RX_TUNING_SEL", .addr =3D A_SD0_RX_TUNING_SEL, + .rsvd =3D 0xfffffe00, + .ro =3D 0x1ff, + },{ .name =3D "SD0_DLL_DIV_MAP0", .addr =3D A_SD0_DLL_DIV_MAP0, + .reset =3D 0x50505050, + },{ .name =3D "SD0_DLL_DIV_MAP1", .addr =3D A_SD0_DLL_DIV_MAP1, + .reset =3D 0x50505050, + },{ .name =3D "SD0_IOU_COHERENT_CTRL", .addr =3D A_SD0_IOU_COHERENT_C= TRL, + .rsvd =3D 0xfffffff0, + },{ .name =3D "SD0_IOU_INTERCONNECT_ROUTE", + .addr =3D A_SD0_IOU_INTERCONNECT_ROUTE, + .rsvd =3D 0xfffffffe, + },{ .name =3D "SD0_IOU_RAM", .addr =3D A_SD0_IOU_RAM, + .reset =3D 0x24, + .rsvd =3D 0xffffff80, + },{ .name =3D "SD0_IOU_INTERCONNECT_QOS", + .addr =3D A_SD0_IOU_INTERCONNECT_QOS, + .rsvd =3D 0xfffffff0, + },{ .name =3D "SD1_CLK_CTRL", .addr =3D A_SD1_CLK_CTRL, + .rsvd =3D 0xfffffffc, + },{ .name =3D "SD1_CTRL_REG", .addr =3D A_SD1_CTRL_REG, + .rsvd =3D 0xfffffffe, + .pre_write =3D sd1_ctrl_reg_prew, + },{ .name =3D "SD1_CONFIG_REG1", .addr =3D A_SD1_CONFIG_REG1, + .reset =3D 0x3250, + .rsvd =3D 0xffff8000, + },{ .name =3D "SD1_CONFIG_REG2", .addr =3D A_SD1_CONFIG_REG2, + .reset =3D 0xffc, + .rsvd =3D 0xffffc000, + },{ .name =3D "SD1_CONFIG_REG3", .addr =3D A_SD1_CONFIG_REG3, + .reset =3D 0x407, + .rsvd =3D 0xfffff800, + },{ .name =3D "SD1_INITPRESET", .addr =3D A_SD1_INITPRESET, + .reset =3D 0x100, + .rsvd =3D 0xffffe000, + },{ .name =3D "SD1_DSPPRESET", .addr =3D A_SD1_DSPPRESET, + .reset =3D 0x4, + .rsvd =3D 0xffffe000, + },{ .name =3D "SD1_HSPDPRESET", .addr =3D A_SD1_HSPDPRESET, + .reset =3D 0x2, + .rsvd =3D 0xffffe000, + },{ .name =3D "SD1_SDR12PRESET", .addr =3D A_SD1_SDR12PRESET, + .reset =3D 0x4, + .rsvd =3D 0xffffe000, + },{ .name =3D "SD1_SDR25PRESET", .addr =3D A_SD1_SDR25PRESET, + .reset =3D 0x2, + .rsvd =3D 0xffffe000, + },{ .name =3D "SD1_SDR50PRSET", .addr =3D A_SD1_SDR50PRSET, + .reset =3D 0x1, + .rsvd =3D 0xffffe000, + },{ .name =3D "SD1_SDR104PRST", .addr =3D A_SD1_SDR104PRST, + .rsvd =3D 0xffffe000, + },{ .name =3D "SD1_DDR50PRESET", .addr =3D A_SD1_DDR50PRESET, + .reset =3D 0x2, + .rsvd =3D 0xffffe000, + },{ .name =3D "SD1_MAXCUR1P8", .addr =3D A_SD1_MAXCUR1P8, + .rsvd =3D 0xffffff00, + },{ .name =3D "SD1_MAXCUR3P0", .addr =3D A_SD1_MAXCUR3P0, + .rsvd =3D 0xffffff00, + },{ .name =3D "SD1_MAXCUR3P3", .addr =3D A_SD1_MAXCUR3P3, + .rsvd =3D 0xffffff00, + },{ .name =3D "SD1_DLL_CTRL", .addr =3D A_SD1_DLL_CTRL, + .reset =3D 0x1, + .rsvd =3D 0xfffffc00, + .ro =3D 0x19, + },{ .name =3D "SD1_CDN_CTRL", .addr =3D A_SD1_CDN_CTRL, + .rsvd =3D 0xfffffffe, + },{ .name =3D "SD1_DLL_TEST", .addr =3D A_SD1_DLL_TEST, + .rsvd =3D 0xff000000, + },{ .name =3D "SD1_RX_TUNING_SEL", .addr =3D A_SD1_RX_TUNING_SEL, + .rsvd =3D 0xfffffe00, + .ro =3D 0x1ff, + },{ .name =3D "SD1_DLL_DIV_MAP0", .addr =3D A_SD1_DLL_DIV_MAP0, + .reset =3D 0x50505050, + },{ .name =3D "SD1_DLL_DIV_MAP1", .addr =3D A_SD1_DLL_DIV_MAP1, + .reset =3D 0x50505050, + },{ .name =3D "SD1_IOU_COHERENT_CTRL", .addr =3D A_SD1_IOU_COHERENT_C= TRL, + .rsvd =3D 0xfffffff0, + },{ .name =3D "SD1_IOU_INTERCONNECT_ROUTE", + .addr =3D A_SD1_IOU_INTERCONNECT_ROUTE, + .rsvd =3D 0xfffffffe, + },{ .name =3D "SD1_IOU_RAM", .addr =3D A_SD1_IOU_RAM, + .reset =3D 0x24, + .rsvd =3D 0xffffff80, + },{ .name =3D "SD1_IOU_INTERCONNECT_QOS", + .addr =3D A_SD1_IOU_INTERCONNECT_QOS, + .rsvd =3D 0xfffffff0, + },{ .name =3D "OSPI_QSPI_IOU_AXI_MUX_SEL", + .addr =3D A_OSPI_QSPI_IOU_AXI_MUX_SEL, + .reset =3D 0x1, + .rsvd =3D 0xfffffffc, + .pre_write =3D ospi_qspi_iou_axi_mux_sel_prew, + },{ .name =3D "QSPI_IOU_COHERENT_CTRL", .addr =3D A_QSPI_IOU_COHERENT= _CTRL, + .rsvd =3D 0xfffffff0, + },{ .name =3D "QSPI_IOU_INTERCONNECT_ROUTE", + .addr =3D A_QSPI_IOU_INTERCONNECT_ROUTE, + .rsvd =3D 0xfffffffe, + },{ .name =3D "QSPI_IOU_RAM", .addr =3D A_QSPI_IOU_RAM, + .reset =3D 0x1224, + .rsvd =3D 0xffffc000, + },{ .name =3D "QSPI_IOU_INTERCONNECT_QOS", + .addr =3D A_QSPI_IOU_INTERCONNECT_QOS, + .rsvd =3D 0xfffffff0, + },{ .name =3D "OSPI_IOU_COHERENT_CTRL", .addr =3D A_OSPI_IOU_COHERENT= _CTRL, + .rsvd =3D 0xfffffff0, + },{ .name =3D "OSPI_IOU_INTERCONNECT_ROUTE", + .addr =3D A_OSPI_IOU_INTERCONNECT_ROUTE, + .rsvd =3D 0xfffffffe, + },{ .name =3D "OSPI_IOU_RAM", .addr =3D A_OSPI_IOU_RAM, + .reset =3D 0xa, + .rsvd =3D 0xffffffc0, + },{ .name =3D "OSPI_IOU_INTERCONNECT_QOS", + .addr =3D A_OSPI_IOU_INTERCONNECT_QOS, + .rsvd =3D 0xfffffff0, + },{ .name =3D "OSPI_REFCLK_DLY_CTRL", .addr =3D A_OSPI_REFCLK_DLY_CTR= L, + .reset =3D 0x13, + .rsvd =3D 0xffffffe0, + },{ .name =3D "CUR_PWR_ST", .addr =3D A_CUR_PWR_ST, + .rsvd =3D 0xfffffffc, + .ro =3D 0x3, + },{ .name =3D "CONNECT_ST", .addr =3D A_CONNECT_ST, + .rsvd =3D 0xfffffffe, + .ro =3D 0x1, + },{ .name =3D "PW_STATE_REQ", .addr =3D A_PW_STATE_REQ, + .rsvd =3D 0xfffffffc, + },{ .name =3D "HOST_U2_PORT_DISABLE", .addr =3D A_HOST_U2_PORT_DISABL= E, + .rsvd =3D 0xfffffffe, + },{ .name =3D "DBG_U2PMU", .addr =3D A_DBG_U2PMU, + .ro =3D 0xffffffff, + },{ .name =3D "DBG_U2PMU_EXT1", .addr =3D A_DBG_U2PMU_EXT1, + .ro =3D 0xffffffff, + },{ .name =3D "DBG_U2PMU_EXT2", .addr =3D A_DBG_U2PMU_EXT2, + .rsvd =3D 0xfffffff0, + .ro =3D 0xf, + },{ .name =3D "PME_GEN_U2PMU", .addr =3D A_PME_GEN_U2PMU, + .rsvd =3D 0xfffffffe, + .ro =3D 0x1, + },{ .name =3D "PWR_CONFIG_USB2", .addr =3D A_PWR_CONFIG_USB2, + .rsvd =3D 0xc0000000, + },{ .name =3D "PHY_HUB", .addr =3D A_PHY_HUB, + .rsvd =3D 0xfffffffc, + .ro =3D 0x2, + },{ .name =3D "CTRL", .addr =3D A_CTRL, + },{ .name =3D "ISR", .addr =3D A_ISR, + .w1c =3D 0x1, + .post_write =3D isr_postw, + },{ .name =3D "IMR", .addr =3D A_IMR, + .reset =3D 0x1, + .ro =3D 0x1, + },{ .name =3D "IER", .addr =3D A_IER, + .pre_write =3D ier_prew, + },{ .name =3D "IDR", .addr =3D A_IDR, + .pre_write =3D idr_prew, + },{ .name =3D "ITR", .addr =3D A_ITR, + .pre_write =3D itr_prew, + },{ .name =3D "PARITY_ISR", .addr =3D A_PARITY_ISR, + .w1c =3D 0x1fff, + .post_write =3D parity_isr_postw, + },{ .name =3D "PARITY_IMR", .addr =3D A_PARITY_IMR, + .reset =3D 0x1fff, + .ro =3D 0x1fff, + },{ .name =3D "PARITY_IER", .addr =3D A_PARITY_IER, + .pre_write =3D parity_ier_prew, + },{ .name =3D "PARITY_IDR", .addr =3D A_PARITY_IDR, + .pre_write =3D parity_idr_prew, + },{ .name =3D "PARITY_ITR", .addr =3D A_PARITY_ITR, + .pre_write =3D parity_itr_prew, + },{ .name =3D "WPROT0", .addr =3D A_WPROT0, + .reset =3D 0x1, + } +}; + +static void xlnx_versal_pmc_iou_slcr_reset_init(Object *obj, ResetType typ= e) +{ + XlnxVersalPmcIouSlcr *s =3D XILINX_VERSAL_PMC_IOU_SLCR(obj); + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(s->regs_info); ++i) { + register_reset(&s->regs_info[i]); + } +} + +static void xlnx_versal_pmc_iou_slcr_reset_hold(Object *obj) +{ + XlnxVersalPmcIouSlcr *s =3D XILINX_VERSAL_PMC_IOU_SLCR(obj); + + parity_imr_update_irq(s); + imr_update_irq(s); + + /* + * Setup OSPI_QSPI mux + * By default axi slave interface is enabled for ospi-dma + */ + qemu_set_irq(s->ospi_mux_sel, 0); + qemu_set_irq(s->qspi_ospi_mux_sel, 1); +} + +static const MemoryRegionOps pmc_iou_slcr_ops =3D { + .read =3D register_read_memory, + .write =3D register_write_memory, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static void xlnx_versal_pmc_iou_slcr_realize(DeviceState *dev, Error **err= p) +{ + XlnxVersalPmcIouSlcr *s =3D XILINX_VERSAL_PMC_IOU_SLCR(dev); + + qdev_init_gpio_out(dev, s->sd_emmc_sel, 2); + qdev_init_gpio_out(dev, &s->qspi_ospi_mux_sel, 1); + qdev_init_gpio_out(dev, &s->ospi_mux_sel, 1); +} + +static void xlnx_versal_pmc_iou_slcr_init(Object *obj) +{ + XlnxVersalPmcIouSlcr *s =3D XILINX_VERSAL_PMC_IOU_SLCR(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + RegisterInfoArray *reg_array; + + memory_region_init(&s->iomem, obj, TYPE_XILINX_VERSAL_PMC_IOU_SLCR, + XILINX_VERSAL_PMC_IOU_SLCR_R_MAX * 4); + reg_array =3D + register_init_block32(DEVICE(obj), pmc_iou_slcr_regs_info, + ARRAY_SIZE(pmc_iou_slcr_regs_info), + s->regs_info, s->regs, + &pmc_iou_slcr_ops, + XILINX_VERSAL_PMC_IOU_SLCR_ERR_DEBUG, + XILINX_VERSAL_PMC_IOU_SLCR_R_MAX * 4); + memory_region_add_subregion(&s->iomem, + 0x0, + ®_array->mem); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq_parity_imr); + sysbus_init_irq(sbd, &s->irq_imr); +} + +static const VMStateDescription vmstate_pmc_iou_slcr =3D { + .name =3D TYPE_XILINX_VERSAL_PMC_IOU_SLCR, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, XlnxVersalPmcIouSlcr, + XILINX_VERSAL_PMC_IOU_SLCR_R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static void xlnx_versal_pmc_iou_slcr_class_init(ObjectClass *klass, void *= data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + dc->realize =3D xlnx_versal_pmc_iou_slcr_realize; + dc->vmsd =3D &vmstate_pmc_iou_slcr; + rc->phases.enter =3D xlnx_versal_pmc_iou_slcr_reset_init; + rc->phases.hold =3D xlnx_versal_pmc_iou_slcr_reset_hold; +} + +static const TypeInfo xlnx_versal_pmc_iou_slcr_info =3D { + .name =3D TYPE_XILINX_VERSAL_PMC_IOU_SLCR, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(XlnxVersalPmcIouSlcr), + .class_init =3D xlnx_versal_pmc_iou_slcr_class_init, + .instance_init =3D xlnx_versal_pmc_iou_slcr_init, +}; + +static void xlnx_versal_pmc_iou_slcr_register_types(void) +{ + type_register_static(&xlnx_versal_pmc_iou_slcr_info); +} + +type_init(xlnx_versal_pmc_iou_slcr_register_types) diff --git a/include/hw/misc/xlnx-versal-pmc-iou-slcr.h b/include/hw/misc/x= lnx-versal-pmc-iou-slcr.h new file mode 100644 index 0000000000..cbb5b5282a --- /dev/null +++ b/include/hw/misc/xlnx-versal-pmc-iou-slcr.h @@ -0,0 +1,51 @@ +/* + * Header file for the Xilinx Versal's PMC IOU SLCR + * + * Copyright (C) 2021 Xilinx Inc + * Written by Edgar E. Iglesias + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef XILINX_VERSAL_PMC_IOU_SLCR_H +#define XILINX_VERSAL_PMC_IOU_SLCR_H + +#include "hw/register.h" + +#define TYPE_XILINX_VERSAL_PMC_IOU_SLCR "xlnx.versal-pmc-iou-slcr" + +#define XILINX_VERSAL_PMC_IOU_SLCR(obj) \ + OBJECT_CHECK(XlnxVersalPmcIouSlcr, (obj), TYPE_XILINX_VERSAL_PMC_IOU_= SLCR) + +#define XILINX_VERSAL_PMC_IOU_SLCR_R_MAX (0x828 / 4 + 1) + +typedef struct XlnxVersalPmcIouSlcr { + SysBusDevice parent_obj; + MemoryRegion iomem; + qemu_irq irq_parity_imr; + qemu_irq irq_imr; + qemu_irq sd_emmc_sel[2]; + qemu_irq qspi_ospi_mux_sel; + qemu_irq ospi_mux_sel; + + uint32_t regs[XILINX_VERSAL_PMC_IOU_SLCR_R_MAX]; + RegisterInfo regs_info[XILINX_VERSAL_PMC_IOU_SLCR_R_MAX]; +} XlnxVersalPmcIouSlcr; + +#endif /* XILINX_VERSAL_PMC_IOU_SLCR_H */ --=20 2.11.0 From nobody Fri Apr 19 16:53:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail(p=none dis=none) header.from=xilinx.com ARC-Seal: i=2; a=rsa-sha256; t=1637664971; cv=pass; d=zohomail.com; s=zohoarc; b=lGsVyVvK0hYgRRol/hi+Cp3wIBndqGMsBNzWj1AyWwwdyVuUjZ97VUdG6Z6qC0TdsmWeSUIMYALYAzSREGf5OGKaj71akbd+NGIMnRvBmdN9TFbPY8eWvriQkHwKymNF4cQq/KvZu9cOIwn5iVyrtdVLuobWbBAuOqGZLCKu3hY= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637664971; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=O6wFSjjFxQiIbqOG6eN7sadsXSsJa3HX/wNFLngggJE=; b=WB5ShCCAdr3+TW9ow0OV/tRgTXzj7Po1egUG2s5dOfN0mIR2TxtpZuA+432fel8aA7eLmt5AnHjEIZtCJiC/s7Kko2DQvOLyUATGSX70PoWZJcM9kdvz2eUqMk+tCQEni8AcUshVFu56qWWUZ1O9IH9nNBDv4/62/x1o4fuFajk= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637664971590915.595832339234; Tue, 23 Nov 2021 02:56:11 -0800 (PST) Received: from localhost ([::1]:42752 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mpTT7-0007Nj-Au for importer@patchew.org; Tue, 23 Nov 2021 05:56:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35930) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpTRZ-00062c-Lp for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:54:33 -0500 Received: from mail-bn8nam12on2061.outbound.protection.outlook.com ([40.107.237.61]:2626 helo=NAM12-BN8-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpTRW-0003Hk-BH for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:54:32 -0500 Received: from BN9PR03CA0752.namprd03.prod.outlook.com (2603:10b6:408:13a::7) by DM5PR02MB2569.namprd02.prod.outlook.com (2603:10b6:3:40::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.19; Tue, 23 Nov 2021 10:34:35 +0000 Received: from BN1NAM02FT049.eop-nam02.prod.protection.outlook.com (2603:10b6:408:13a:cafe::45) by BN9PR03CA0752.outlook.office365.com (2603:10b6:408:13a::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.20 via Frontend Transport; Tue, 23 Nov 2021 10:34:35 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (149.199.62.198) by BN1NAM02FT049.mail.protection.outlook.com (10.13.2.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4713.19 via Frontend Transport; Tue, 23 Nov 2021 10:34:35 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 23 Nov 2021 02:34:34 -0800 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 23 Nov 2021 02:34:34 -0800 Received: from [10.23.120.28] (port=57995 helo=debian.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mpT8D-000GX6-VD; Tue, 23 Nov 2021 02:34:34 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=oEqcAimvcTRNRYM4AMOWNXjyGkpXeDQ46GeL4s3rR+CQI55FKQZLXkL3Av7D2d7GEcoSJuh7E/AOR/KIYy9B35etFQTo4gIvIaDSqK5LzuiBZPszqypa1lbIS485ObgC0OvlilodawNA6nyY3D9biawyUaMGstsQoByJp6A2jwaomB5ah9kAV0M3g9loW6Xrk/MzyK+LxpuuR2M95mCE+ZmsyRJuVnpI/D0M8GzhHyv/3OYKmbdrvplr8vxDYrsEwDNtEM7+9B62H2jFpu+9FB5Ayxu39g7oN1vJrWwUh9LxjN5TsGVCn0AqfihbD0MegALu0tI/L/PmeePe0a//Aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=O6wFSjjFxQiIbqOG6eN7sadsXSsJa3HX/wNFLngggJE=; b=H/OkHmW811AqRxlIIAFIn5uf6D8mGGcnJSdidyd1PO6Ce8YKJXUDanUwPj/c0+HH4yqpUMSJUjjS57bsTQxI4WYGMG13QP0z2RcZnTdit/Ll5YB76zOee6t1fMPT7DVWtVy3smN4Fb1MbyYxvkCp+QJ4Rh5hH1NomZxtY8t6pj05z1tZFYxt/lEhC6O55EtIJoqU7VvofXlEZdu9Uq8ql7Cy23eUS1JJSyysTrJXjOPOakE60TgZl02fkeX50TOcDDWyKvmw8bZ428HcafcxCyIj5AlXatao8H2iFZJrTSEqWUeceHL+Hc7qTHNRJNAUmZZwcZK+rO6rZ1YLRcmrPA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=nongnu.org smtp.mailfrom=xilinx.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=O6wFSjjFxQiIbqOG6eN7sadsXSsJa3HX/wNFLngggJE=; b=oRyyYgMj/rfo1rn9UCPQah94D9T3L6yT+rHMBNzOCdTdxSfd0nre08sdD26UuWDEQZbP497qK9TPOtLtnSrpyIR055hhXhPRralFdVXJRE9618M8WeR2juE6cQgxSXCxJQl/Rnc7uJ7DO92NXPfTcgE8ITYiFEAMw5Bvf9qBQlw= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch02.xlnx.xilinx.com; From: Francisco Iglesias To: Subject: [PATCH v2 02/10] hw/arm/xlnx-versal: Connect Versal's PMC SLCR Date: Tue, 23 Nov 2021 10:34:20 +0000 Message-ID: <20211123103428.8765-3-francisco.iglesias@xilinx.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20211123103428.8765-1-francisco.iglesias@xilinx.com> References: <20211123103428.8765-1-francisco.iglesias@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 14669212-a19d-44f5-d54e-08d9ae6cd7f1 X-MS-TrafficTypeDiagnostic: DM5PR02MB2569: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:167; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MgwwiwcHpVH0bGSmXXSNOSZeuiJeo20sayCtN3ZK+ni3NSzKa7of2/QtO9nMZyUdWpX2//zkfRXFmdJDcjwwN31dK25rh/klp4K9IHxq0GM4+I1q9zLfwO/5bg3YBGdtY0ZPst/+npBocuLqc/ywuX9ncmaB9svf+rUA+apgld+EqhNr69/sGrcKd4Hi11GH0aFCkumrU3J+0rX2BcnNsETSPRj/Otb0S8dX9u/TvmXAia7sB/SSwizn345lNeEZ6M6jFrycL2/p7/rWtPjJRoPQD7iBLPRjUHwszkHDe0RqnDjljoilbptxS5A6bECDZ6A/VPQxWhqth+n+hpQqiZvCDmgLZrq4ps1zGI6ycdz1t+nOArKHWbl+sE2ir0v+iyefPakkXi6efyIu0JnCFZQFu/xTIPWF4HMRUbLrLNd7R/e+XsN4mcvuoHL03+wWOPtCXPMEeMPPqpWpSUTtcrnF11F/YXsztWTT2xzjqLhk0e8I6jL9qkObc0SvwaZogFv5uu3r7Et+Bq1W7geX3QVoDVVTN9/8Z9J0xSUHrySwtRUJkiBaMilCZtlREovO37La563GBa7eaqu0jEtnWaWEBBksOfLwXzA2GR4jdGWM/nEv/l5H799KZdoY7eb/qBmnpGqzmtUkSTvToLeEREiw2v39RaXDjw3ikdOGh4Tv34yWoZcX9489xvXlIWjQmsUhpo/2PI1+4Qr/LBVqH8PX5hoj9EWN7uFUqIc7Z+A= X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(46966006)(36840700001)(508600001)(36906005)(316002)(336012)(44832011)(8936002)(426003)(7696005)(7636003)(9786002)(2616005)(54906003)(36860700001)(6916009)(6666004)(70206006)(70586007)(186003)(1076003)(26005)(5660300002)(356005)(47076005)(4326008)(36756003)(8676002)(2906002)(82310400004)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2021 10:34:35.0867 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 14669212-a19d-44f5-d54e-08d9ae6cd7f1 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT049.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR02MB2569 Received-SPF: pass client-ip=40.107.237.61; envelope-from=figlesia@xilinx.com; helo=NAM12-BN8-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, peter.maydell@linaro.org, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1637664972369100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Connect Versal's PMC SLCR (system-level control registers) model. Signed-off-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias --- hw/arm/xlnx-versal.c | 18 ++++++++++++++++++ include/hw/arm/xlnx-versal.h | 6 ++++++ 2 files changed, 24 insertions(+) diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index b2705b6925..08e250945f 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -369,6 +369,23 @@ static void versal_create_efuse(Versal *s, qemu_irq *p= ic) sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]); } =20 +static void versal_create_pmc_iou_slcr(Versal *s, qemu_irq *pic) +{ + SysBusDevice *sbd; + + object_initialize_child(OBJECT(s), "versal-pmc-iou-slcr", &s->pmc.iou.= slcr, + TYPE_XILINX_VERSAL_PMC_IOU_SLCR); + + sbd =3D SYS_BUS_DEVICE(&s->pmc.iou.slcr); + sysbus_realize(sbd, &error_fatal); + + memory_region_add_subregion(&s->mr_ps, MM_PMC_PMC_IOU_SLCR, + sysbus_mmio_get_region(sbd, 0)); + + sysbus_connect_irq(sbd, 0, pic[VERSAL_PMC_IOU_SLCR_IRQ]); +} + + /* This takes the board allocated linear DDR memory and creates aliases * for each split DDR range/aperture on the Versal address map. */ @@ -459,6 +476,7 @@ static void versal_realize(DeviceState *dev, Error **er= rp) versal_create_xrams(s, pic); versal_create_bbram(s, pic); versal_create_efuse(s, pic); + versal_create_pmc_iou_slcr(s, pic); versal_map_ddr(s); versal_unimp(s); =20 diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 895ba12c61..729c093dfc 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -26,6 +26,7 @@ #include "hw/misc/xlnx-versal-xramc.h" #include "hw/nvram/xlnx-bbram.h" #include "hw/nvram/xlnx-versal-efuse.h" +#include "hw/misc/xlnx-versal-pmc-iou-slcr.h" =20 #define TYPE_XLNX_VERSAL "xlnx-versal" OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) @@ -78,6 +79,7 @@ struct Versal { struct { struct { SDHCIState sd[XLNX_VERSAL_NR_SDS]; + XlnxVersalPmcIouSlcr slcr; } iou; =20 XlnxZynqMPRTC rtc; @@ -113,6 +115,7 @@ struct Versal { #define VERSAL_XRAM_IRQ_0 79 #define VERSAL_BBRAM_APB_IRQ_0 121 #define VERSAL_RTC_APB_ERR_IRQ 121 +#define VERSAL_PMC_IOU_SLCR_IRQ 121 #define VERSAL_SD0_IRQ_0 126 #define VERSAL_EFUSE_IRQ 139 #define VERSAL_RTC_ALARM_IRQ 142 @@ -178,6 +181,9 @@ struct Versal { #define MM_FPD_FPD_APU 0xfd5c0000 #define MM_FPD_FPD_APU_SIZE 0x100 =20 +#define MM_PMC_PMC_IOU_SLCR 0xf1060000 +#define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000 + #define MM_PMC_SD0 0xf1040000U #define MM_PMC_SD0_SIZE 0x10000 #define MM_PMC_BBRAM_CTRL 0xf11f0000 --=20 2.11.0 From nobody Fri Apr 19 16:53:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail(p=none dis=none) header.from=xilinx.com ARC-Seal: i=2; a=rsa-sha256; t=1637663936; cv=pass; d=zohomail.com; s=zohoarc; b=dbrqAyImXPd2TRjPfvyrwjHtk+2ztufc+tbDu+SwaRWy9eS4FTrVseSJ8avw/Od0mkbRZxU9B6tuyAmeZxaj/Uls9T0nPaMxjav6f1E858XBe9biZTCUHNJ3Uf9Sx2vjlwCb84no49RBaZgE7DOvD4vUEZDhILD/hV7kVuQt99Y= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637663936; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8nqRu9hAriGCDY8wXrJ2ZR8F9wDDPQuQ30VcoOLDeos=; b=KTIE852ykdazkGesHZmYg8DOTtQOfrv6H0gBzbCDBLwXiA/8aTR7g7pXvvHCSwcKNrh1CsBSpYsLlWbaMl7jORJgSC1gaYT/6xlRQHv58nIdhOE6zf9wNtryA+uDmH5XPrL2UjOjmhWx5mx/BtbH8/Omej3USXrROzTVEc2ioMc= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637663936309829.0179968564931; Tue, 23 Nov 2021 02:38:56 -0800 (PST) Received: from localhost ([::1]:41374 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mpTCQ-0003qt-BV for importer@patchew.org; Tue, 23 Nov 2021 05:38:54 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60400) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpT8M-0004WH-Cj for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:34:42 -0500 Received: from mail-dm6nam10on2064.outbound.protection.outlook.com ([40.107.93.64]:19296 helo=NAM10-DM6-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpT8J-0000gB-RS for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:34:41 -0500 Received: from DM6PR03CA0036.namprd03.prod.outlook.com (2603:10b6:5:40::49) by BY5PR02MB6275.namprd02.prod.outlook.com (2603:10b6:a03:1b6::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.19; Tue, 23 Nov 2021 10:34:36 +0000 Received: from DM3NAM02FT015.eop-nam02.prod.protection.outlook.com (2603:10b6:5:40:cafe::a4) by DM6PR03CA0036.outlook.office365.com (2603:10b6:5:40::49) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.20 via Frontend Transport; Tue, 23 Nov 2021 10:34:36 +0000 Received: from xsj-pvapexch01.xlnx.xilinx.com (149.199.62.198) by DM3NAM02FT015.mail.protection.outlook.com (10.13.5.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4713.19 via Frontend Transport; Tue, 23 Nov 2021 10:34:36 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 23 Nov 2021 02:34:35 -0800 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 23 Nov 2021 02:34:35 -0800 Received: from [10.23.120.28] (port=57995 helo=debian.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mpT8F-000GX6-Ju; Tue, 23 Nov 2021 02:34:35 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=aQkpu996p58/XWr4kPeVLt7fY2Pl4gUWxqlszPV+2w1ya5/D2Y5U/OxCpLlbg7IFOPpg0tB9hf97LV9+S+hrmF/ksJzYv8Z94e5Q0BSH+TSGp4E+s4k/RfFlnEYKXMuPYBKuqCDCxdpFyjieT0Bc6UQxPV9rFDjaid9+CayNaGp1qyEtiUKjv5ZW6jPfnbniol7Edk/LvT0bcB86KnjNlqyKFImhBGt4uWMf5SnpVJwgJErz8rW9oPkk3gAB9xegWygh4zfMelFH0gjWAtNy9xJBQz2B7Kb+zSX0WKJGoFvvW37FJFt92mMpRXp+mFHuuzRTMcyTT0Zm1u4IN+hY+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=8nqRu9hAriGCDY8wXrJ2ZR8F9wDDPQuQ30VcoOLDeos=; b=fpg5NFJlfMyR6eMqdAhcAbJHbn0Tvy8sDFC5utVuAAWjIAkG6wgffWxIuXwT7E7K0PDDUgqPESxefc4Ei3OHmWvUkvCD84RF8hvSCLDvU0v0hM5Uj2z6hItgx+AzliOGoxrEqxC8DQdMuJXv386QCGt+U1f/fOPmTRww+fViv3ldDElql1GA+HHIK5M7P8AitOApz4lLErOzLWECIlpqGbLSvMPSAxlYF+PnbKgdZjoEMoFik3DxZUXGwheQT34I6RGQfPVruV8SHXvyySo/NZLC+GHFxtzcUIdTN62js9eo0T1gz7l7ZGuYAcWr8C4Fcn3pkxwZ0wXIsp+4XBVccw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=nongnu.org smtp.mailfrom=xilinx.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=8nqRu9hAriGCDY8wXrJ2ZR8F9wDDPQuQ30VcoOLDeos=; b=ZEQ/1NbV7VJe1a2XoGV8UKLapoP9TEUDUnI3IUxelwrJVF0rNhMJsf0g0jVpMjru/QYoOO7pVFTVHu1r3KzxnMO7ykINeID4RuOR4+mJJnlj0gR3qQH3BLC1fAs1Aoh+cumAbnCJCBVQXFrR8gOhgV1c+7mqJasmIWNrWd7okhY= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch01.xlnx.xilinx.com; From: Francisco Iglesias To: Subject: [PATCH v2 03/10] include/hw/dma/xlnx_csu_dma: Include ptimer.h and stream.h in the header Date: Tue, 23 Nov 2021 10:34:21 +0000 Message-ID: <20211123103428.8765-4-francisco.iglesias@xilinx.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20211123103428.8765-1-francisco.iglesias@xilinx.com> References: <20211123103428.8765-1-francisco.iglesias@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3e972fee-9808-4927-5ed3-08d9ae6cd8a9 X-MS-TrafficTypeDiagnostic: BY5PR02MB6275: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:4714; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vHxLIko7bukShGTEx9YXpsMcZ3odPC/T6iZG/99JlWnD1SeHsgOjYCafWU+9c3CObWLm8pDWRBQhBICI70nXBjgcBbR5gluaiMs5btA/c5XmaAB7oaLk2Len19G1f8L4HReJBV5jMv0cgNxHpaNWu0pmV8TkBr3Xlw1dueP6naMUVWUf7g8K2k3kasbHGkY7EjDx8F7ccrpRTRucB1iqS57ie4qyoVp0zn2A5/Jmn8zJyuAmOLJaFuIrk4Q3ciSTFeAIyrR3qwmY0V/oF1u++wW5VZYBgitcF/FQo+wnTfPLQJ/2qfqowEQijWbZ4/Ij/d/A0pfmas6FYEIIHB8PR+XCTrrXEnxjmzHw4l2IfgwPvu2D1RdjxbBzs+nwJc3tBQZCnHW5GAEJA5bz1pzOi5uJ/W0HheOmy9W1M4nkxx+/yCUMoGt6iRfJ+s2UfPuu4MTz6qmddbpf+DCofn/cyYnt21PMAqznkYglDdL3+3TiuFsipMHBtmK2b6RT+ocj26Ozh0hVS6kQFAe0SlgdSsnEkCgoAvOwWHJV3HsHHy0fOeqIGqi7HZwQIYpWwNqXyb9J4qW3e5py3g/fCYCqcywzzwvPov1yPUewoGih5iHzUKi2ymS2H/5bWUvs0WHYDNKk07gi4F86h91aT5S83SDXgnUK4W0O+tKGxyu7Se5BlUX1BwBniMxhTsAx3nhdeLW2FsF54Uy9CdaKG2iLuNTUqNzjs5nTLISYMLjugdQ= X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch01.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(36840700001)(46966006)(8936002)(6666004)(36860700001)(36756003)(44832011)(356005)(6916009)(5660300002)(186003)(7696005)(47076005)(4326008)(426003)(2616005)(316002)(54906003)(4744005)(36906005)(8676002)(2906002)(9786002)(508600001)(26005)(1076003)(336012)(82310400004)(7636003)(70206006)(70586007)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2021 10:34:36.3405 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e972fee-9808-4927-5ed3-08d9ae6cd8a9 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT015.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR02MB6275 Received-SPF: pass client-ip=40.107.93.64; envelope-from=figlesia@xilinx.com; helo=NAM10-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, peter.maydell@linaro.org, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1637663938692100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Include ptimer.h and stream.h in the header for being able to build and reuse the DMA model (the first usage of StreamSink, StreamCanPushNotifyFn and ptimer_state is in the header). Signed-off-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias --- include/hw/dma/xlnx_csu_dma.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/hw/dma/xlnx_csu_dma.h b/include/hw/dma/xlnx_csu_dma.h index 9e9dc551e9..8c39e46f58 100644 --- a/include/hw/dma/xlnx_csu_dma.h +++ b/include/hw/dma/xlnx_csu_dma.h @@ -21,6 +21,9 @@ #ifndef XLNX_CSU_DMA_H #define XLNX_CSU_DMA_H =20 +#include "hw/ptimer.h" +#include "hw/stream.h" + #define TYPE_XLNX_CSU_DMA "xlnx.csu_dma" =20 #define XLNX_CSU_DMA_R_MAX (0x2c / 4) --=20 2.11.0 From nobody Fri Apr 19 16:53:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail(p=none dis=none) header.from=xilinx.com ARC-Seal: i=2; a=rsa-sha256; t=1637663823; cv=pass; d=zohomail.com; s=zohoarc; b=axmxD0RE2Y3LMOTLd3nPdXaylM3OzDyElcOode2ZP40HrOAelU3H1homX0SXILMHe1EeL/NRLPK43dzdaMmre5flyMAW0E0EhuK/5cFhgO55PDCQDaHVskzvZmKw5h+D1IOSZdGecjbV0fLO4ffgeEmQHZcJBymg/SvugV0CERA= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637663823; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zhCzaXc4aImKVpMcjwxjWVho/pSrarlvgXVsQTWFYH4=; b=Vtsas1Ah1bdlH+CeA3ekEmaYh2JMoffO5EEZSwCXCneVWkv9VDgh1daQoybz8tK2v3SgDOXuTrvJ1IFEmyrf8SnNM+bqjSdSWotT7r1LYj9UUZRZvEo6CYmXAfzlN6Yuv3ddyPg1SR+VnaZj/RQx0ACNeZ6iHvFqbR/6X4jFWQc= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637663823176417.5464317796443; Tue, 23 Nov 2021 02:37:03 -0800 (PST) Received: from localhost ([::1]:35000 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mpTAb-00082Z-0I for importer@patchew.org; Tue, 23 Nov 2021 05:37:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60402) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpT8M-0004Wl-N8 for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:34:42 -0500 Received: from mail-dm6nam10on2071.outbound.protection.outlook.com ([40.107.93.71]:58785 helo=NAM10-DM6-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpT8K-0000gr-Mg for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:34:42 -0500 Received: from BN9PR03CA0780.namprd03.prod.outlook.com (2603:10b6:408:13a::35) by MN2PR02MB6720.namprd02.prod.outlook.com (2603:10b6:208:1db::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.21; Tue, 23 Nov 2021 10:34:38 +0000 Received: from BN1NAM02FT049.eop-nam02.prod.protection.outlook.com (2603:10b6:408:13a:cafe::46) by BN9PR03CA0780.outlook.office365.com (2603:10b6:408:13a::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.21 via Frontend Transport; Tue, 23 Nov 2021 10:34:38 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (149.199.62.198) by BN1NAM02FT049.mail.protection.outlook.com (10.13.2.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4713.19 via Frontend Transport; Tue, 23 Nov 2021 10:34:38 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 23 Nov 2021 02:34:37 -0800 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 23 Nov 2021 02:34:37 -0800 Received: from [10.23.120.28] (port=57995 helo=debian.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mpT8H-000GX6-8h; Tue, 23 Nov 2021 02:34:37 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Cy5/HTb9vg+eoozEnASbXTzSzxGDm8Ffk8HbA8r5yQZvUpcF92x1C//JYsqnSA5DvpNz+QnY0Y/7N+ShwGpMIuIAsJFVWmrFdq+cxNieM9qDDXoF3f8SmYJBA8RynLEGTa2PzE7a+jkfgeARAN86QFdOUJYTpU9hQJI7zMqk6IknVh/5MFcBiMZIqmpEtmHI7wdmnuQyXlgGLflYBL8+UP1Lz63se9F5tLkWlc2PAI2pSJC+Qe355V/XtwtfzH6cALJyZDPHOAmeb8SYd5j3GruAIm48mYeI0gaBSqpYyndc7syeCq9Wp5hqbH9xTxmonExeZh4H54JMy8/ehiAo/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zhCzaXc4aImKVpMcjwxjWVho/pSrarlvgXVsQTWFYH4=; b=OSWSpQVUw5XsDulkVN3adBKc6YFULHcw3JRRWa6MyjwozdqmFuc3basyyqPJNtKKnk6kK3v1jR/+6V1PklGkqHKgq19p5rRPYVZqy/PYQaDow5MUVY35BQMVIECpfGmYTdI+Y6OR0FNafHQ5ZIyLoN6S9NU6yQS7yA88rRQit77zP7zktPRFU5LewOedX/qseSXyoW9cUdhDvnRyYtTFg0KrsT6YwM4/nhJA8uUsQSzlBvSZeIBKkVdWj8AloLVkI8ZHsVTqlNHOCMahnHQBapkKptVAmlNL0x4iHVCwB8uUS/cBNbrJdiRq4qdRd6BpXfU/MJUD2BCJTKMvAuuG2Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=nongnu.org smtp.mailfrom=xilinx.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zhCzaXc4aImKVpMcjwxjWVho/pSrarlvgXVsQTWFYH4=; b=QQoJ6Z4PevR/8G5NlF+e4BII8HGnXJU+Uq31WfAILADVRO3SCCLczQ8zgVBV1XjZsAkAJ/Labl9UGSRRe3R85pJNii15audofVaOvKMY2e+ttpoUjX1XHPoSfnVidvoWh2aGZJeMYw64j00MLjM4FwSJ8d//e398LyQIE4oAwBU= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch02.xlnx.xilinx.com; From: Francisco Iglesias To: Subject: [PATCH v2 04/10] hw/dma: Add the DMA control interface Date: Tue, 23 Nov 2021 10:34:22 +0000 Message-ID: <20211123103428.8765-5-francisco.iglesias@xilinx.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20211123103428.8765-1-francisco.iglesias@xilinx.com> References: <20211123103428.8765-1-francisco.iglesias@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 42f15797-826a-44ec-4af0-08d9ae6cd9d2 X-MS-TrafficTypeDiagnostic: MN2PR02MB6720: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:4502; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nmUvwfgRBqe6T45RbBfsUAv8K71yhl4oYaG/LhMuZ+11ia/QF9z82hcPneOMX6GCW2ajqF2u4zxE0y4TKBnvYtLC8kvpIX2/LgScO4GgiBb7DYepjqO673+o8BoVASYlD14nQkhobLneDI4QiM31kx2dJzVyfgSJ4QwjKLbIf8waqz+IryObV+hRlHPFv5Q11TB5Wl6dj6yVlGJLX5yOhU0mb2F6I5BvdYN3RF7Glj/0fxqEsUiiULYkVmCL8C0/8UG73EKozF2PGGHohXqAyOzUcI/ePJuuANt1UQiPUygXA4GEl2nRlX4w3/YX2byYFcvd94TaqZQdCox8m3WvgLA7SQ/I70/GpOlftcZ720DhPR5QeDHwy87eyBvcZ8/cIRbzRgNu+zSaNgDUjE0DsK34EOi3O00dpDzFDoBrZbgLwBiodsvsdA1cAN9xeY0tq7e3wgzovpD9XVdNE61ZgtFPeAnxjetDZptIRw+jYIUGWoJvKqL4ZAATJPxPZo7OTS81dibQpC36n6gIpJHn/XJJZJX1zC4YpLPI5+7A9KWTkIiFmDg314KUMynkXQ1kLap32qBZA0BsdV38PX8fGAyo+nJoaxkK67lLE2G2IiElZJvQigmcbI6r14nFuuZn3gPpUaoF9mfXgcuhX7whuRqZXlQdEagJro853theL54oOPE6a91nUEYAm7y+4kpTZ8wQ1o0zaSqtetXmNbRjnp3zD2NJuahRWI0Hw3ncA1w= X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(46966006)(36840700001)(426003)(44832011)(8676002)(2616005)(36906005)(8936002)(508600001)(36756003)(54906003)(356005)(316002)(47076005)(26005)(336012)(5660300002)(70206006)(6916009)(1076003)(7636003)(4326008)(6666004)(36860700001)(70586007)(7696005)(2906002)(82310400004)(186003)(9786002)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2021 10:34:38.2365 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 42f15797-826a-44ec-4af0-08d9ae6cd9d2 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT049.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR02MB6720 Received-SPF: pass client-ip=40.107.93.71; envelope-from=figlesia@xilinx.com; helo=NAM10-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, peter.maydell@linaro.org, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1637663824051100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add an interface for controlling DMA models that are reused with other models. This allows a controlling model to start transfers through the DMA while reusing the DMA's handling of transfer state and completion signaling. Signed-off-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias --- hw/dma/dma-ctrl.c | 31 ++++++++++++++++++++ hw/dma/meson.build | 1 + include/hw/dma/dma-ctrl.h | 74 +++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 106 insertions(+) create mode 100644 hw/dma/dma-ctrl.c create mode 100644 include/hw/dma/dma-ctrl.h diff --git a/hw/dma/dma-ctrl.c b/hw/dma/dma-ctrl.c new file mode 100644 index 0000000000..4a9b68dac1 --- /dev/null +++ b/hw/dma/dma-ctrl.c @@ -0,0 +1,31 @@ +/* + * DMA control interface. + * + * Copyright (c) 2021 Xilinx Inc. + * Written by Francisco Iglesias + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "exec/hwaddr.h" +#include "hw/dma/dma-ctrl.h" + +void dma_ctrl_read_with_notify(DmaCtrl *dma_ctrl, hwaddr addr, uint32_t le= n, + DmaCtrlNotify *notify, bool start_dma) +{ + DmaCtrlClass *dcc =3D DMA_CTRL_GET_CLASS(dma_ctrl); + dcc->read(dma_ctrl, addr, len, notify, start_dma); +} + +static const TypeInfo dma_ctrl_info =3D { + .name =3D TYPE_DMA_CTRL, + .parent =3D TYPE_INTERFACE, + .class_size =3D sizeof(DmaCtrlClass), +}; + +static void dma_ctrl_register_types(void) +{ + type_register_static(&dma_ctrl_info); +} + +type_init(dma_ctrl_register_types) diff --git a/hw/dma/meson.build b/hw/dma/meson.build index f3f0661bc3..c0bc134046 100644 --- a/hw/dma/meson.build +++ b/hw/dma/meson.build @@ -14,3 +14,4 @@ softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa= 2xx_dma.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_PDMA', if_true: files('sifive_pdma.c')) softmmu_ss.add(when: 'CONFIG_XLNX_CSU_DMA', if_true: files('xlnx_csu_dma.c= ')) +common_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('dma-ctrl.c')) diff --git a/include/hw/dma/dma-ctrl.h b/include/hw/dma/dma-ctrl.h new file mode 100644 index 0000000000..498469395f --- /dev/null +++ b/include/hw/dma/dma-ctrl.h @@ -0,0 +1,74 @@ +/* + * DMA control interface. + * + * Copyright (c) 2021 Xilinx Inc. + * Written by Francisco Iglesias + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef HW_DMA_CTRL_H +#define HW_DMA_CTRL_H + +#include "qemu-common.h" +#include "hw/hw.h" +#include "qom/object.h" + +#define TYPE_DMA_CTRL "dma-ctrl" + +#define DMA_CTRL_CLASS(klass) \ + OBJECT_CLASS_CHECK(DmaCtrlClass, (klass), TYPE_DMA_CTRL) +#define DMA_CTRL_GET_CLASS(obj) \ + OBJECT_GET_CLASS(DmaCtrlClass, (obj), TYPE_DMA_CTRL) +#define DMA_CTRL(obj) \ + INTERFACE_CHECK(DmaCtrl, (obj), TYPE_DMA_CTRL) + +typedef void (*dmactrl_notify_fn)(void *opaque); + +typedef struct DmaCtrlNotify { + void *opaque; + dmactrl_notify_fn cb; +} DmaCtrlNotify; + +typedef struct DmaCtrl { + Object Parent; +} DmaCtrl; + +typedef struct DmaCtrlClass { + InterfaceClass parent; + + /* + * read: Start a read transfer on the DMA implementing the DMA control + * interface + * + * @dma_ctrl: the DMA implementing this interface + * @addr: the address to read + * @len: the amount of bytes to read at 'addr' + * @notify: the structure containg a callback to call and opaque point= er + * to pass the callback when the transfer has been completed + * @start_dma: true for starting the DMA transfer and false for just + * refilling and proceding an already started transfer + */ + void (*read)(DmaCtrl *dma_ctrl, hwaddr addr, uint32_t len, + DmaCtrlNotify *notify, bool start_dma); +} DmaCtrlClass; + +/* + * Start a read transfer on a DMA implementing the DMA control interface. + * The DMA will notify the caller that 'len' bytes have been read at 'addr' + * through the callback in the DmaCtrlNotify structure. For allowing refil= ling + * an already started transfer the DMA notifies the caller before consider= ing + * the transfer done (e.g. before setting done flags, generating IRQs and + * modifying other relevant internal device state). + * + * @dma_ctrl: the DMA implementing this interface + * @addr: the address to read + * @len: the amount of bytes to read at 'addr' + * @notify: the structure containing a callback to call and opaque pointer + * to pass the callback when the transfer has been completed + * @start_dma: true for starting the DMA transfer and false for just + * refilling and proceding an already started transfer + */ +void dma_ctrl_read_with_notify(DmaCtrl *dma_ctrl, hwaddr addr, uint32_t le= n, + DmaCtrlNotify *notify, bool start_dma); + +#endif /* HW_DMA_CTRL_H */ --=20 2.11.0 From nobody Fri Apr 19 16:53:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail(p=none dis=none) header.from=xilinx.com ARC-Seal: i=2; a=rsa-sha256; t=1637663796; cv=pass; d=zohomail.com; s=zohoarc; b=OzB0D1O2mlBkSvq5WSWl5LKzcU8mi7dv5iz6J3/tQWd2xqIU54it20MZS6BYT7oidL/poI1bAQYuXhakXwjdpsOXxyNHvoB8nMShSib8QrW/R36Lxo2KSgIMl/ih+URDvdhlbF++l2fD680+MQqDyusi1/f3DYoAuJIWnQQ+ztI= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637663796; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zTXww8o72NyYGbiT5puw7yIhM/D7vD31ZnWRU04c0yA=; b=Dg93qikYK3/eTI841LTIaws/+nyym+g70iHV0Rk0/G4wJJkHeO/McS+5LE4qs7x6k4wq5pZaUauYlDlYTv139s4YgZobt6mAHwS8A8OTc/zPy1QwLEJLQhbhoEl2MUaL8Vrlxkc9QkGJ99TVoGXRiD1e2jPYz46Obgu/AVjyGWA= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637663796063706.9698798904636; Tue, 23 Nov 2021 02:36:36 -0800 (PST) Received: from localhost ([::1]:34168 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mpTA9-0007PN-KQ for importer@patchew.org; Tue, 23 Nov 2021 05:36:33 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60448) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpT8S-0004kv-39 for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:34:48 -0500 Received: from mail-co1nam11on2046.outbound.protection.outlook.com ([40.107.220.46]:16352 helo=NAM11-CO1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpT8Q-0000hQ-Cz for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:34:47 -0500 Received: from BN9PR03CA0436.namprd03.prod.outlook.com (2603:10b6:408:113::21) by DM6PR02MB7097.namprd02.prod.outlook.com (2603:10b6:5:25d::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.22; Tue, 23 Nov 2021 10:34:43 +0000 Received: from BN1NAM02FT011.eop-nam02.prod.protection.outlook.com (2603:10b6:408:113:cafe::d1) by BN9PR03CA0436.outlook.office365.com (2603:10b6:408:113::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.21 via Frontend Transport; Tue, 23 Nov 2021 10:34:43 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (149.199.62.198) by BN1NAM02FT011.mail.protection.outlook.com (10.13.2.129) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4713.19 via Frontend Transport; Tue, 23 Nov 2021 10:34:43 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 23 Nov 2021 02:34:39 -0800 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 23 Nov 2021 02:34:39 -0800 Received: from [10.23.120.28] (port=57995 helo=debian.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mpT8I-000GX6-Sl; Tue, 23 Nov 2021 02:34:39 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WHxDNSDZVsTt5VxHrGXSv05cSyS2DbZRNWxh3i2gYDnxEKElX30PCyqzuKTsSB+J4p5U8wLaK43nWHViCPqj+9Re6pIi2wnH+lMV/Hy5qxWLxmGSYcu92aBaUqGsEVbkqTLCMZgXmC0R3mg86GYNftuCCxtOX35qnaNNPSFS23CD4mTgFUZ8/S+7PZN4UPThJRruHXH7mEnPOPTXElyFfEjCJfz6PQ9SGZcMGJ5lJPWrICeSKrbMxY8QNW0u0SoOA8bIm8zVa6sYsucjB8sWVBb62w3rLJCU2mr8F/led3NjNwn8vGF9s/3FWhgTAtlxapS3mwU3TJcmNZn4kW0Y7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zTXww8o72NyYGbiT5puw7yIhM/D7vD31ZnWRU04c0yA=; b=J+wxK28F5oVBu+kDw3Ifn9YLFkqM0w7JXTllEz/cSy8dr6/NnmXoqJ/57tkc61cWsQuu4sPkrQ3/C5EelP5rzYbZPeudLsYRuF3oHAloj/HQfCeNycGeWMsq0Ky0oa8d/DajU/PZS4yyyE/nB5Ai+Vv7aOXf6URCT9sHpoo59SaBmUj6Jl6OFhHuC/TEny+2eZvBO/13F4FfKq8m91mCiVJ06c4oRSupnIkJBhRzX0PxUo7K8DRGRVYSJveIoVGA6eXTt9PTuMIdneGbjtqSiOCFtoR5x1hoXDcAWJ1rox+QZZf1fouamJEnzrfb7u3+7fCjQhF4GP9TcD9E3V7LUA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=nongnu.org smtp.mailfrom=xilinx.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zTXww8o72NyYGbiT5puw7yIhM/D7vD31ZnWRU04c0yA=; b=g58ZkWaEIwn9MHCy9jdhB8IdwMEdgu7JKcCH7DtOLt/OBcmFh4oe8DteC9tQ3X87MJ2+Mz7Wu8qKOD9H0BfpPN+kYL7D9Wpfs3IIqYgpTdyzKMlsZw0rkNLFD9sj+ScX4MZlD28CjWQqB3lMe8peIFSY5r0j2juWpiJaqWt+uW0= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch02.xlnx.xilinx.com; From: Francisco Iglesias To: Subject: [PATCH v2 05/10] hw/dma/xlnx_csu_dma: Implement the DMA control interface Date: Tue, 23 Nov 2021 10:34:23 +0000 Message-ID: <20211123103428.8765-6-francisco.iglesias@xilinx.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20211123103428.8765-1-francisco.iglesias@xilinx.com> References: <20211123103428.8765-1-francisco.iglesias@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c6368ed8-28cb-4ec2-3d9f-08d9ae6cdcec X-MS-TrafficTypeDiagnostic: DM6PR02MB7097: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:751; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9XV+B0Sm2U1ZkZL4RyymHDVYPjttdjnhDfO7i8WHzzqrJUAyjnSaFYRCS904O5vu/lvFPw01PCp1CYTo6wWcYJmSNeB/SyyMpaFB5FtFQ4GCTW9KkmfxvCQosrWZCDXeIPyZg4mRbfq1C2zDbR+nMSdA0Pw+2a9r4Hhl/28ru9WG256nf9euF9n4wFTHBoLjL/9JASZ46kxgaurY89TVkoVL+zM5fHA9JoP4IY+72VGuLOCGj7fKafbqz2V3bvKnr+yyyb1cJ3jxYkCT2li+RxxVfLde0vnt6SSlOjCDa3A9hPNzIPBgoYS/nJQNTgJpt+L+PRsHaDvi+v1ooX9j8oysqs2CE+nk4HwlkTVoB23qsfUEr+5im4duFtLz8S2iW8TCN9dzU353y0EIpPQGwR+Ciqe2K5FG3obtKtCgDv7umuyIT4nqZtDhwuYy7ZjBPYGZbfUzPKJS47GPme4OoCpyiCL6jUn1kZeYGXPw2fKRu3B0Hrs1yD/QnSAlXmUQOLgDMPSt4V1M6eyLGYA4YIvtaf13js2cyvImueVChZzO9gxeMzJpJU3p+HUvtvaxS0kxDZlBrNlmr0H6JlIs17/UI8nmP7WkRTQ67ww+3v5LCXVQ9qNnA+TvYcwEX5ESyDLzDWEjD79nT7YmOgKmvBh9//XH3lUHiIQIrnetos9XHyK9tYMSMtda1bb+lRQWdlzUmXl5K4T8d9fPFu1QoMfL922BAKQdmDjtEO092JY= X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(36840700001)(46966006)(336012)(6916009)(426003)(1076003)(70586007)(7696005)(5660300002)(9786002)(36860700001)(36756003)(186003)(82310400004)(316002)(36906005)(508600001)(8676002)(83380400001)(70206006)(54906003)(2906002)(44832011)(8936002)(47076005)(7636003)(356005)(6666004)(26005)(4326008)(2616005)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2021 10:34:43.4397 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6368ed8-28cb-4ec2-3d9f-08d9ae6cdcec X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT011.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB7097 Received-SPF: pass client-ip=40.107.220.46; envelope-from=figlesia@xilinx.com; helo=NAM11-CO1-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, peter.maydell@linaro.org, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1637663798157100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement the DMA control interface for allowing control of DMA operations from inside models that contain instances of (and reuse) the Xilinx CSU DMA. Signed-off-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias --- hw/dma/xlnx_csu_dma.c | 32 ++++++++++++++++++++++++++++++++ include/hw/dma/xlnx_csu_dma.h | 4 ++++ 2 files changed, 36 insertions(+) diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c index 896bb3574d..9ed6e82225 100644 --- a/hw/dma/xlnx_csu_dma.c +++ b/hw/dma/xlnx_csu_dma.c @@ -277,6 +277,11 @@ static uint32_t xlnx_csu_dma_advance(XlnxCSUDMA *s, ui= nt32_t len) s->regs[R_ADDR_MSB] =3D dst >> 32; } =20 + /* Notify dma-ctrl clients when the transfer has been completed */ + if (size =3D=3D 0 && s->dma_ctrl_notify) { + s->dma_ctrl_notify(s->dma_ctrl_opaque); + } + if (size =3D=3D 0) { xlnx_csu_dma_done(s); } @@ -472,6 +477,29 @@ static uint64_t addr_msb_pre_write(RegisterInfo *reg, = uint64_t val) return val & R_ADDR_MSB_ADDR_MSB_MASK; } =20 +static void xlnx_csu_dma_dma_ctrl_read(DmaCtrl *dma_ctrl, hwaddr addr, + uint32_t len, DmaCtrlNotify *noti= fy, + bool start_dma) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(dma_ctrl); + RegisterInfo *reg =3D &s->regs_info[R_SIZE]; + uint64_t we =3D MAKE_64BIT_MASK(0, 4 * 8); + + s->regs[R_ADDR] =3D addr; + s->regs[R_ADDR_MSB] =3D (uint64_t)addr >> 32; + + if (notify) { + s->dma_ctrl_notify =3D notify->cb; + s->dma_ctrl_opaque =3D notify->opaque; + } + + if (start_dma) { + register_write(reg, len, we, object_get_typename(OBJECT(s)), false= ); + } else { + s->regs[R_SIZE] =3D len; + } +} + static const RegisterAccessInfo *xlnx_csu_dma_regs_info[] =3D { #define DMACH_REGINFO(NAME, snd) = \ (const RegisterAccessInfo []) { = \ @@ -696,6 +724,7 @@ static void xlnx_csu_dma_class_init(ObjectClass *klass,= void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); StreamSinkClass *ssc =3D STREAM_SINK_CLASS(klass); + DmaCtrlClass *dcc =3D DMA_CTRL_CLASS(klass); =20 dc->reset =3D xlnx_csu_dma_reset; dc->realize =3D xlnx_csu_dma_realize; @@ -704,6 +733,8 @@ static void xlnx_csu_dma_class_init(ObjectClass *klass,= void *data) =20 ssc->push =3D xlnx_csu_dma_stream_push; ssc->can_push =3D xlnx_csu_dma_stream_can_push; + + dcc->read =3D xlnx_csu_dma_dma_ctrl_read; } =20 static void xlnx_csu_dma_init(Object *obj) @@ -731,6 +762,7 @@ static const TypeInfo xlnx_csu_dma_info =3D { .instance_init =3D xlnx_csu_dma_init, .interfaces =3D (InterfaceInfo[]) { { TYPE_STREAM_SINK }, + { TYPE_DMA_CTRL }, { } } }; diff --git a/include/hw/dma/xlnx_csu_dma.h b/include/hw/dma/xlnx_csu_dma.h index 8c39e46f58..f7f086593c 100644 --- a/include/hw/dma/xlnx_csu_dma.h +++ b/include/hw/dma/xlnx_csu_dma.h @@ -23,6 +23,7 @@ =20 #include "hw/ptimer.h" #include "hw/stream.h" +#include "hw/dma/dma-ctrl.h" =20 #define TYPE_XLNX_CSU_DMA "xlnx.csu_dma" =20 @@ -45,6 +46,9 @@ typedef struct XlnxCSUDMA { StreamCanPushNotifyFn notify; void *notify_opaque; =20 + dmactrl_notify_fn dma_ctrl_notify; + void *dma_ctrl_opaque; + uint32_t regs[XLNX_CSU_DMA_R_MAX]; RegisterInfo regs_info[XLNX_CSU_DMA_R_MAX]; } XlnxCSUDMA; --=20 2.11.0 From nobody Fri Apr 19 16:53:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail(p=none dis=none) header.from=xilinx.com ARC-Seal: i=2; a=rsa-sha256; t=1637663825; cv=pass; d=zohomail.com; s=zohoarc; b=WPzRiCOXNYW0oxtjqa6epcAHas7gTF2hlCn3dXkDLmndCl+eCFmZwzAfvJjkELVZAglYHtw9qPgFcaJzJkZvv/tNULk0y0DaSgk6+J9bzZUjBi7MvIF0PfolOH9avkcq5/ZXMzaXH61sMYNdUOwFI5Kfc0WFqSehrTf4KWcw1rM= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637663825; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IX1vbkd0o8jV6H+x5mOP27LqWJmXLcEj+g6WPvyElDE=; b=PWOI9EgauYOITUcowlh9u4/IA6OnpQHsdZ66wMTCUG+0WsfeZN0nKECInt5s/eafjimp9LhlNPHDIoLWiuTmY8zF3TuFbu/b1N3lAGhVvNpljZ195ibYtD9EXC4uhgmOIjcnb0MHd8mh4+sl47otct+wUnsM+H9LB62+g1Qn03E= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163766382571134.504996542839194; Tue, 23 Nov 2021 02:37:05 -0800 (PST) Received: from localhost ([::1]:34928 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mpTAd-0007zq-3l for importer@patchew.org; Tue, 23 Nov 2021 05:37:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60482) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpT8V-0004rO-IT for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:34:54 -0500 Received: from mail-bn7nam10on2067.outbound.protection.outlook.com ([40.107.92.67]:61174 helo=NAM10-BN7-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpT8Q-0000hb-I4 for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:34:51 -0500 Received: from DM5PR15CA0071.namprd15.prod.outlook.com (2603:10b6:3:ae::33) by BYAPR02MB4871.namprd02.prod.outlook.com (2603:10b6:a03:49::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.19; Tue, 23 Nov 2021 10:34:42 +0000 Received: from DM3NAM02FT023.eop-nam02.prod.protection.outlook.com (2603:10b6:3:ae:cafe::eb) by DM5PR15CA0071.outlook.office365.com (2603:10b6:3:ae::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.22 via Frontend Transport; Tue, 23 Nov 2021 10:34:42 +0000 Received: from xsj-pvapexch01.xlnx.xilinx.com (149.199.62.198) by DM3NAM02FT023.mail.protection.outlook.com (10.13.5.127) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4713.19 via Frontend Transport; Tue, 23 Nov 2021 10:34:41 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 23 Nov 2021 02:34:40 -0800 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 23 Nov 2021 02:34:40 -0800 Received: from [10.23.120.28] (port=57995 helo=debian.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mpT8K-000GX6-H8; Tue, 23 Nov 2021 02:34:40 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=f+31m5TtA1Xykt8WaQADK4aAYiT2UuT+LVBtg4XwhK1uHN99V66KdQ+PSjddTOeZkdt4Ei7B9tjxiC+rB0WXoxntwgFrw0XskGRFZSpPkQ6Wni1f083DCOIgoq/DmtF2pzlkmdEeODMsTakTPoKWEEPR3VgVEdgCkWdITmEoFpFY9MDL7iC76ytVKEpTuqKaq8slqcegOoFc+cSsQ4EMb2yY36+SGlwv4T3BsJXlSvnKjz4l8DtmD64/XU+N1Gr9Z5Fmi1mL8gLUOG4DCJJUiVJbXEW29RVQHeQWxPK4C0xg9REaXyO33DwcMykRs6wD+A2Z8kcM1XV7qt+6LF24Ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=IX1vbkd0o8jV6H+x5mOP27LqWJmXLcEj+g6WPvyElDE=; b=SJ/rPXByU8U6Wf+tfMAMtsCtn7oJg2jrKswFZnuhl1NpcAzVk9dcLl1nly5YVt8F3p5bf7+p7upUluVvlR6YQ7ApYjlH1PD6AYP4HmL+MjqvbcHwmQZ0ekToqo4aqJZTTvsJ7uR7gHTZuYA3O3m99A0NCudjo6YBpEcA39iKvq5yhVGr1AM3eskHbVYeBUtrloJ9QHY59mqyuczGBew+a951PQffzX7mN/RwyvLnMMTe9OgHfKjmJw+Bl+wUNLbfXrdwlMOgihGv5kb9EDldrKFNIZWftxl4k0WCsjAtHh+VsAvI84N3/PPcRdXSKgh/jnTS6sCMe8VMG69pKhhwCw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=nongnu.org smtp.mailfrom=xilinx.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IX1vbkd0o8jV6H+x5mOP27LqWJmXLcEj+g6WPvyElDE=; b=lFjtTGWNSLl6PTa1FnEz3dRQ4WV8vIAln5+V8CFj+flV5qmVobLAYxtqLHpYrUt+5KMVF/FoE75inU+v2ZQYAIIH6A2btM6AzAWoEjgU+puKv+Q6X7lvHXSdl2nws/k/iXU3ySA4nRCiEmqYyXxiwQgf/2h775NZhTXOCo3Fdo4= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch01.xlnx.xilinx.com; From: Francisco Iglesias To: Subject: [PATCH v2 06/10] hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller Date: Tue, 23 Nov 2021 10:34:24 +0000 Message-ID: <20211123103428.8765-7-francisco.iglesias@xilinx.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20211123103428.8765-1-francisco.iglesias@xilinx.com> References: <20211123103428.8765-1-francisco.iglesias@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b8ced71f-eaf9-485a-7740-08d9ae6cdc04 X-MS-TrafficTypeDiagnostic: BYAPR02MB4871: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:3513; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PrNy8lSCUVpzCnwXiswv7IqUR2d6etY7o2tiJvuqUfG2EZpS1SaoTRSPitDxubXTmmE34MIDQqbMkfjKHXxtcebEV8HfIjlxVWfozrCAmdJYYYSBOCcC7Us4oIcNxRjaNzSyG9AHkRIpBzFxrsBwR+swnmN1PvO4TMs1Lr3LCKjCf89Z17AU4Hf6ZpGXyS/V+q5/sCB3b9vDNPgzOjycKo8/DVSuUoWZghBE2fTdCFBZ84AhnCtT1qmameJ+IsJEfDWPfb0qhPvDnUi0OvE3dK1aIIxZUYYJzIrEc43BIoXLFxTcVEBjtl/PTSyq82JKTUbbISxrACAzp0Isl7a5oI8hqvRdPii0Ssc2eZGC877JL0CNtu1q4FbG+nOE5TziDH1X8YcxKXsaviUcoLKvljUa5Zi9zjRpvvgZE15uSlBx5thniiuWHvSVBc11OirGMLwDsUUd+7GZLnjrf02VgCtmW3eiUNmnrZ//3c84S1Th4dv1aPcjEUDsUoyUBALKh75GdZRlRhUQ2cFK160F3rQQY4tAN9NSPZ589wIVXOi0aw9/Df9WknF84y5eRJJySSe1/SGA3OL4mv9wX9mIJ8RdiAIMDLjMyGdSEhlAF4jA/iiaPy7/Hvy7fRsG+6Uoi145M/eKHDUiugktzVqkImpjqh1f5bwfDCx0fCrIxjQ5jO35I8sPp3LuUibCrxwiQ6y4vNE+5oBfxMiMM1n9eNpoMqDRr6tgY9RNLCqS/Eo= X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch01.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(36840700001)(46966006)(36756003)(30864003)(70586007)(6916009)(36906005)(316002)(4326008)(9786002)(7696005)(2906002)(1076003)(356005)(26005)(70206006)(54906003)(508600001)(83380400001)(2616005)(336012)(6666004)(8936002)(5660300002)(36860700001)(7636003)(186003)(47076005)(426003)(82310400004)(8676002)(44832011)(102446001)(559001)(579004); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2021 10:34:41.9707 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b8ced71f-eaf9-485a-7740-08d9ae6cdc04 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT023.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB4871 Received-SPF: pass client-ip=40.107.92.67; envelope-from=figlesia@xilinx.com; helo=NAM10-BN7-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, peter.maydell@linaro.org, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1637663826498100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a model of Xilinx Versal's OSPI flash memory controller. Signed-off-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias --- hw/ssi/meson.build | 1 + hw/ssi/xlnx-versal-ospi.c | 1892 +++++++++++++++++++++++++++++++++= ++++ include/hw/ssi/xlnx-versal-ospi.h | 86 ++ 3 files changed, 1979 insertions(+) create mode 100644 hw/ssi/xlnx-versal-ospi.c create mode 100644 include/hw/ssi/xlnx-versal-ospi.h diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build index 3d6bc82ab1..0ded9cd092 100644 --- a/hw/ssi/meson.build +++ b/hw/ssi/meson.build @@ -7,5 +7,6 @@ softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_SPI', if_true: files('stm32f2xx_spi= .c')) softmmu_ss.add(when: 'CONFIG_XILINX_SPI', if_true: files('xilinx_spi.c')) softmmu_ss.add(when: 'CONFIG_XILINX_SPIPS', if_true: files('xilinx_spips.c= ')) +softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-osp= i.c')) softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_spi.c')) softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_spi.c')) diff --git a/hw/ssi/xlnx-versal-ospi.c b/hw/ssi/xlnx-versal-ospi.c new file mode 100644 index 0000000000..c02fc143de --- /dev/null +++ b/hw/ssi/xlnx-versal-ospi.c @@ -0,0 +1,1892 @@ +/* + * QEMU model of Xilinx Versal's OSPI controller. + * + * Copyright (c) 2021 Xilinx Inc. + * Written by Francisco Iglesias + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "hw/irq.h" +#include "hw/ssi/xlnx-versal-ospi.h" + +#ifndef XILINX_VERSAL_OSPI_ERR_DEBUG +#define XILINX_VERSAL_OSPI_ERR_DEBUG 0 +#endif + +REG32(CONFIG_REG, 0x0) + FIELD(CONFIG_REG, IDLE_FLD, 31, 1) + FIELD(CONFIG_REG, DUAL_BYTE_OPCODE_EN_FLD, 30, 1) + FIELD(CONFIG_REG, CRC_ENABLE_FLD, 29, 1) + FIELD(CONFIG_REG, CONFIG_RESV2_FLD, 26, 3) + FIELD(CONFIG_REG, PIPELINE_PHY_FLD, 25, 1) + FIELD(CONFIG_REG, ENABLE_DTR_PROTOCOL_FLD, 24, 1) + FIELD(CONFIG_REG, ENABLE_AHB_DECODER_FLD, 23, 1) + FIELD(CONFIG_REG, MSTR_BAUD_DIV_FLD, 19, 4) + FIELD(CONFIG_REG, ENTER_XIP_MODE_IMM_FLD, 18, 1) + FIELD(CONFIG_REG, ENTER_XIP_MODE_FLD, 17, 1) + FIELD(CONFIG_REG, ENB_AHB_ADDR_REMAP_FLD, 16, 1) + FIELD(CONFIG_REG, ENB_DMA_IF_FLD, 15, 1) + FIELD(CONFIG_REG, WR_PROT_FLASH_FLD, 14, 1) + FIELD(CONFIG_REG, PERIPH_CS_LINES_FLD, 10, 4) + FIELD(CONFIG_REG, PERIPH_SEL_DEC_FLD, 9, 1) + FIELD(CONFIG_REG, ENB_LEGACY_IP_MODE_FLD, 8, 1) + FIELD(CONFIG_REG, ENB_DIR_ACC_CTLR_FLD, 7, 1) + FIELD(CONFIG_REG, RESET_CFG_FLD, 6, 1) + FIELD(CONFIG_REG, RESET_PIN_FLD, 5, 1) + FIELD(CONFIG_REG, HOLD_PIN_FLD, 4, 1) + FIELD(CONFIG_REG, PHY_MODE_ENABLE_FLD, 3, 1) + FIELD(CONFIG_REG, SEL_CLK_PHASE_FLD, 2, 1) + FIELD(CONFIG_REG, SEL_CLK_POL_FLD, 1, 1) + FIELD(CONFIG_REG, ENB_SPI_FLD, 0, 1) +REG32(DEV_INSTR_RD_CONFIG_REG, 0x4) + FIELD(DEV_INSTR_RD_CONFIG_REG, RD_INSTR_RESV5_FLD, 29, 3) + FIELD(DEV_INSTR_RD_CONFIG_REG, DUMMY_RD_CLK_CYCLES_FLD, 24, 5) + FIELD(DEV_INSTR_RD_CONFIG_REG, RD_INSTR_RESV4_FLD, 21, 3) + FIELD(DEV_INSTR_RD_CONFIG_REG, MODE_BIT_ENABLE_FLD, 20, 1) + FIELD(DEV_INSTR_RD_CONFIG_REG, RD_INSTR_RESV3_FLD, 18, 2) + FIELD(DEV_INSTR_RD_CONFIG_REG, DATA_XFER_TYPE_EXT_MODE_FLD, 16, 2) + FIELD(DEV_INSTR_RD_CONFIG_REG, RD_INSTR_RESV2_FLD, 14, 2) + FIELD(DEV_INSTR_RD_CONFIG_REG, ADDR_XFER_TYPE_STD_MODE_FLD, 12, 2) + FIELD(DEV_INSTR_RD_CONFIG_REG, PRED_DIS_FLD, 11, 1) + FIELD(DEV_INSTR_RD_CONFIG_REG, DDR_EN_FLD, 10, 1) + FIELD(DEV_INSTR_RD_CONFIG_REG, INSTR_TYPE_FLD, 8, 2) + FIELD(DEV_INSTR_RD_CONFIG_REG, RD_OPCODE_NON_XIP_FLD, 0, 8) +REG32(DEV_INSTR_WR_CONFIG_REG, 0x8) + FIELD(DEV_INSTR_WR_CONFIG_REG, WR_INSTR_RESV4_FLD, 29, 3) + FIELD(DEV_INSTR_WR_CONFIG_REG, DUMMY_WR_CLK_CYCLES_FLD, 24, 5) + FIELD(DEV_INSTR_WR_CONFIG_REG, WR_INSTR_RESV3_FLD, 18, 6) + FIELD(DEV_INSTR_WR_CONFIG_REG, DATA_XFER_TYPE_EXT_MODE_FLD, 16, 2) + FIELD(DEV_INSTR_WR_CONFIG_REG, WR_INSTR_RESV2_FLD, 14, 2) + FIELD(DEV_INSTR_WR_CONFIG_REG, ADDR_XFER_TYPE_STD_MODE_FLD, 12, 2) + FIELD(DEV_INSTR_WR_CONFIG_REG, WR_INSTR_RESV1_FLD, 9, 3) + FIELD(DEV_INSTR_WR_CONFIG_REG, WEL_DIS_FLD, 8, 1) + FIELD(DEV_INSTR_WR_CONFIG_REG, WR_OPCODE_FLD, 0, 8) +REG32(DEV_DELAY_REG, 0xc) + FIELD(DEV_DELAY_REG, D_NSS_FLD, 24, 8) + FIELD(DEV_DELAY_REG, D_BTWN_FLD, 16, 8) + FIELD(DEV_DELAY_REG, D_AFTER_FLD, 8, 8) + FIELD(DEV_DELAY_REG, D_INIT_FLD, 0, 8) +REG32(RD_DATA_CAPTURE_REG, 0x10) + FIELD(RD_DATA_CAPTURE_REG, RD_DATA_RESV3_FLD, 20, 12) + FIELD(RD_DATA_CAPTURE_REG, DDR_READ_DELAY_FLD, 16, 4) + FIELD(RD_DATA_CAPTURE_REG, RD_DATA_RESV2_FLD, 9, 7) + FIELD(RD_DATA_CAPTURE_REG, DQS_ENABLE_FLD, 8, 1) + FIELD(RD_DATA_CAPTURE_REG, RD_DATA_RESV1_FLD, 6, 2) + FIELD(RD_DATA_CAPTURE_REG, SAMPLE_EDGE_SEL_FLD, 5, 1) + FIELD(RD_DATA_CAPTURE_REG, DELAY_FLD, 1, 4) + FIELD(RD_DATA_CAPTURE_REG, BYPASS_FLD, 0, 1) +REG32(DEV_SIZE_CONFIG_REG, 0x14) + FIELD(DEV_SIZE_CONFIG_REG, DEV_SIZE_RESV_FLD, 29, 3) + FIELD(DEV_SIZE_CONFIG_REG, MEM_SIZE_ON_CS3_FLD, 27, 2) + FIELD(DEV_SIZE_CONFIG_REG, MEM_SIZE_ON_CS2_FLD, 25, 2) + FIELD(DEV_SIZE_CONFIG_REG, MEM_SIZE_ON_CS1_FLD, 23, 2) + FIELD(DEV_SIZE_CONFIG_REG, MEM_SIZE_ON_CS0_FLD, 21, 2) + FIELD(DEV_SIZE_CONFIG_REG, BYTES_PER_SUBSECTOR_FLD, 16, 5) + FIELD(DEV_SIZE_CONFIG_REG, BYTES_PER_DEVICE_PAGE_FLD, 4, 12) + FIELD(DEV_SIZE_CONFIG_REG, NUM_ADDR_BYTES_FLD, 0, 4) +REG32(SRAM_PARTITION_CFG_REG, 0x18) + FIELD(SRAM_PARTITION_CFG_REG, SRAM_PARTITION_RESV_FLD, 8, 24) + FIELD(SRAM_PARTITION_CFG_REG, ADDR_FLD, 0, 8) +REG32(IND_AHB_ADDR_TRIGGER_REG, 0x1c) +REG32(DMA_PERIPH_CONFIG_REG, 0x20) + FIELD(DMA_PERIPH_CONFIG_REG, DMA_PERIPH_RESV2_FLD, 12, 20) + FIELD(DMA_PERIPH_CONFIG_REG, NUM_BURST_REQ_BYTES_FLD, 8, 4) + FIELD(DMA_PERIPH_CONFIG_REG, DMA_PERIPH_RESV1_FLD, 4, 4) + FIELD(DMA_PERIPH_CONFIG_REG, NUM_SINGLE_REQ_BYTES_FLD, 0, 4) +REG32(REMAP_ADDR_REG, 0x24) +REG32(MODE_BIT_CONFIG_REG, 0x28) + FIELD(MODE_BIT_CONFIG_REG, RX_CRC_DATA_LOW_FLD, 24, 8) + FIELD(MODE_BIT_CONFIG_REG, RX_CRC_DATA_UP_FLD, 16, 8) + FIELD(MODE_BIT_CONFIG_REG, CRC_OUT_ENABLE_FLD, 15, 1) + FIELD(MODE_BIT_CONFIG_REG, MODE_BIT_RESV1_FLD, 11, 4) + FIELD(MODE_BIT_CONFIG_REG, CHUNK_SIZE_FLD, 8, 3) + FIELD(MODE_BIT_CONFIG_REG, MODE_FLD, 0, 8) +REG32(SRAM_FILL_REG, 0x2c) + FIELD(SRAM_FILL_REG, SRAM_FILL_INDAC_WRITE_FLD, 16, 16) + FIELD(SRAM_FILL_REG, SRAM_FILL_INDAC_READ_FLD, 0, 16) +REG32(TX_THRESH_REG, 0x30) + FIELD(TX_THRESH_REG, TX_THRESH_RESV_FLD, 5, 27) + FIELD(TX_THRESH_REG, LEVEL_FLD, 0, 5) +REG32(RX_THRESH_REG, 0x34) + FIELD(RX_THRESH_REG, RX_THRESH_RESV_FLD, 5, 27) + FIELD(RX_THRESH_REG, LEVEL_FLD, 0, 5) +REG32(WRITE_COMPLETION_CTRL_REG, 0x38) + FIELD(WRITE_COMPLETION_CTRL_REG, POLL_REP_DELAY_FLD, 24, 8) + FIELD(WRITE_COMPLETION_CTRL_REG, POLL_COUNT_FLD, 16, 8) + FIELD(WRITE_COMPLETION_CTRL_REG, ENABLE_POLLING_EXP_FLD, 15, 1) + FIELD(WRITE_COMPLETION_CTRL_REG, DISABLE_POLLING_FLD, 14, 1) + FIELD(WRITE_COMPLETION_CTRL_REG, POLLING_POLARITY_FLD, 13, 1) + FIELD(WRITE_COMPLETION_CTRL_REG, WR_COMP_CTRL_RESV1_FLD, 12, 1) + FIELD(WRITE_COMPLETION_CTRL_REG, POLLING_ADDR_EN_FLD, 11, 1) + FIELD(WRITE_COMPLETION_CTRL_REG, POLLING_BIT_INDEX_FLD, 8, 3) + FIELD(WRITE_COMPLETION_CTRL_REG, OPCODE_FLD, 0, 8) +REG32(NO_OF_POLLS_BEF_EXP_REG, 0x3c) +REG32(IRQ_STATUS_REG, 0x40) + FIELD(IRQ_STATUS_REG, IRQ_STAT_RESV_FLD, 20, 12) + FIELD(IRQ_STATUS_REG, ECC_FAIL_FLD, 19, 1) + FIELD(IRQ_STATUS_REG, TX_CRC_CHUNK_BRK_FLD, 18, 1) + FIELD(IRQ_STATUS_REG, RX_CRC_DATA_VAL_FLD, 17, 1) + FIELD(IRQ_STATUS_REG, RX_CRC_DATA_ERR_FLD, 16, 1) + FIELD(IRQ_STATUS_REG, IRQ_STAT_RESV1_FLD, 15, 1) + FIELD(IRQ_STATUS_REG, STIG_REQ_INT_FLD, 14, 1) + FIELD(IRQ_STATUS_REG, POLL_EXP_INT_FLD, 13, 1) + FIELD(IRQ_STATUS_REG, INDRD_SRAM_FULL_FLD, 12, 1) + FIELD(IRQ_STATUS_REG, RX_FIFO_FULL_FLD, 11, 1) + FIELD(IRQ_STATUS_REG, RX_FIFO_NOT_EMPTY_FLD, 10, 1) + FIELD(IRQ_STATUS_REG, TX_FIFO_FULL_FLD, 9, 1) + FIELD(IRQ_STATUS_REG, TX_FIFO_NOT_FULL_FLD, 8, 1) + FIELD(IRQ_STATUS_REG, RECV_OVERFLOW_FLD, 7, 1) + FIELD(IRQ_STATUS_REG, INDIRECT_XFER_LEVEL_BREACH_FLD, 6, 1) + FIELD(IRQ_STATUS_REG, ILLEGAL_ACCESS_DET_FLD, 5, 1) + FIELD(IRQ_STATUS_REG, PROT_WR_ATTEMPT_FLD, 4, 1) + FIELD(IRQ_STATUS_REG, INDIRECT_TRANSFER_REJECT_FLD, 3, 1) + FIELD(IRQ_STATUS_REG, INDIRECT_OP_DONE_FLD, 2, 1) + FIELD(IRQ_STATUS_REG, UNDERFLOW_DET_FLD, 1, 1) + FIELD(IRQ_STATUS_REG, MODE_M_FAIL_FLD, 0, 1) +REG32(IRQ_MASK_REG, 0x44) + FIELD(IRQ_MASK_REG, IRQ_MASK_RESV_FLD, 20, 12) + FIELD(IRQ_MASK_REG, ECC_FAIL_MASK_FLD, 19, 1) + FIELD(IRQ_MASK_REG, TX_CRC_CHUNK_BRK_MASK_FLD, 18, 1) + FIELD(IRQ_MASK_REG, RX_CRC_DATA_VAL_MASK_FLD, 17, 1) + FIELD(IRQ_MASK_REG, RX_CRC_DATA_ERR_MASK_FLD, 16, 1) + FIELD(IRQ_MASK_REG, IRQ_MASK_RESV1_FLD, 15, 1) + FIELD(IRQ_MASK_REG, STIG_REQ_MASK_FLD, 14, 1) + FIELD(IRQ_MASK_REG, POLL_EXP_INT_MASK_FLD, 13, 1) + FIELD(IRQ_MASK_REG, INDRD_SRAM_FULL_MASK_FLD, 12, 1) + FIELD(IRQ_MASK_REG, RX_FIFO_FULL_MASK_FLD, 11, 1) + FIELD(IRQ_MASK_REG, RX_FIFO_NOT_EMPTY_MASK_FLD, 10, 1) + FIELD(IRQ_MASK_REG, TX_FIFO_FULL_MASK_FLD, 9, 1) + FIELD(IRQ_MASK_REG, TX_FIFO_NOT_FULL_MASK_FLD, 8, 1) + FIELD(IRQ_MASK_REG, RECV_OVERFLOW_MASK_FLD, 7, 1) + FIELD(IRQ_MASK_REG, INDIRECT_XFER_LEVEL_BREACH_MASK_FLD, 6, 1) + FIELD(IRQ_MASK_REG, ILLEGAL_ACCESS_DET_MASK_FLD, 5, 1) + FIELD(IRQ_MASK_REG, PROT_WR_ATTEMPT_MASK_FLD, 4, 1) + FIELD(IRQ_MASK_REG, INDIRECT_TRANSFER_REJECT_MASK_FLD, 3, 1) + FIELD(IRQ_MASK_REG, INDIRECT_OP_DONE_MASK_FLD, 2, 1) + FIELD(IRQ_MASK_REG, UNDERFLOW_DET_MASK_FLD, 1, 1) + FIELD(IRQ_MASK_REG, MODE_M_FAIL_MASK_FLD, 0, 1) +REG32(LOWER_WR_PROT_REG, 0x50) +REG32(UPPER_WR_PROT_REG, 0x54) +REG32(WR_PROT_CTRL_REG, 0x58) + FIELD(WR_PROT_CTRL_REG, WR_PROT_CTRL_RESV_FLD, 2, 30) + FIELD(WR_PROT_CTRL_REG, ENB_FLD, 1, 1) + FIELD(WR_PROT_CTRL_REG, INV_FLD, 0, 1) +REG32(INDIRECT_READ_XFER_CTRL_REG, 0x60) + FIELD(INDIRECT_READ_XFER_CTRL_REG, INDIR_RD_XFER_RESV_FLD, 8, 24) + FIELD(INDIRECT_READ_XFER_CTRL_REG, NUM_IND_OPS_DONE_FLD, 6, 2) + FIELD(INDIRECT_READ_XFER_CTRL_REG, IND_OPS_DONE_STATUS_FLD, 5, 1) + FIELD(INDIRECT_READ_XFER_CTRL_REG, RD_QUEUED_FLD, 4, 1) + FIELD(INDIRECT_READ_XFER_CTRL_REG, SRAM_FULL_FLD, 3, 1) + FIELD(INDIRECT_READ_XFER_CTRL_REG, RD_STATUS_FLD, 2, 1) + FIELD(INDIRECT_READ_XFER_CTRL_REG, CANCEL_FLD, 1, 1) + FIELD(INDIRECT_READ_XFER_CTRL_REG, START_FLD, 0, 1) +REG32(INDIRECT_READ_XFER_WATERMARK_REG, 0x64) +REG32(INDIRECT_READ_XFER_START_REG, 0x68) +REG32(INDIRECT_READ_XFER_NUM_BYTES_REG, 0x6c) +REG32(INDIRECT_WRITE_XFER_CTRL_REG, 0x70) + FIELD(INDIRECT_WRITE_XFER_CTRL_REG, INDIR_WR_XFER_RESV2_FLD, 8, 24) + FIELD(INDIRECT_WRITE_XFER_CTRL_REG, NUM_IND_OPS_DONE_FLD, 6, 2) + FIELD(INDIRECT_WRITE_XFER_CTRL_REG, IND_OPS_DONE_STATUS_FLD, 5, 1) + FIELD(INDIRECT_WRITE_XFER_CTRL_REG, WR_QUEUED_FLD, 4, 1) + FIELD(INDIRECT_WRITE_XFER_CTRL_REG, INDIR_WR_XFER_RESV1_FLD, 3, 1) + FIELD(INDIRECT_WRITE_XFER_CTRL_REG, WR_STATUS_FLD, 2, 1) + FIELD(INDIRECT_WRITE_XFER_CTRL_REG, CANCEL_FLD, 1, 1) + FIELD(INDIRECT_WRITE_XFER_CTRL_REG, START_FLD, 0, 1) +REG32(INDIRECT_WRITE_XFER_WATERMARK_REG, 0x74) +REG32(INDIRECT_WRITE_XFER_START_REG, 0x78) +REG32(INDIRECT_WRITE_XFER_NUM_BYTES_REG, 0x7c) +REG32(INDIRECT_TRIGGER_ADDR_RANGE_REG, 0x80) + FIELD(INDIRECT_TRIGGER_ADDR_RANGE_REG, IND_RANGE_RESV1_FLD, 4, 28) + FIELD(INDIRECT_TRIGGER_ADDR_RANGE_REG, IND_RANGE_WIDTH_FLD, 0, 4) +REG32(FLASH_COMMAND_CTRL_MEM_REG, 0x8c) + FIELD(FLASH_COMMAND_CTRL_MEM_REG, FLASH_COMMAND_CTRL_MEM_RESV1_FLD, 29= , 3) + FIELD(FLASH_COMMAND_CTRL_MEM_REG, MEM_BANK_ADDR_FLD, 20, 9) + FIELD(FLASH_COMMAND_CTRL_MEM_REG, FLASH_COMMAND_CTRL_MEM_RESV2_FLD, 19= , 1) + FIELD(FLASH_COMMAND_CTRL_MEM_REG, NB_OF_STIG_READ_BYTES_FLD, 16, 3) + FIELD(FLASH_COMMAND_CTRL_MEM_REG, MEM_BANK_READ_DATA_FLD, 8, 8) + FIELD(FLASH_COMMAND_CTRL_MEM_REG, FLASH_COMMAND_CTRL_MEM_RESV3_FLD, 2,= 6) + FIELD(FLASH_COMMAND_CTRL_MEM_REG, MEM_BANK_REQ_IN_PROGRESS_FLD, 1, 1) + FIELD(FLASH_COMMAND_CTRL_MEM_REG, TRIGGER_MEM_BANK_REQ_FLD, 0, 1) +REG32(FLASH_CMD_CTRL_REG, 0x90) + FIELD(FLASH_CMD_CTRL_REG, CMD_OPCODE_FLD, 24, 8) + FIELD(FLASH_CMD_CTRL_REG, ENB_READ_DATA_FLD, 23, 1) + FIELD(FLASH_CMD_CTRL_REG, NUM_RD_DATA_BYTES_FLD, 20, 3) + FIELD(FLASH_CMD_CTRL_REG, ENB_COMD_ADDR_FLD, 19, 1) + FIELD(FLASH_CMD_CTRL_REG, ENB_MODE_BIT_FLD, 18, 1) + FIELD(FLASH_CMD_CTRL_REG, NUM_ADDR_BYTES_FLD, 16, 2) + FIELD(FLASH_CMD_CTRL_REG, ENB_WRITE_DATA_FLD, 15, 1) + FIELD(FLASH_CMD_CTRL_REG, NUM_WR_DATA_BYTES_FLD, 12, 3) + FIELD(FLASH_CMD_CTRL_REG, NUM_DUMMY_CYCLES_FLD, 7, 5) + FIELD(FLASH_CMD_CTRL_REG, FLASH_CMD_CTRL_RESV1_FLD, 3, 4) + FIELD(FLASH_CMD_CTRL_REG, STIG_MEM_BANK_EN_FLD, 2, 1) + FIELD(FLASH_CMD_CTRL_REG, CMD_EXEC_STATUS_FLD, 1, 1) + FIELD(FLASH_CMD_CTRL_REG, CMD_EXEC_FLD, 0, 1) +REG32(FLASH_CMD_ADDR_REG, 0x94) +REG32(FLASH_RD_DATA_LOWER_REG, 0xa0) +REG32(FLASH_RD_DATA_UPPER_REG, 0xa4) +REG32(FLASH_WR_DATA_LOWER_REG, 0xa8) +REG32(FLASH_WR_DATA_UPPER_REG, 0xac) +REG32(POLLING_FLASH_STATUS_REG, 0xb0) + FIELD(POLLING_FLASH_STATUS_REG, DEVICE_STATUS_RSVD_FLD2, 21, 11) + FIELD(POLLING_FLASH_STATUS_REG, DEVICE_STATUS_NB_DUMMY, 16, 5) + FIELD(POLLING_FLASH_STATUS_REG, DEVICE_STATUS_RSVD_FLD1, 9, 7) + FIELD(POLLING_FLASH_STATUS_REG, DEVICE_STATUS_VALID_FLD, 8, 1) + FIELD(POLLING_FLASH_STATUS_REG, DEVICE_STATUS_FLD, 0, 8) +REG32(PHY_CONFIGURATION_REG, 0xb4) + FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_RESYNC_FLD, 31, 1) + FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_RESET_FLD, 30, 1) + FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_RX_DLL_BYPASS_FLD, 29, 1) + FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_RESV2_FLD, 23, 6) + FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_TX_DLL_DELAY_FLD, 16, 7) + FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_RESV1_FLD, 7, 9) + FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_RX_DLL_DELAY_FLD, 0, 7) +REG32(PHY_MASTER_CONTROL_REG, 0xb8) + FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_CONTROL_RESV3_FLD, 25, 7) + FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_LOCK_MODE_FLD, 24, 1) + FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_BYPASS_MODE_FLD, 23, 1) + FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_PHASE_DETECT_SELECTOR_FLD, 20= , 3) + FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_CONTROL_RESV2_FLD, 19, 1) + FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_NB_INDICATIONS_FLD, 16, 3) + FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_CONTROL_RESV1_FLD, 7, 9) + FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_INITIAL_DELAY_FLD, 0, 7) +REG32(DLL_OBSERVABLE_LOWER_REG, 0xbc) + FIELD(DLL_OBSERVABLE_LOWER_REG, + DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD, 24, 8) + FIELD(DLL_OBSERVABLE_LOWER_REG, + DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD, 16, 8) + FIELD(DLL_OBSERVABLE_LOWER_REG, + DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD, 15, 1) + FIELD(DLL_OBSERVABLE_LOWER_REG, + DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD, 8, 7) + FIELD(DLL_OBSERVABLE_LOWER_REG, + DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD, 3, 5) + FIELD(DLL_OBSERVABLE_LOWER_REG, + DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD, 1, 2) + FIELD(DLL_OBSERVABLE_LOWER_REG, + DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD, 0, 1) +REG32(DLL_OBSERVABLE_UPPER_REG, 0xc0) + FIELD(DLL_OBSERVABLE_UPPER_REG, + DLL_OBSERVABLE_UPPER_RESV2_FLD, 23, 9) + FIELD(DLL_OBSERVABLE_UPPER_REG, + DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD, 16, 7) + FIELD(DLL_OBSERVABLE_UPPER_REG, + DLL_OBSERVABLE_UPPER_RESV1_FLD, 7, 9) + FIELD(DLL_OBSERVABLE_UPPER_REG, + DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD, 0, 7) +REG32(OPCODE_EXT_LOWER_REG, 0xe0) + FIELD(OPCODE_EXT_LOWER_REG, EXT_READ_OPCODE_FLD, 24, 8) + FIELD(OPCODE_EXT_LOWER_REG, EXT_WRITE_OPCODE_FLD, 16, 8) + FIELD(OPCODE_EXT_LOWER_REG, EXT_POLL_OPCODE_FLD, 8, 8) + FIELD(OPCODE_EXT_LOWER_REG, EXT_STIG_OPCODE_FLD, 0, 8) +REG32(OPCODE_EXT_UPPER_REG, 0xe4) + FIELD(OPCODE_EXT_UPPER_REG, WEL_OPCODE_FLD, 24, 8) + FIELD(OPCODE_EXT_UPPER_REG, EXT_WEL_OPCODE_FLD, 16, 8) + FIELD(OPCODE_EXT_UPPER_REG, OPCODE_EXT_UPPER_RESV1_FLD, 0, 16) +REG32(MODULE_ID_REG, 0xfc) + FIELD(MODULE_ID_REG, FIX_PATCH_FLD, 24, 8) + FIELD(MODULE_ID_REG, MODULE_ID_FLD, 8, 16) + FIELD(MODULE_ID_REG, MODULE_ID_RESV_FLD, 2, 6) + FIELD(MODULE_ID_REG, CONF_FLD, 0, 2) + +#define RXFF_SZ 1024 +#define TXFF_SZ 1024 + +#define MAX_RX_DEC_OUT 8 + +#define SZ_512MBIT (512 * 1024 * 1024) +#define SZ_1GBIT (1024 * 1024 * 1024) +#define SZ_2GBIT (2ULL * SZ_1GBIT) +#define SZ_4GBIT (4ULL * SZ_1GBIT) + +#define IS_IND_DMA_START(op) (op->done_bytes =3D=3D 0) +/* + * Bit field size of R_INDIRECT_WRITE_XFER_CTRL_REG_NUM_IND_OPS_DONE_FLD + * is 2 bits, which can record max of 3 indac operations. + */ +#define IND_OPS_DONE_MAX 3 + +typedef enum { + WREN =3D 0x6, +} FlashCMD; + +/* Type to avoid cpu endian byte swaps */ +typedef union { + uint64_t u64; + uint8_t u8[8]; +} OSPIRdData; + +static unsigned int ospi_stig_addr_len(XlnxVersalOspi *s) +{ + /* Num address bytes is NUM_ADDR_BYTES_FLD + 1 */ + return ARRAY_FIELD_EX32(s->regs, + FLASH_CMD_CTRL_REG, NUM_ADDR_BYTES_FLD) + 1; +} + +static unsigned int ospi_stig_wr_data_len(XlnxVersalOspi *s) +{ + /* Num write data bytes is NUM_WR_DATA_BYTES_FLD + 1 */ + return ARRAY_FIELD_EX32(s->regs, + FLASH_CMD_CTRL_REG, NUM_WR_DATA_BYTES_FLD) + 1; +} + +static unsigned int ospi_stig_rd_data_len(XlnxVersalOspi *s) +{ + /* Num read data bytes is NUM_RD_DATA_BYTES_FLD + 1 */ + return ARRAY_FIELD_EX32(s->regs, + FLASH_CMD_CTRL_REG, NUM_RD_DATA_BYTES_FLD) + 1; +} + +/* + * Status bits in R_IRQ_STATUS_REG are set when the event occurs and the + * interrupt is enabled in the mask register ([1] Section 2.3.17) + */ +static void set_irq(XlnxVersalOspi *s, uint32_t set_mask) +{ + s->regs[R_IRQ_STATUS_REG] |=3D s->regs[R_IRQ_MASK_REG] & set_mask; +} + +static void ospi_update_irq_line(XlnxVersalOspi *s) +{ + qemu_set_irq(s->irq, !!(s->regs[R_IRQ_STATUS_REG] & + s->regs[R_IRQ_MASK_REG])); +} + +static uint8_t ospi_get_wr_opcode(XlnxVersalOspi *s) +{ + return ARRAY_FIELD_EX32(s->regs, + DEV_INSTR_WR_CONFIG_REG, WR_OPCODE_FLD); +} + +static uint8_t ospi_get_rd_opcode(XlnxVersalOspi *s) +{ + return ARRAY_FIELD_EX32(s->regs, + DEV_INSTR_RD_CONFIG_REG, RD_OPCODE_NON_XIP_FLD= ); +} + +static uint32_t ospi_get_num_addr_bytes(XlnxVersalOspi *s) +{ + /* Num address bytes is NUM_ADDR_BYTES_FLD + 1 */ + return ARRAY_FIELD_EX32(s->regs, + DEV_SIZE_CONFIG_REG, NUM_ADDR_BYTES_FLD) + 1; +} + +static void ospi_stig_membank_req(XlnxVersalOspi *s) +{ + int idx =3D ARRAY_FIELD_EX32(s->regs, + FLASH_COMMAND_CTRL_MEM_REG, MEM_BANK_ADDR_F= LD); + + ARRAY_FIELD_DP32(s->regs, FLASH_COMMAND_CTRL_MEM_REG, + MEM_BANK_READ_DATA_FLD, s->stig_membank[idx]); +} + +static int ospi_stig_membank_rd_bytes(XlnxVersalOspi *s) +{ + int rd_data_fld =3D ARRAY_FIELD_EX32(s->regs, FLASH_COMMAND_CTRL_MEM_R= EG, + NB_OF_STIG_READ_BYTES_FLD); + int sizes[6] =3D { 16, 32, 64, 128, 256, 512 }; + return (rd_data_fld < 6) ? sizes[rd_data_fld] : 0; +} + +static uint32_t ospi_get_page_sz(XlnxVersalOspi *s) +{ + return ARRAY_FIELD_EX32(s->regs, + DEV_SIZE_CONFIG_REG, BYTES_PER_DEVICE_PAGE_FLD= ); +} + +static bool ospi_ind_rd_watermark_enabled(XlnxVersalOspi *s) +{ + return s->regs[R_INDIRECT_READ_XFER_WATERMARK_REG]; +} + +static void ind_op_advance(IndOp *op, unsigned int len) +{ + op->done_bytes +=3D len; + assert(op->done_bytes <=3D op->num_bytes); + if (op->done_bytes =3D=3D op->num_bytes) { + op->completed =3D true; + } +} + +static uint32_t ind_op_next_byte(IndOp *op) +{ + return op->flash_addr + op->done_bytes; +} + +static uint32_t ind_op_end_byte(IndOp *op) +{ + return op->flash_addr + op->num_bytes; +} + +static void ospi_ind_op_next(IndOp *op) +{ + op[0] =3D op[1]; + op[1].completed =3D true; +} + +static void ind_op_setup(IndOp *op, uint32_t flash_addr, uint32_t num_byte= s) +{ + if (num_bytes & 0x3) { + qemu_log_mask(LOG_GUEST_ERROR, + "OSPI indirect op num bytes not word aligned\n"); + } + op->flash_addr =3D flash_addr; + op->num_bytes =3D num_bytes; + op->done_bytes =3D 0; + op->completed =3D false; +} + +static bool ospi_ind_op_completed(IndOp *op) +{ + return op->completed; +} + +static bool ospi_ind_op_all_completed(XlnxVersalOspi *s) +{ + return s->rd_ind_op[0].completed && s->wr_ind_op[0].completed; +} + +static void ospi_ind_op_cancel(IndOp *op) +{ + op[0].completed =3D true; + op[1].completed =3D true; +} + +static bool ospi_ind_op_add(IndOp *op, Fifo8 *fifo, + uint32_t flash_addr, uint32_t num_bytes) +{ + /* Check if first indirect op has been completed */ + if (op->completed) { + fifo8_reset(fifo); + ind_op_setup(op, flash_addr, num_bytes); + return false; + } + + /* Check if second indirect op has been completed */ + op++; + if (op->completed) { + ind_op_setup(op, flash_addr, num_bytes); + return false; + } + return true; +} + +static void ospi_ind_op_queue_up_rd(XlnxVersalOspi *s) +{ + uint32_t num_bytes =3D s->regs[R_INDIRECT_READ_XFER_NUM_BYTES_REG]; + uint32_t flash_addr =3D s->regs[R_INDIRECT_READ_XFER_START_REG]; + bool failed; + + failed =3D ospi_ind_op_add(s->rd_ind_op, &s->rx_sram, flash_addr, num_= bytes); + /* If two already queued set rd reject interrupt */ + if (failed) { + set_irq(s, R_IRQ_STATUS_REG_INDIRECT_TRANSFER_REJECT_FLD_MASK); + } +} + +static void ospi_ind_op_queue_up_wr(XlnxVersalOspi *s) +{ + uint32_t num_bytes =3D s->regs[R_INDIRECT_WRITE_XFER_NUM_BYTES_REG]; + uint32_t flash_addr =3D s->regs[R_INDIRECT_WRITE_XFER_START_REG]; + bool failed; + + failed =3D ospi_ind_op_add(s->wr_ind_op, &s->tx_sram, flash_addr, num_= bytes); + /* If two already queued set rd reject interrupt */ + if (failed) { + set_irq(s, R_IRQ_STATUS_REG_INDIRECT_TRANSFER_REJECT_FLD_MASK); + } +} + +static uint64_t flash_sz(XlnxVersalOspi *s, unsigned int cs) +{ + /* Flash sizes in MB */ + static const uint64_t sizes[4] =3D { SZ_512MBIT / 8, SZ_1GBIT / 8, + SZ_2GBIT / 8, SZ_4GBIT / 8 }; + uint32_t v =3D s->regs[R_DEV_SIZE_CONFIG_REG]; + + v >>=3D cs * R_DEV_SIZE_CONFIG_REG_MEM_SIZE_ON_CS0_FLD_LENGTH; + return sizes[FIELD_EX32(v, DEV_SIZE_CONFIG_REG, MEM_SIZE_ON_CS0_FLD)]; +} + +static unsigned int ospi_get_block_sz(XlnxVersalOspi *s) +{ + unsigned int block_fld =3D ARRAY_FIELD_EX32(s->regs, + DEV_SIZE_CONFIG_REG, + BYTES_PER_SUBSECTOR_FLD); + return 1 << block_fld; +} + +static unsigned int flash_blocks(XlnxVersalOspi *s, unsigned int cs) +{ + unsigned int b_sz =3D ospi_get_block_sz(s); + unsigned int f_sz =3D flash_sz(s, cs); + + return f_sz / b_sz; +} + +static int ospi_ahb_decoder_cs(XlnxVersalOspi *s, hwaddr addr) +{ + uint64_t end_addr =3D 0; + int cs; + + for (cs =3D 0; cs < s->num_cs; cs++) { + end_addr +=3D flash_sz(s, cs); + if (addr < end_addr) { + break; + } + } + + if (cs =3D=3D s->num_cs) { + /* Address is out of range */ + qemu_log_mask(LOG_GUEST_ERROR, + "OSPI flash address does not fit in configuraton\n"); + return -1; + } + return cs; +} + +static void ospi_ahb_decoder_enable_cs(XlnxVersalOspi *s, hwaddr addr) +{ + int cs =3D ospi_ahb_decoder_cs(s, addr); + + if (cs >=3D 0) { + for (int i =3D 0; i < s->num_cs; i++) { + if (cs =3D=3D i) { + qemu_set_irq(s->cs_lines[i], 0); + } else { + qemu_set_irq(s->cs_lines[i], 1); + } + } + } +} + +static unsigned int single_cs(XlnxVersalOspi *s) +{ + unsigned int field =3D ARRAY_FIELD_EX32(s->regs, + CONFIG_REG, PERIPH_CS_LINES_FLD); + int i; + + /* + * 4'bXXX0 -> 4'b1110 + * 4'bXX0X -> 4'b1101 + * 4'bX0XX -> 4'b1011 + * 4'b0XXX -> 4'b0111 + * 4'b1111 -> 4'b1111 + */ + for (i =3D 0; i < 4; i++) { + if ((field & (1 << i)) =3D=3D 0) { + return (~(1 << i)) & 0xF; + } + } + return 0; +} + +static void ospi_update_cs_lines(XlnxVersalOspi *s) +{ + unsigned int all_cs; + int i; + + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, PERIPH_SEL_DEC_FLD)) { + all_cs =3D ARRAY_FIELD_EX32(s->regs, CONFIG_REG, PERIPH_CS_LINES_F= LD); + } else { + all_cs =3D single_cs(s); + } + + for (i =3D 0; i < s->num_cs; i++) { + bool cs =3D (all_cs >> i) & 1; + + qemu_set_irq(s->cs_lines[i], cs); + } +} + +static void ospi_dac_cs(XlnxVersalOspi *s, hwaddr addr) +{ + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENABLE_AHB_DECODER_FLD)) { + ospi_ahb_decoder_enable_cs(s, addr); + } else { + ospi_update_cs_lines(s); + } +} + +static void ospi_disable_cs(XlnxVersalOspi *s) +{ + int i; + + for (i =3D 0; i < s->num_cs; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } +} + +static void ospi_flush_txfifo(XlnxVersalOspi *s) +{ + while (!fifo8_is_empty(&s->tx_fifo)) { + uint32_t tx_rx =3D fifo8_pop(&s->tx_fifo); + + tx_rx =3D ssi_transfer(s->spi, tx_rx); + fifo8_push(&s->rx_fifo, tx_rx); + } +} + +static void ospi_tx_fifo_push_address_raw(XlnxVersalOspi *s, + uint32_t flash_addr, + unsigned int addr_bytes) +{ + /* Push write address */ + if (addr_bytes =3D=3D 4) { + fifo8_push(&s->tx_fifo, flash_addr >> 24); + } + if (addr_bytes >=3D 3) { + fifo8_push(&s->tx_fifo, flash_addr >> 16); + } + if (addr_bytes >=3D 2) { + fifo8_push(&s->tx_fifo, flash_addr >> 8); + } + fifo8_push(&s->tx_fifo, flash_addr); +} + +static void ospi_tx_fifo_push_address(XlnxVersalOspi *s, uint32_t flash_ad= dr) +{ + /* Push write address */ + int addr_bytes =3D ospi_get_num_addr_bytes(s); + + ospi_tx_fifo_push_address_raw(s, flash_addr, addr_bytes); +} + +static void ospi_tx_fifo_push_stig_addr(XlnxVersalOspi *s) +{ + uint32_t flash_addr =3D s->regs[R_FLASH_CMD_ADDR_REG]; + unsigned int addr_bytes =3D ospi_stig_addr_len(s); + + ospi_tx_fifo_push_address_raw(s, flash_addr, addr_bytes); +} + +static void ospi_tx_fifo_push_rd_op_addr(XlnxVersalOspi *s, uint32_t flash= _addr) +{ + uint8_t inst_code =3D ospi_get_rd_opcode(s); + + fifo8_reset(&s->tx_fifo); + + /* Push read opcode */ + fifo8_push(&s->tx_fifo, inst_code); + + /* Push read address */ + ospi_tx_fifo_push_address(s, flash_addr); +} + +static void ospi_tx_fifo_push_stig_wr_data(XlnxVersalOspi *s) +{ + uint64_t data =3D s->regs[R_FLASH_WR_DATA_LOWER_REG]; + int wr_data_len =3D ospi_stig_wr_data_len(s); + int i; + + data |=3D (uint64_t) s->regs[R_FLASH_WR_DATA_UPPER_REG] << 32; + for (i =3D 0; i < wr_data_len; i++) { + int shift =3D i * 8; + fifo8_push(&s->tx_fifo, data >> shift); + } +} + +static void ospi_tx_fifo_push_stig_rd_data(XlnxVersalOspi *s) +{ + int rd_data_len; + int i; + + if (ARRAY_FIELD_EX32(s->regs, FLASH_CMD_CTRL_REG, STIG_MEM_BANK_EN_FLD= )) { + rd_data_len =3D ospi_stig_membank_rd_bytes(s); + } else { + rd_data_len =3D ospi_stig_rd_data_len(s); + } + + /* transmit second part (data) */ + for (i =3D 0; i < rd_data_len; ++i) { + fifo8_push(&s->tx_fifo, 0); + } +} + +static void ospi_rx_fifo_pop_stig_rd_data(XlnxVersalOspi *s) +{ + int size =3D ospi_stig_rd_data_len(s); + OSPIRdData res =3D {}; + int i; + + size =3D MIN(fifo8_num_used(&s->rx_fifo), size); + for (i =3D 0; i < size; i++) { + res.u8[i] =3D fifo8_pop(&s->rx_fifo); + } + + s->regs[R_FLASH_RD_DATA_LOWER_REG] =3D res.u64 & 0xFFFFFFFF; + s->regs[R_FLASH_RD_DATA_UPPER_REG] =3D (res.u64 >> 32) & 0xFFFFFFFF; +} + +static void ospi_ind_read(XlnxVersalOspi *s, uint32_t flash_addr, uint32_t= len) +{ + int i; + + /* Create first section of read cmd */ + ospi_tx_fifo_push_rd_op_addr(s, flash_addr); + + /* transmit first part */ + ospi_update_cs_lines(s); + ospi_flush_txfifo(s); + + fifo8_reset(&s->rx_fifo); + + /* transmit second part (data) */ + for (i =3D 0; i < len; ++i) { + fifo8_push(&s->tx_fifo, 0); + } + ospi_flush_txfifo(s); + + for (i =3D 0; i < len; ++i) { + fifo8_push(&s->rx_sram, fifo8_pop(&s->rx_fifo)); + } + + /* done */ + ospi_disable_cs(s); +} + +static unsigned int ospi_dma_burst_size(XlnxVersalOspi *s) +{ + return 1 << ARRAY_FIELD_EX32(s->regs, + DMA_PERIPH_CONFIG_REG, + NUM_BURST_REQ_BYTES_FLD); +} + +static unsigned int ospi_dma_single_size(XlnxVersalOspi *s) +{ + return 1 << ARRAY_FIELD_EX32(s->regs, + DMA_PERIPH_CONFIG_REG, + NUM_SINGLE_REQ_BYTES_FLD); +} + +static void ind_rd_inc_num_done(XlnxVersalOspi *s) +{ + unsigned int done =3D ARRAY_FIELD_EX32(s->regs, + INDIRECT_READ_XFER_CTRL_REG, + NUM_IND_OPS_DONE_FLD); + if (done < IND_OPS_DONE_MAX) { + done++; + } + done &=3D 0x3; + ARRAY_FIELD_DP32(s->regs, INDIRECT_READ_XFER_CTRL_REG, + NUM_IND_OPS_DONE_FLD, done); +} + +static void ospi_ind_rd_completed(XlnxVersalOspi *s) +{ + ARRAY_FIELD_DP32(s->regs, INDIRECT_READ_XFER_CTRL_REG, + IND_OPS_DONE_STATUS_FLD, 1); + + ind_rd_inc_num_done(s); + ospi_ind_op_next(s->rd_ind_op); + if (ospi_ind_op_all_completed(s)) { + set_irq(s, R_IRQ_STATUS_REG_INDIRECT_OP_DONE_FLD_MASK); + } +} + +static uint32_t get_ind_rd_dma_len(XlnxVersalOspi *s, IndOp *op) +{ + uint32_t len =3D 0; + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_DMA_IF_FLD)) { + if (fifo8_num_used(&s->rx_sram) < + ospi_dma_burst_size(s)) { + len =3D ospi_dma_single_size(s); + } else { + len =3D ospi_dma_burst_size(s); + } + } + return len; +} + +static void ospi_notify(void *opaque); + +static void ospi_dma_read(XlnxVersalOspi *s, bool start_dma) +{ + IndOp *op =3D s->rd_ind_op; + uint32_t dma_len; + uint32_t flush_bytes =3D fifo8_num_used(&s->rx_sram); + DmaCtrlNotify notify =3D { .cb =3D ospi_notify, + .opaque =3D (void *)s, + }; + + if (flush_bytes && !s->src_dma_inprog) { + dma_len =3D get_ind_rd_dma_len(s, op); + /* + * Source dma accesses SRAM at address 0 (at its own addresss spac= e). + */ + dma_ctrl_read_with_notify(s->dma_src, 0, dma_len, ¬ify, start_d= ma); + + /* + * ospi_dma_read is called for every call of ospi_notify + * in that case, by the time we are here, if flush_bytes is not ze= ro + * then we have pending dma transactions. + */ + flush_bytes =3D fifo8_num_used(&s->rx_sram); + if (flush_bytes) { + s->src_dma_inprog =3D true; + } + } +} + +static void ospi_do_ind_read(XlnxVersalOspi *s) +{ + IndOp *op =3D s->rd_ind_op; + uint32_t next_b; + uint32_t end_b; + uint32_t len; + bool start_dma =3D IS_IND_DMA_START(op); + + /* Continue to read flash until we run out of space in sram */ + while (!ospi_ind_op_completed(op) && + !fifo8_is_full(&s->rx_sram)) { + /* Read reqested number of bytes, max bytes limited to size of sra= m */ + next_b =3D ind_op_next_byte(op); + end_b =3D next_b + fifo8_num_free(&s->rx_sram); + end_b =3D MIN(end_b, ind_op_end_byte(op)); + + len =3D end_b - next_b; + ospi_ind_read(s, next_b, len); + ind_op_advance(op, len); + + if (ospi_ind_rd_watermark_enabled(s)) { + ARRAY_FIELD_DP32(s->regs, IRQ_STATUS_REG, + INDIRECT_XFER_LEVEL_BREACH_FLD, 1); + set_irq(s, + R_IRQ_STATUS_REG_INDIRECT_XFER_LEVEL_BREACH_FLD_MASK); + } + + if (!s->src_dma_inprog && + ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_DMA_IF_FLD)) { + ospi_dma_read(s, start_dma); + } + } + + /* Set sram full */ + if (fifo8_num_used(&s->rx_sram) =3D=3D RXFF_SZ) { + ARRAY_FIELD_DP32(s->regs, + INDIRECT_READ_XFER_CTRL_REG, SRAM_FULL_FLD, 1); + set_irq(s, R_IRQ_STATUS_REG_INDRD_SRAM_FULL_FLD_MASK); + } + + /* Signal completion if done, unless inside recursion via ospi_dma_rea= d */ + if (!ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_DMA_IF_FLD) || start_dm= a) { + if (ospi_ind_op_completed(op)) { + ospi_ind_rd_completed(s); + } + } +} + +static void ospi_notify(void *opaque) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(opaque); + + s->src_dma_inprog =3D false; + ospi_dma_read(s, false); + if (!ospi_ind_op_completed(s->rd_ind_op)) { + ospi_do_ind_read(s); + } +} + +/* Transmit write enable instruction */ +static void ospi_transmit_wel(XlnxVersalOspi *s, bool ahb_decoder_cs, + hwaddr addr) +{ + fifo8_reset(&s->tx_fifo); + fifo8_push(&s->tx_fifo, WREN); + + if (ahb_decoder_cs) { + ospi_ahb_decoder_enable_cs(s, addr); + } else { + ospi_update_cs_lines(s); + } + + ospi_flush_txfifo(s); + ospi_disable_cs(s); + + fifo8_reset(&s->rx_fifo); +} + +static void ospi_ind_write(XlnxVersalOspi *s, uint32_t flash_addr, uint32_= t len) +{ + bool ahb_decoder_cs =3D false; + uint8_t inst_code; + int i; + + assert(fifo8_num_used(&s->tx_sram) >=3D len); + + if (!ARRAY_FIELD_EX32(s->regs, DEV_INSTR_WR_CONFIG_REG, WEL_DIS_FLD)) { + ospi_transmit_wel(s, ahb_decoder_cs, 0); + } + + /* reset fifos */ + fifo8_reset(&s->tx_fifo); + fifo8_reset(&s->rx_fifo); + + /* Push write opcode */ + inst_code =3D ospi_get_wr_opcode(s); + fifo8_push(&s->tx_fifo, inst_code); + + /* Push write address */ + ospi_tx_fifo_push_address(s, flash_addr); + + /* data */ + for (i =3D 0; i < len; i++) { + fifo8_push(&s->tx_fifo, fifo8_pop(&s->tx_sram)); + } + + /* transmit */ + ospi_update_cs_lines(s); + ospi_flush_txfifo(s); + + /* done */ + ospi_disable_cs(s); + fifo8_reset(&s->rx_fifo); +} + +static void ind_wr_inc_num_done(XlnxVersalOspi *s) +{ + unsigned int done =3D ARRAY_FIELD_EX32(s->regs, INDIRECT_WRITE_XFER_CT= RL_REG, + NUM_IND_OPS_DONE_FLD); + if (done < IND_OPS_DONE_MAX) { + done++; + } + done &=3D 0x3; + ARRAY_FIELD_DP32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, + NUM_IND_OPS_DONE_FLD, done); +} + +static void ospi_ind_wr_completed(XlnxVersalOspi *s) +{ + ARRAY_FIELD_DP32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, + IND_OPS_DONE_STATUS_FLD, 1); + ind_wr_inc_num_done(s); + ospi_ind_op_next(s->wr_ind_op); + /* Set indirect op done interrupt if enabled */ + if (ospi_ind_op_all_completed(s)) { + set_irq(s, R_IRQ_STATUS_REG_INDIRECT_OP_DONE_FLD_MASK); + } +} + +static void ospi_do_indirect_write(XlnxVersalOspi *s) +{ + uint32_t write_watermark =3D s->regs[R_INDIRECT_WRITE_XFER_WATERMARK_R= EG]; + uint32_t pagesz =3D ospi_get_page_sz(s); + uint32_t page_mask =3D ~(pagesz - 1); + IndOp *op =3D s->wr_ind_op; + uint32_t next_b; + uint32_t end_b; + uint32_t len; + + /* Write out tx_fifo in maximum page sz chunks */ + while (!ospi_ind_op_completed(op) && fifo8_num_used(&s->tx_sram) > 0) { + next_b =3D ind_op_next_byte(op); + end_b =3D next_b + MIN(fifo8_num_used(&s->tx_sram), pagesz); + + /* Dont cross page boundery */ + if ((end_b & page_mask) > next_b) { + end_b &=3D page_mask; + } + + len =3D end_b - next_b; + len =3D MIN(len, op->num_bytes - op->done_bytes); + ospi_ind_write(s, next_b, len); + ind_op_advance(op, len); + } + + /* + * Always set indirect transfer level breached interrupt if enabled + * (write watermark > 0) since the tx_sram always will be emptied + */ + if (write_watermark > 0) { + set_irq(s, R_IRQ_STATUS_REG_INDIRECT_XFER_LEVEL_BREACH_FLD_MASK); + } + + /* Signal completions if done */ + if (ospi_ind_op_completed(op)) { + ospi_ind_wr_completed(s); + } +} + +static void ospi_stig_fill_membank(XlnxVersalOspi *s) +{ + int num_rd_bytes =3D ospi_stig_membank_rd_bytes(s); + int idx =3D num_rd_bytes - 8; /* first of last 8 */ + uint32_t lower =3D 0; + uint32_t upper =3D 0; + int i; + + for (i =3D 0; i < num_rd_bytes; i++) { + s->stig_membank[i] =3D fifo8_pop(&s->rx_fifo); + } + + /* Fill in lower upper regs */ + for (i =3D 0; i < 4; i++) { + lower |=3D ((uint32_t)s->stig_membank[idx++]) << 8 * i; + } + + for (i =3D 0; i < 4; i++) { + upper |=3D ((uint32_t)s->stig_membank[idx++]) << 8 * i; + } + + s->regs[R_FLASH_RD_DATA_LOWER_REG] =3D lower; + s->regs[R_FLASH_RD_DATA_UPPER_REG] =3D upper; +} + +static void ospi_stig_cmd_exec(XlnxVersalOspi *s) +{ + uint8_t inst_code; + + /* Reset fifos */ + fifo8_reset(&s->tx_fifo); + fifo8_reset(&s->rx_fifo); + + /* Push write opcode */ + inst_code =3D ARRAY_FIELD_EX32(s->regs, FLASH_CMD_CTRL_REG, CMD_OPCODE= _FLD); + fifo8_push(&s->tx_fifo, inst_code); + + /* Push address if enabled */ + if (ARRAY_FIELD_EX32(s->regs, FLASH_CMD_CTRL_REG, ENB_COMD_ADDR_FLD)) { + ospi_tx_fifo_push_stig_addr(s); + } + + /* Enable cs */ + ospi_update_cs_lines(s); + + /* Data */ + if (ARRAY_FIELD_EX32(s->regs, FLASH_CMD_CTRL_REG, ENB_WRITE_DATA_FLD))= { + ospi_tx_fifo_push_stig_wr_data(s); + } else if (ARRAY_FIELD_EX32(s->regs, + FLASH_CMD_CTRL_REG, ENB_READ_DATA_FLD)) { + /* transmit first part */ + ospi_flush_txfifo(s); + fifo8_reset(&s->rx_fifo); + ospi_tx_fifo_push_stig_rd_data(s); + } + + /* Transmit */ + ospi_flush_txfifo(s); + ospi_disable_cs(s); + + if (ARRAY_FIELD_EX32(s->regs, FLASH_CMD_CTRL_REG, ENB_READ_DATA_FLD)) { + if (ARRAY_FIELD_EX32(s->regs, + FLASH_CMD_CTRL_REG, STIG_MEM_BANK_EN_FLD)) { + ospi_stig_fill_membank(s); + } else { + ospi_rx_fifo_pop_stig_rd_data(s); + } + } +} + +static uint32_t ospi_block_address(XlnxVersalOspi *s, unsigned int block) +{ + unsigned int block_sz =3D ospi_get_block_sz(s); + unsigned int cs =3D 0; + uint32_t addr =3D 0; + + while (cs < s->num_cs && block >=3D flash_blocks(s, cs)) { + block -=3D flash_blocks(s, 0); + addr +=3D flash_sz(s, cs); + } + addr +=3D block * block_sz; + return addr; +} + +static uint32_t ospi_get_wr_prot_addr_low(XlnxVersalOspi *s) +{ + unsigned int block =3D s->regs[R_LOWER_WR_PROT_REG]; + + return ospi_block_address(s, block); +} + +static uint32_t ospi_get_wr_prot_addr_upper(XlnxVersalOspi *s) +{ + unsigned int block =3D s->regs[R_UPPER_WR_PROT_REG]; + + /* Get address of first block out of defined range */ + return ospi_block_address(s, block + 1); +} + +static bool ospi_is_write_protected(XlnxVersalOspi *s, hwaddr addr) +{ + uint32_t wr_prot_addr_upper =3D ospi_get_wr_prot_addr_upper(s); + uint32_t wr_prot_addr_low =3D ospi_get_wr_prot_addr_low(s); + bool in_range =3D false; + + if (addr >=3D wr_prot_addr_low && addr < wr_prot_addr_upper) { + in_range =3D true; + } + + if (ARRAY_FIELD_EX32(s->regs, WR_PROT_CTRL_REG, INV_FLD)) { + in_range =3D !in_range; + } + return in_range; +} + +static uint64_t ospi_rx_sram_read(XlnxVersalOspi *s, unsigned int size) +{ + OSPIRdData ret =3D {}; + int i; + + if (size < 4 && fifo8_num_used(&s->rx_sram) >=3D 4) { + qemu_log_mask(LOG_GUEST_ERROR, + "OSPI only last read of internal " + "sram is allowed to be < 32 bits\n"); + } + + size =3D MIN(fifo8_num_used(&s->rx_sram), size); + for (i =3D 0; i < size; i++) { + ret.u8[i] =3D fifo8_pop(&s->rx_sram); + } + return ret.u64; +} + +static void ospi_tx_sram_write(XlnxVersalOspi *s, uint64_t value, + unsigned int size) +{ + int i; + for (i =3D 0; i < size; i++) { + fifo8_push(&s->tx_sram, value >> 8 * i); + } +} + +static uint64_t ospi_do_dac_read(void *opaque, hwaddr addr, unsigned int s= ize) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(opaque); + OSPIRdData ret =3D {}; + int i; + + /* Create first section of read cmd */ + ospi_tx_fifo_push_rd_op_addr(s, (uint32_t) addr); + + /* Enable cs and transmit first part */ + ospi_dac_cs(s, addr); + ospi_flush_txfifo(s); + + fifo8_reset(&s->rx_fifo); + + /* transmit second part (data) */ + for (i =3D 0; i < size; ++i) { + fifo8_push(&s->tx_fifo, 0); + } + ospi_flush_txfifo(s); + + /* fill in result */ + size =3D MIN(fifo8_num_used(&s->rx_fifo), size); + + for (i =3D 0; i < size; i++) { + ret.u8[i] =3D fifo8_pop(&s->rx_fifo); + } + + /* done */ + ospi_disable_cs(s); + + return ret.u64; +} + +static void ospi_do_dac_write(void *opaque, + hwaddr addr, + uint64_t value, + unsigned int size) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(opaque); + bool ahb_decoder_cs =3D ARRAY_FIELD_EX32(s->regs, CONFIG_REG, + ENABLE_AHB_DECODER_FLD); + uint8_t inst_code; + unsigned int i; + + if (!ARRAY_FIELD_EX32(s->regs, DEV_INSTR_WR_CONFIG_REG, WEL_DIS_FLD)) { + ospi_transmit_wel(s, ahb_decoder_cs, addr); + } + + /* reset fifos */ + fifo8_reset(&s->tx_fifo); + fifo8_reset(&s->rx_fifo); + + /* Push write opcode */ + inst_code =3D ospi_get_wr_opcode(s); + fifo8_push(&s->tx_fifo, inst_code); + + /* Push write address */ + ospi_tx_fifo_push_address(s, addr); + + /* data */ + for (i =3D 0; i < size; i++) { + fifo8_push(&s->tx_fifo, value >> 8 * i); + } + + /* Enable cs and transmit */ + ospi_dac_cs(s, addr); + ospi_flush_txfifo(s); + ospi_disable_cs(s); + + fifo8_reset(&s->rx_fifo); +} + +static void flash_cmd_ctrl_mem_reg_post_write(RegisterInfo *reg, + uint64_t val) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(reg->opaque); + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_SPI_FLD)) { + if (ARRAY_FIELD_EX32(s->regs, + FLASH_COMMAND_CTRL_MEM_REG, + TRIGGER_MEM_BANK_REQ_FLD)) { + ospi_stig_membank_req(s); + ARRAY_FIELD_DP32(s->regs, FLASH_COMMAND_CTRL_MEM_REG, + TRIGGER_MEM_BANK_REQ_FLD, 0); + } + } +} + +static void flash_cmd_ctrl_reg_post_write(RegisterInfo *reg, uint64_t val) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_SPI_FLD) && + ARRAY_FIELD_EX32(s->regs, FLASH_CMD_CTRL_REG, CMD_EXEC_FLD)) { + ospi_stig_cmd_exec(s); + set_irq(s, R_IRQ_STATUS_REG_STIG_REQ_INT_FLD_MASK); + ARRAY_FIELD_DP32(s->regs, FLASH_CMD_CTRL_REG, CMD_EXEC_FLD, 0); + } +} + +static uint64_t ind_wr_dec_num_done(XlnxVersalOspi *s, uint64_t val) +{ + unsigned int done =3D ARRAY_FIELD_EX32(s->regs, INDIRECT_WRITE_XFER_CT= RL_REG, + NUM_IND_OPS_DONE_FLD); + done--; + done &=3D 0x3; + val =3D FIELD_DP32(val, INDIRECT_WRITE_XFER_CTRL_REG, + NUM_IND_OPS_DONE_FLD, done); + return val; +} + +static bool ind_wr_clearing_op_done(XlnxVersalOspi *s, uint64_t new_val) +{ + bool set_in_reg =3D ARRAY_FIELD_EX32(s->regs, INDIRECT_WRITE_XFER_CTRL= _REG, + IND_OPS_DONE_STATUS_FLD); + bool set_in_new_val =3D FIELD_EX32(new_val, INDIRECT_WRITE_XFER_CTRL_R= EG, + IND_OPS_DONE_STATUS_FLD); + /* return true if clearing bit */ + return set_in_reg && !set_in_new_val; +} + +static uint64_t ind_wr_xfer_ctrl_reg_pre_write(RegisterInfo *reg, + uint64_t val) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(reg->opaque); + + if (ind_wr_clearing_op_done(s, val)) { + val =3D ind_wr_dec_num_done(s, val); + } + return val; +} + +static void ind_wr_xfer_ctrl_reg_post_write(RegisterInfo *reg, uint64_t va= l) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(reg->opaque); + + if (s->ind_write_disabled) { + return; + } + + if (ARRAY_FIELD_EX32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, START_FLD)= ) { + ospi_ind_op_queue_up_wr(s); + ospi_do_indirect_write(s); + ARRAY_FIELD_DP32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, START_FLD,= 0); + } + + if (ARRAY_FIELD_EX32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, CANCEL_FLD= )) { + ospi_ind_op_cancel(s->wr_ind_op); + fifo8_reset(&s->tx_sram); + ARRAY_FIELD_DP32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, CANCEL_FLD= , 0); + } +} + +static uint64_t ind_wr_xfer_ctrl_reg_post_read(RegisterInfo *reg, + uint64_t val) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(reg->opaque); + IndOp *op =3D s->wr_ind_op; + + /* Check if ind ops is ongoing */ + if (!ospi_ind_op_completed(&op[0])) { + /* Check if two ind ops are queued */ + if (!ospi_ind_op_completed(&op[1])) { + val =3D FIELD_DP32(val, INDIRECT_WRITE_XFER_CTRL_REG, + WR_QUEUED_FLD, 1); + } + val =3D FIELD_DP32(val, INDIRECT_WRITE_XFER_CTRL_REG, WR_STATUS_FL= D, 1); + } + return val; +} + +static uint64_t ind_rd_dec_num_done(XlnxVersalOspi *s, uint64_t val) +{ + unsigned int done =3D ARRAY_FIELD_EX32(s->regs, INDIRECT_READ_XFER_CTR= L_REG, + NUM_IND_OPS_DONE_FLD); + done--; + done &=3D 0x3; + val =3D FIELD_DP32(val, INDIRECT_READ_XFER_CTRL_REG, + NUM_IND_OPS_DONE_FLD, done); + return val; +} + +static uint64_t ind_rd_xfer_ctrl_reg_pre_write(RegisterInfo *reg, + uint64_t val) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(reg->opaque); + + if (FIELD_EX32(val, INDIRECT_READ_XFER_CTRL_REG, + IND_OPS_DONE_STATUS_FLD)) { + val =3D ind_rd_dec_num_done(s, val); + val &=3D ~R_INDIRECT_READ_XFER_CTRL_REG_IND_OPS_DONE_STATUS_FLD_MA= SK; + } + return val; +} + +static void ind_rd_xfer_ctrl_reg_post_write(RegisterInfo *reg, uint64_t va= l) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, INDIRECT_READ_XFER_CTRL_REG, START_FLD))= { + ospi_ind_op_queue_up_rd(s); + ospi_do_ind_read(s); + ARRAY_FIELD_DP32(s->regs, INDIRECT_READ_XFER_CTRL_REG, START_FLD, = 0); + } + + if (ARRAY_FIELD_EX32(s->regs, INDIRECT_READ_XFER_CTRL_REG, CANCEL_FLD)= ) { + ospi_ind_op_cancel(s->rd_ind_op); + fifo8_reset(&s->rx_sram); + ARRAY_FIELD_DP32(s->regs, INDIRECT_READ_XFER_CTRL_REG, CANCEL_FLD,= 0); + } +} + +static uint64_t ind_rd_xfer_ctrl_reg_post_read(RegisterInfo *reg, + uint64_t val) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(reg->opaque); + IndOp *op =3D s->rd_ind_op; + + /* Check if ind ops is ongoing */ + if (!ospi_ind_op_completed(&op[0])) { + /* Check if two ind ops are queued */ + if (!ospi_ind_op_completed(&op[1])) { + val =3D FIELD_DP32(val, INDIRECT_READ_XFER_CTRL_REG, + RD_QUEUED_FLD, 1); + } + val =3D FIELD_DP32(val, INDIRECT_READ_XFER_CTRL_REG, RD_STATUS_FLD= , 1); + } + return val; +} + +static uint64_t sram_fill_reg_post_read(RegisterInfo *reg, uint64_t val) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(reg->opaque); + val =3D ((fifo8_num_used(&s->tx_sram) & 0xFFFF) << 16) | + (fifo8_num_used(&s->rx_sram) & 0xFFFF); + return val; +} + +static uint64_t dll_obs_upper_reg_post_read(RegisterInfo *reg, uint64_t va= l) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(reg->opaque); + uint32_t rx_dec_out; + + rx_dec_out =3D FIELD_EX32(val, DLL_OBSERVABLE_UPPER_REG, + DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD); + + if (rx_dec_out < MAX_RX_DEC_OUT) { + ARRAY_FIELD_DP32(s->regs, DLL_OBSERVABLE_UPPER_REG, + DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD, + rx_dec_out + 1); + } + + return val; +} + + +static void xlnx_versal_ospi_reset(DeviceState *dev) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(dev); + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(s->regs_info); ++i) { + register_reset(&s->regs_info[i]); + } + + fifo8_reset(&s->rx_fifo); + fifo8_reset(&s->tx_fifo); + fifo8_reset(&s->rx_sram); + fifo8_reset(&s->tx_sram); + + s->rd_ind_op[0].completed =3D true; + s->rd_ind_op[1].completed =3D true; + s->wr_ind_op[0].completed =3D true; + s->wr_ind_op[1].completed =3D true; + ARRAY_FIELD_DP32(s->regs, DLL_OBSERVABLE_LOWER_REG, + DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD, 1); + ARRAY_FIELD_DP32(s->regs, DLL_OBSERVABLE_LOWER_REG, + DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD, 1); +} + +static RegisterAccessInfo ospi_regs_info[] =3D { + { .name =3D "CONFIG_REG", + .addr =3D A_CONFIG_REG, + .reset =3D 0x80780081, + .ro =3D 0x9c000000, + },{ .name =3D "DEV_INSTR_RD_CONFIG_REG", + .addr =3D A_DEV_INSTR_RD_CONFIG_REG, + .reset =3D 0x3, + .ro =3D 0xe0ecc800, + },{ .name =3D "DEV_INSTR_WR_CONFIG_REG", + .addr =3D A_DEV_INSTR_WR_CONFIG_REG, + .reset =3D 0x2, + .ro =3D 0xe0fcce00, + },{ .name =3D "DEV_DELAY_REG", + .addr =3D A_DEV_DELAY_REG, + },{ .name =3D "RD_DATA_CAPTURE_REG", + .addr =3D A_RD_DATA_CAPTURE_REG, + .reset =3D 0x1, + .ro =3D 0xfff0fec0, + },{ .name =3D "DEV_SIZE_CONFIG_REG", + .addr =3D A_DEV_SIZE_CONFIG_REG, + .reset =3D 0x101002, + .ro =3D 0xe0000000, + },{ .name =3D "SRAM_PARTITION_CFG_REG", + .addr =3D A_SRAM_PARTITION_CFG_REG, + .reset =3D 0x80, + .ro =3D 0xffffff00, + },{ .name =3D "IND_AHB_ADDR_TRIGGER_REG", + .addr =3D A_IND_AHB_ADDR_TRIGGER_REG, + },{ .name =3D "DMA_PERIPH_CONFIG_REG", + .addr =3D A_DMA_PERIPH_CONFIG_REG, + .ro =3D 0xfffff0f0, + },{ .name =3D "REMAP_ADDR_REG", + .addr =3D A_REMAP_ADDR_REG, + },{ .name =3D "MODE_BIT_CONFIG_REG", + .addr =3D A_MODE_BIT_CONFIG_REG, + .reset =3D 0x200, + .ro =3D 0xffff7800, + },{ .name =3D "SRAM_FILL_REG", + .addr =3D A_SRAM_FILL_REG, + .ro =3D 0xffffffff, + .post_read =3D sram_fill_reg_post_read, + },{ .name =3D "TX_THRESH_REG", + .addr =3D A_TX_THRESH_REG, + .reset =3D 0x1, + .ro =3D 0xffffffe0, + },{ .name =3D "RX_THRESH_REG", + .addr =3D A_RX_THRESH_REG, + .reset =3D 0x1, + .ro =3D 0xffffffe0, + },{ .name =3D "WRITE_COMPLETION_CTRL_REG", + .addr =3D A_WRITE_COMPLETION_CTRL_REG, + .reset =3D 0x10005, + .ro =3D 0x1800, + },{ .name =3D "NO_OF_POLLS_BEF_EXP_REG", + .addr =3D A_NO_OF_POLLS_BEF_EXP_REG, + .reset =3D 0xffffffff, + },{ .name =3D "IRQ_STATUS_REG", + .addr =3D A_IRQ_STATUS_REG, + .ro =3D 0xfff08000, + .w1c =3D 0xf7fff, + },{ .name =3D "IRQ_MASK_REG", + .addr =3D A_IRQ_MASK_REG, + .ro =3D 0xfff08000, + },{ .name =3D "LOWER_WR_PROT_REG", + .addr =3D A_LOWER_WR_PROT_REG, + },{ .name =3D "UPPER_WR_PROT_REG", + .addr =3D A_UPPER_WR_PROT_REG, + },{ .name =3D "WR_PROT_CTRL_REG", + .addr =3D A_WR_PROT_CTRL_REG, + .ro =3D 0xfffffffc, + },{ .name =3D "INDIRECT_READ_XFER_CTRL_REG", + .addr =3D A_INDIRECT_READ_XFER_CTRL_REG, + .ro =3D 0xffffffd4, + .w1c =3D 0x08, + .pre_write =3D ind_rd_xfer_ctrl_reg_pre_write, + .post_write =3D ind_rd_xfer_ctrl_reg_post_write, + .post_read =3D ind_rd_xfer_ctrl_reg_post_read, + },{ .name =3D "INDIRECT_READ_XFER_WATERMARK_REG", + .addr =3D A_INDIRECT_READ_XFER_WATERMARK_REG, + },{ .name =3D "INDIRECT_READ_XFER_START_REG", + .addr =3D A_INDIRECT_READ_XFER_START_REG, + },{ .name =3D "INDIRECT_READ_XFER_NUM_BYTES_REG", + .addr =3D A_INDIRECT_READ_XFER_NUM_BYTES_REG, + },{ .name =3D "INDIRECT_WRITE_XFER_CTRL_REG", + .addr =3D A_INDIRECT_WRITE_XFER_CTRL_REG, + .ro =3D 0xffffffdc, + .w1c =3D 0x20, + .pre_write =3D ind_wr_xfer_ctrl_reg_pre_write, + .post_write =3D ind_wr_xfer_ctrl_reg_post_write, + .post_read =3D ind_wr_xfer_ctrl_reg_post_read, + },{ .name =3D "INDIRECT_WRITE_XFER_WATERMARK_REG", + .addr =3D A_INDIRECT_WRITE_XFER_WATERMARK_REG, + .reset =3D 0xffffffff, + },{ .name =3D "INDIRECT_WRITE_XFER_START_REG", + .addr =3D A_INDIRECT_WRITE_XFER_START_REG, + },{ .name =3D "INDIRECT_WRITE_XFER_NUM_BYTES_REG", + .addr =3D A_INDIRECT_WRITE_XFER_NUM_BYTES_REG, + },{ .name =3D "INDIRECT_TRIGGER_ADDR_RANGE_REG", + .addr =3D A_INDIRECT_TRIGGER_ADDR_RANGE_REG, + .reset =3D 0x4, + .ro =3D 0xfffffff0, + },{ .name =3D "FLASH_COMMAND_CTRL_MEM_REG", + .addr =3D A_FLASH_COMMAND_CTRL_MEM_REG, + .ro =3D 0xe008fffe, + .post_write =3D flash_cmd_ctrl_mem_reg_post_write, + },{ .name =3D "FLASH_CMD_CTRL_REG", + .addr =3D A_FLASH_CMD_CTRL_REG, + .ro =3D 0x7a, + .post_write =3D flash_cmd_ctrl_reg_post_write, + },{ .name =3D "FLASH_CMD_ADDR_REG", + .addr =3D A_FLASH_CMD_ADDR_REG, + },{ .name =3D "FLASH_RD_DATA_LOWER_REG", + .addr =3D A_FLASH_RD_DATA_LOWER_REG, + .ro =3D 0xffffffff, + },{ .name =3D "FLASH_RD_DATA_UPPER_REG", + .addr =3D A_FLASH_RD_DATA_UPPER_REG, + .ro =3D 0xffffffff, + },{ .name =3D "FLASH_WR_DATA_LOWER_REG", + .addr =3D A_FLASH_WR_DATA_LOWER_REG, + },{ .name =3D "FLASH_WR_DATA_UPPER_REG", + .addr =3D A_FLASH_WR_DATA_UPPER_REG, + },{ .name =3D "POLLING_FLASH_STATUS_REG", + .addr =3D A_POLLING_FLASH_STATUS_REG, + .ro =3D 0xfff0ffff, + },{ .name =3D "PHY_CONFIGURATION_REG", + .addr =3D A_PHY_CONFIGURATION_REG, + .reset =3D 0x40000000, + .ro =3D 0x1f80ff80, + },{ .name =3D "PHY_MASTER_CONTROL_REG", + .addr =3D A_PHY_MASTER_CONTROL_REG, + .reset =3D 0x800000, + .ro =3D 0xfe08ff80, + },{ .name =3D "DLL_OBSERVABLE_LOWER_REG", + .addr =3D A_DLL_OBSERVABLE_LOWER_REG, + .ro =3D 0xffffffff, + },{ .name =3D "DLL_OBSERVABLE_UPPER_REG", + .addr =3D A_DLL_OBSERVABLE_UPPER_REG, + .ro =3D 0xffffffff, + .post_read =3D dll_obs_upper_reg_post_read, + },{ .name =3D "OPCODE_EXT_LOWER_REG", + .addr =3D A_OPCODE_EXT_LOWER_REG, + .reset =3D 0x13edfa00, + },{ .name =3D "OPCODE_EXT_UPPER_REG", + .addr =3D A_OPCODE_EXT_UPPER_REG, + .reset =3D 0x6f90000, + .ro =3D 0xffff, + },{ .name =3D "MODULE_ID_REG", + .addr =3D A_MODULE_ID_REG, + .reset =3D 0x300, + .ro =3D 0xffffffff, + } +}; + +/* Return dev-obj from reg-region created by register_init_block32 */ +static XlnxVersalOspi *xilinx_ospi_of_mr(void *mr_accessor) +{ + RegisterInfoArray *reg_array =3D mr_accessor; + Object *dev; + + assert(reg_array !=3D NULL); + + dev =3D reg_array->mem.owner; + assert(dev); + + return XILINX_VERSAL_OSPI(dev); +} + +static void ospi_write(void *opaque, hwaddr addr, uint64_t value, + unsigned int size) +{ + XlnxVersalOspi *s =3D xilinx_ospi_of_mr(opaque); + + register_write_memory(opaque, addr, value, size); + ospi_update_irq_line(s); +} + +static const MemoryRegionOps ospi_ops =3D { + .read =3D register_read_memory, + .write =3D ospi_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static uint64_t ospi_indac_read(void *opaque, unsigned int size) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(opaque); + uint64_t ret =3D ospi_rx_sram_read(s, size); + + if (!ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_DMA_IF_FLD) && + !ospi_ind_op_completed(s->rd_ind_op)) { + ospi_do_ind_read(s); + } + return ret; +} + +static void ospi_indac_write(void *opaque, uint64_t value, unsigned int si= ze) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(opaque); + + if (s->ind_write_disabled) { + g_assert_not_reached(); + } + + if (!ospi_ind_op_completed(s->wr_ind_op)) { + ospi_tx_sram_write(s, value, size); + ospi_do_indirect_write(s); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "OSPI wr into indac area while no ongoing indac wr\n"); + } +} + +static bool is_inside_indac_range(XlnxVersalOspi *s, hwaddr addr) +{ + uint32_t range_start =3D s->regs[R_IND_AHB_ADDR_TRIGGER_REG]; + uint32_t range_end =3D range_start + + (1 << ARRAY_FIELD_EX32(s->regs, + INDIRECT_TRIGGER_ADDR_RANG= E_REG, + IND_RANGE_WIDTH_FLD)); + + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_DMA_IF_FLD)) { + addr +=3D s->regs[R_IND_AHB_ADDR_TRIGGER_REG]; + } else { + addr +=3D s->regs[R_IND_AHB_ADDR_TRIGGER_REG] & 0xF0000000; + } + + return addr >=3D range_start && addr < range_end; +} + +static bool ospi_is_indac_active(XlnxVersalOspi *s) +{ + /* + * When dac and indac cannot be active at the same time, + * return true when dac is disabled. + */ + return s->dac_with_indac || !s->dac_enable; +} + +static uint64_t ospi_dac_read(void *opaque, hwaddr addr, unsigned int size) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(opaque); + + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_SPI_FLD)) { + if (ospi_is_indac_active(s) && + is_inside_indac_range(s, addr)) { + return ospi_indac_read(s, size); + } + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_DIR_ACC_CTLR_FLD) + && s->dac_enable) { + if (ARRAY_FIELD_EX32(s->regs, + CONFIG_REG, ENB_AHB_ADDR_REMAP_FLD)) { + addr +=3D s->regs[R_REMAP_ADDR_REG]; + } + return ospi_do_dac_read(opaque, addr, size); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "OSPI AHB rd while DAC disabled= \n"); + } + } else { + qemu_log_mask(LOG_GUEST_ERROR, "OSPI AHB rd while OSPI disabled\n"= ); + } + + return 0; +} + +static void ospi_dac_write(void *opaque, hwaddr addr, uint64_t value, + unsigned int size) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(opaque); + + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_SPI_FLD)) { + if (ospi_is_indac_active(s) && + !s->ind_write_disabled && + is_inside_indac_range(s, addr)) { + return ospi_indac_write(s, value, size); + } + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_DIR_ACC_CTLR_FLD) && + s->dac_enable) { + if (ARRAY_FIELD_EX32(s->regs, + CONFIG_REG, ENB_AHB_ADDR_REMAP_FLD)) { + addr +=3D s->regs[R_REMAP_ADDR_REG]; + } + /* Check if addr is write protected */ + if (ARRAY_FIELD_EX32(s->regs, WR_PROT_CTRL_REG, ENB_FLD) && + ospi_is_write_protected(s, addr)) { + set_irq(s, R_IRQ_STATUS_REG_PROT_WR_ATTEMPT_FLD_MASK); + ospi_update_irq_line(s); + qemu_log_mask(LOG_GUEST_ERROR, + "OSPI writing into write protected area\n"); + return; + } + ospi_do_dac_write(opaque, addr, value, size); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "OSPI AHB wr while DAC disabled= \n"); + } + } else { + qemu_log_mask(LOG_GUEST_ERROR, "OSPI AHB wr while OSPI disabled\n"= ); + } +} + +static const MemoryRegionOps ospi_dac_ops =3D { + .read =3D ospi_dac_read, + .write =3D ospi_dac_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static void ospi_update_dac_status(void *opaque, int n, int level) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(opaque); + + s->dac_enable =3D level; +} + +static void xlnx_versal_ospi_realize(DeviceState *dev, Error **errp) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + s->num_cs =3D 4; + s->spi =3D ssi_create_bus(dev, "spi0"); + s->cs_lines =3D g_new0(qemu_irq, s->num_cs); + for (int i =3D 0; i < s->num_cs; ++i) { + sysbus_init_irq(sbd, &s->cs_lines[i]); + } + + fifo8_create(&s->rx_fifo, RXFF_SZ); + fifo8_create(&s->tx_fifo, TXFF_SZ); + fifo8_create(&s->rx_sram, RXFF_SZ); + fifo8_create(&s->tx_sram, TXFF_SZ); +} + +static void xlnx_versal_ospi_init(Object *obj) +{ + XlnxVersalOspi *s =3D XILINX_VERSAL_OSPI(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + DeviceState *dev =3D DEVICE(obj); + RegisterInfoArray *reg_array; + + memory_region_init(&s->iomem, obj, TYPE_XILINX_VERSAL_OSPI, + XILINX_VERSAL_OSPI_R_MAX * 4); + reg_array =3D + register_init_block32(DEVICE(obj), ospi_regs_info, + ARRAY_SIZE(ospi_regs_info), + s->regs_info, s->regs, + &ospi_ops, + XILINX_VERSAL_OSPI_ERR_DEBUG, + XILINX_VERSAL_OSPI_R_MAX * 4); + memory_region_add_subregion(&s->iomem, 0x0, ®_array->mem); + sysbus_init_mmio(sbd, &s->iomem); + + memory_region_init_io(&s->iomem_dac, obj, &ospi_dac_ops, s, + TYPE_XILINX_VERSAL_OSPI "-dac", 0x20000000); + sysbus_init_mmio(sbd, &s->iomem_dac); + + sysbus_init_irq(sbd, &s->irq); + + object_property_add_link(obj, "dma-src", TYPE_DMA_CTRL, + (Object **)&s->dma_src, + object_property_allow_set_link, + OBJ_PROP_LINK_STRONG); + + qdev_init_gpio_in(dev, ospi_update_dac_status, 1); +} + +static const VMStateDescription vmstate_ind_op =3D { + .name =3D "OSPIIndOp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(flash_addr, IndOp), + VMSTATE_UINT32(num_bytes, IndOp), + VMSTATE_UINT32(done_bytes, IndOp), + VMSTATE_BOOL(completed, IndOp), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_xlnx_versal_ospi =3D { + .name =3D TYPE_XILINX_VERSAL_OSPI, + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_FIFO8(rx_fifo, XlnxVersalOspi), + VMSTATE_FIFO8(tx_fifo, XlnxVersalOspi), + VMSTATE_FIFO8(rx_sram, XlnxVersalOspi), + VMSTATE_FIFO8(tx_sram, XlnxVersalOspi), + VMSTATE_BOOL(ind_write_disabled, XlnxVersalOspi), + VMSTATE_BOOL(dac_with_indac, XlnxVersalOspi), + VMSTATE_BOOL(dac_enable, XlnxVersalOspi), + VMSTATE_BOOL(src_dma_inprog, XlnxVersalOspi), + VMSTATE_STRUCT_ARRAY(rd_ind_op, XlnxVersalOspi, 2, 1, + vmstate_ind_op, IndOp), + VMSTATE_STRUCT_ARRAY(wr_ind_op, XlnxVersalOspi, 2, 1, + vmstate_ind_op, IndOp), + VMSTATE_UINT32_ARRAY(regs, XlnxVersalOspi, XILINX_VERSAL_OSPI_R_MA= X), + VMSTATE_UINT8_ARRAY(stig_membank, XlnxVersalOspi, 512), + VMSTATE_END_OF_LIST(), + } +}; + +static Property xlnx_versal_ospi_properties[] =3D { + DEFINE_PROP_BOOL("dac-with-indac", XlnxVersalOspi, dac_with_indac, fal= se), + DEFINE_PROP_BOOL("indac-write-disabled", XlnxVersalOspi, + ind_write_disabled, true), + DEFINE_PROP_UINT8("num-cs", XlnxVersalOspi, num_cs, 4), + DEFINE_PROP_END_OF_LIST(), +}; + +static void xlnx_versal_ospi_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D xlnx_versal_ospi_reset; + dc->realize =3D xlnx_versal_ospi_realize; + dc->vmsd =3D &vmstate_xlnx_versal_ospi; + device_class_set_props(dc, xlnx_versal_ospi_properties); +} + +static const TypeInfo xlnx_versal_ospi_info =3D { + .name =3D TYPE_XILINX_VERSAL_OSPI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(XlnxVersalOspi), + .class_init =3D xlnx_versal_ospi_class_init, + .instance_init =3D xlnx_versal_ospi_init, +}; + +static void xlnx_versal_ospi_register_types(void) +{ + type_register_static(&xlnx_versal_ospi_info); +} + +type_init(xlnx_versal_ospi_register_types) diff --git a/include/hw/ssi/xlnx-versal-ospi.h b/include/hw/ssi/xlnx-versal= -ospi.h new file mode 100644 index 0000000000..cc2602b300 --- /dev/null +++ b/include/hw/ssi/xlnx-versal-ospi.h @@ -0,0 +1,86 @@ +/* + * Header file for the Xilinx Versal's OSPI controller + * + * Copyright (C) 2021 Xilinx Inc + * Written by Francisco Iglesias + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef XILINX_VERSAL_OSPI_H +#define XILINX_VERSAL_OSPI_H + +#include "hw/register.h" +#include "hw/ssi/ssi.h" +#include "qemu/fifo32.h" +#include "hw/dma/dma-ctrl.h" + +#define TYPE_XILINX_VERSAL_OSPI "xlnx.versal-ospi" + +#define XILINX_VERSAL_OSPI(obj) \ + OBJECT_CHECK(XlnxVersalOspi, (obj), TYPE_XILINX_VERSAL_OSPI) + +#define XILINX_VERSAL_OSPI_R_MAX (0xfc / 4 + 1) + +/* + * Indirect operations + */ +typedef struct IndOp { + uint32_t flash_addr; + uint32_t num_bytes; + uint32_t done_bytes; + bool completed; +} IndOp; + +typedef struct XlnxVersalOspi { + SysBusDevice parent_obj; + + MemoryRegion iomem; + MemoryRegion iomem_dac; + + uint8_t num_cs; + qemu_irq *cs_lines; + + SSIBus *spi; + + Fifo8 rx_fifo; + Fifo8 tx_fifo; + + Fifo8 rx_sram; + Fifo8 tx_sram; + + qemu_irq irq; + + DmaCtrl *dma_src; + bool ind_write_disabled; + bool dac_with_indac; + bool dac_enable; + bool src_dma_inprog; + + IndOp rd_ind_op[2]; + IndOp wr_ind_op[2]; + + uint32_t regs[XILINX_VERSAL_OSPI_R_MAX]; + RegisterInfo regs_info[XILINX_VERSAL_OSPI_R_MAX]; + + /* Maximum inferred membank size is 512 bytes */ + uint8_t stig_membank[512]; +} XlnxVersalOspi; + +#endif /* XILINX_VERSAL_OSPI_H */ --=20 2.11.0 From nobody Fri Apr 19 16:53:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail(p=none dis=none) header.from=xilinx.com ARC-Seal: i=2; a=rsa-sha256; t=1637664141; cv=pass; d=zohomail.com; s=zohoarc; b=EQjw998Nx/1q/Lb9lVDSC9JOnh17V8onKaKwRaByB0GFlBQrFOXLR1pUnXml80fwAe3+Ue6V8JeqCN705EWDwejh1vjP7JNYw2cL+XcnFS+WWCspa4hGFD1H+i9lOCdV5jrdqta2+qo4lX8zTxOW5ccZuSY3rslMBZF0V41EJtQ= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637664141; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OhTxWBgQixX5keqT0NuXkC1t8WtYiZpDKHUdougOGT8=; b=QeeNmhVyJcy/S/F7cPdPsEBReN3ZhFy8V9TBMbwm2mS7l7dQOktsXkGZsnYbWttnxbYKGlrAkrOzOigghg7ky2GuAh9QVck94V2QU4KnAplp/Rm2jAKVcb1rWWZEY6s5j4jkhmX9+1lY8BEVEQmaMRGrj6u8dYBP0x2LUw1fUHY= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637664141096749.5348708567255; Tue, 23 Nov 2021 02:42:21 -0800 (PST) Received: from localhost ([::1]:51476 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mpTFh-0002Hk-QS for importer@patchew.org; Tue, 23 Nov 2021 05:42:18 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60558) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpT8s-0005O6-Vh for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:35:14 -0500 Received: from mail-mw2nam10on2088.outbound.protection.outlook.com ([40.107.94.88]:35425 helo=NAM10-MW2-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpT8o-0000jh-GY for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:35:12 -0500 Received: from BN9PR03CA0443.namprd03.prod.outlook.com (2603:10b6:408:113::28) by MW4PR02MB7363.namprd02.prod.outlook.com (2603:10b6:303:67::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.19; Tue, 23 Nov 2021 10:35:07 +0000 Received: from BN1NAM02FT011.eop-nam02.prod.protection.outlook.com (2603:10b6:408:113:cafe::7b) by BN9PR03CA0443.outlook.office365.com (2603:10b6:408:113::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.20 via Frontend Transport; Tue, 23 Nov 2021 10:35:07 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (149.199.62.198) by BN1NAM02FT011.mail.protection.outlook.com (10.13.2.129) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4713.19 via Frontend Transport; Tue, 23 Nov 2021 10:35:07 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 23 Nov 2021 02:34:42 -0800 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 23 Nov 2021 02:34:42 -0800 Received: from [10.23.120.28] (port=57995 helo=debian.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mpT8M-000GX6-B8; Tue, 23 Nov 2021 02:34:42 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=I0Aonic/0NxN1YAO6WnUoW8oOu3qobp86Q8WwDNS7uYT7S5RSWBkVceWOxqOq7FtBz4eBSVP1jRI9pnjGF2ndK6eKqmfbyB0UGPuc2ZK1YMdW/bkZIh+3lTuW8G9LOcm+QEjDY4S9qiCRWgrs5QYk8BoGmE9yURoiF7hvgT9hlMyhpn3NbLlgDid4J5IGf3qlrkWf/BpLxIIhLwH3TslYO5t+F+igoEwWDPmt9rwzuJVeiOpgizglzKprVZ75GLQHSZWuKnKH9Agkixv1/LF89ajQa05Trijw+4WIwECJAlf9jueOZch/cM63Npy4rz8bh6XGx2KzRbdT3RgIDxxnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=OhTxWBgQixX5keqT0NuXkC1t8WtYiZpDKHUdougOGT8=; b=NWB0dWxOtvCXbE4/JfvPFZvWB2kWUev/IdOZjn64qDv+LW954P7YQ3qYrEPC4+hCcXNYUT2HxllRQ1KnyRKe0lXSV6ihTWvCpXvFYTeAwirC/6wk2OeVaR993u3nIeYERy1DF0CTkb+0Tsy02cAQfpfyXouobiv4aRGUR3g+73g8k/+OIWIjrF9YXQZvf9U1ExrT2qIjH9xw6T8AePwMSVxSjwJ10ARxlKwgwy9E3tveYrveXCxjnoQ+zDQ7jxkr+RiQcbuG3qJgghMxrSgIpetVauEtZ01V+A3HrqPkUSlyFcDLZOQaK8gIGpYuteKPWXL/iFYAn+NiU1LNq9xX3g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=nongnu.org smtp.mailfrom=xilinx.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OhTxWBgQixX5keqT0NuXkC1t8WtYiZpDKHUdougOGT8=; b=T3wXaBVXfqqVUAncTcwB5So8hMQ1nigG8A2cP7xsh6VJhMKKujO53VUuD0WVH+ob7JEB0TyP9YlxuH6dTgfFz834frEWP9PYVIkKDBPYqEbMmf30aTORsre8fuFmD8gtkJkFIyGccehuutmqQC/4zWgXHQ1VxD5VjInt5POrM9M= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch02.xlnx.xilinx.com; From: Francisco Iglesias To: Subject: [PATCH v2 07/10] hw/arm/xlnx-versal: Connect the OSPI flash memory controller model Date: Tue, 23 Nov 2021 10:34:25 +0000 Message-ID: <20211123103428.8765-8-francisco.iglesias@xilinx.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20211123103428.8765-1-francisco.iglesias@xilinx.com> References: <20211123103428.8765-1-francisco.iglesias@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e8798794-9ff9-4b6d-ab3d-08d9ae6ceb56 X-MS-TrafficTypeDiagnostic: MW4PR02MB7363: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:403; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CxE4Aa9UQFUSggACHnv7pKBQ75jySLyHVNuV+6VpgsroFkIjmPNRWMOKYQkH2nIcBWfbMKLSUvS7TJAhIvGgSuocJfZcohYnLOOma9vww9CnVRWZsHysmubDOXBodAGPKa3RWtEkXqS24sstryVpknn6cA00XeUHre6rag3oPfwndGb6N4RHIlFzFbC8l3uzdD/QONLYdmvX4mjghf6nJLLS34rqzT0Sco/aAwDrjV6evLSc/46w6aIG9utYv1vb2ZoFHKsnmv9IXzI/OrT+b3qBL9r2MfZZIRJaE7RgnNMc39/mggjqfNAmN7xqo02bCgPdJ33Xxlequ2TxmfUrAJcWpg3hzXh+ay/0DBAqqBr3nniF6arjTuzw54Y/PdtxzRXa7/UbQGLQlC61NEyAEdg5PT1lRFb2i2bOZyq9c0fV7dauvJC4GnwjRiQ0rGxFGiby45MvjpuAHp2lbsFpchiuPNruACYXvH7pF+5xWtdYmB0gxc2chc3inxhWx9dmviXmRBQ272CE/DGmswCGKGZsAEE87o79obm2La95oWquZ80iAGEQ8t3OoC3J9QSp6RCqJvkuPmdp9kRk+1EGl1l46ljlw55paZ1tmwioiPvQJn33eQsY0362erLQq7r2nP/LuhK9BV9nVU7nHOuenKz0RzC0NjgunKEr2BhkFImESTFCk+LTJqq43Y1vvXZ92UxaNdQNPiD5j14NmPOGdNQkxMzSEA5yfoBAXll5en8= X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(36840700001)(46966006)(36756003)(186003)(2616005)(47076005)(5660300002)(336012)(426003)(9786002)(1076003)(36906005)(2906002)(6666004)(6916009)(8936002)(4326008)(356005)(7696005)(70586007)(508600001)(8676002)(82310400004)(26005)(36860700001)(7636003)(70206006)(316002)(54906003)(44832011)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2021 10:35:07.6253 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e8798794-9ff9-4b6d-ab3d-08d9ae6ceb56 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT011.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR02MB7363 Received-SPF: pass client-ip=40.107.94.88; envelope-from=figlesia@xilinx.com; helo=NAM10-MW2-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, peter.maydell@linaro.org, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1637664143059100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Connect the OSPI flash memory controller model (including the source and destination DMA). Signed-off-by: Francisco Iglesias --- hw/arm/xlnx-versal.c | 87 ++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/arm/xlnx-versal.h | 20 ++++++++++ 2 files changed, 107 insertions(+) diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 08e250945f..20c82bff01 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -24,6 +24,7 @@ =20 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define GEM_REVISION 0x40070106 +#define NUM_OSPI_IRQ_LINES 3 =20 static void versal_create_apu_cpus(Versal *s) { @@ -385,6 +386,91 @@ static void versal_create_pmc_iou_slcr(Versal *s, qemu= _irq *pic) sysbus_connect_irq(sbd, 0, pic[VERSAL_PMC_IOU_SLCR_IRQ]); } =20 +static void versal_create_ospi(Versal *s, qemu_irq *pic) +{ + SysBusDevice *sbd; + MemoryRegion *mr_dac; + + memory_region_init(&s->pmc.iou.ospi.linear_mr, OBJECT(s), + "versal-ospi-linear-mr" , MM_PMC_OSPI_DAC_SIZE); + + object_initialize_child(OBJECT(s), "versal-ospi", &s->pmc.iou.ospi.osp= i, + TYPE_XILINX_VERSAL_OSPI); + + mr_dac =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi= ), 1); + memory_region_add_subregion(&s->pmc.iou.ospi.linear_mr, 0x0, mr_dac); + + /* Create the OSPI destination DMA */ + object_initialize_child(OBJECT(s), "versal-ospi-dma-dst", + &s->pmc.iou.ospi.dma_dst, + TYPE_XLNX_CSU_DMA); + + object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_dst), + "dma", OBJECT(get_system_memory()), + &error_abort); + + sbd =3D SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst); + sysbus_realize(sbd, &error_fatal); + + memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_DST, + sysbus_mmio_get_region(sbd, 0)); + + /* Create the OSPI source DMA */ + object_initialize_child(OBJECT(s), "versal-ospi-dma-src", + &s->pmc.iou.ospi.dma_src, + TYPE_XLNX_CSU_DMA); + + object_property_set_bool(OBJECT(&s->pmc.iou.ospi.dma_src), "is-dst", + false, &error_abort); + + object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src), + "dma", OBJECT(mr_dac), &error_abort); + + object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src), + "stream-connected-dma", + OBJECT(&s->pmc.iou.ospi.dma_dst), + &error_abort); + + sbd =3D SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src); + sysbus_realize(sbd, &error_fatal); + + memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_SRC, + sysbus_mmio_get_region(sbd, 0)); + + /* Realize the OSPI */ + object_property_set_link(OBJECT(&s->pmc.iou.ospi.ospi), "dma-src", + OBJECT(&s->pmc.iou.ospi.dma_src), &error_abor= t); + + sbd =3D SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi); + sysbus_realize(sbd, &error_fatal); + + memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI, + sysbus_mmio_get_region(sbd, 0)); + + memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DAC, + &s->pmc.iou.ospi.linear_mr); + + /* ospi_mux_sel */ + qdev_connect_gpio_out(DEVICE(&s->pmc.iou.slcr), 3, + qdev_get_gpio_in(DEVICE(&s->pmc.iou.ospi.ospi), = 0)); + + /* OSPI irq */ + object_initialize_child(OBJECT(s), "ospi-irq", + &s->pmc.iou.ospi.irq, TYPE_OR_IRQ); + object_property_set_int(OBJECT(&s->pmc.iou.ospi.irq), + "num-lines", NUM_OSPI_IRQ_LINES, &error_fatal); + qdev_realize(DEVICE(&s->pmc.iou.ospi.irq), NULL, &error_fatal); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 0, + qdev_get_gpio_in(DEVICE(&s->pmc.iou.ospi.irq), 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src), 0, + qdev_get_gpio_in(DEVICE(&s->pmc.iou.ospi.irq), 1)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst), 0, + qdev_get_gpio_in(DEVICE(&s->pmc.iou.ospi.irq), 2)); + + qdev_connect_gpio_out(DEVICE(&s->pmc.iou.ospi.irq), 0, + pic[VERSAL_OSPI_IRQ]); +} =20 /* This takes the board allocated linear DDR memory and creates aliases * for each split DDR range/aperture on the Versal address map. @@ -477,6 +563,7 @@ static void versal_realize(DeviceState *dev, Error **er= rp) versal_create_bbram(s, pic); versal_create_efuse(s, pic); versal_create_pmc_iou_slcr(s, pic); + versal_create_ospi(s, pic); versal_map_ddr(s); versal_unimp(s); =20 diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 729c093dfc..d5c9c3900b 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -26,6 +26,8 @@ #include "hw/misc/xlnx-versal-xramc.h" #include "hw/nvram/xlnx-bbram.h" #include "hw/nvram/xlnx-versal-efuse.h" +#include "hw/ssi/xlnx-versal-ospi.h" +#include "hw/dma/xlnx_csu_dma.h" #include "hw/misc/xlnx-versal-pmc-iou-slcr.h" =20 #define TYPE_XLNX_VERSAL "xlnx-versal" @@ -80,6 +82,14 @@ struct Versal { struct { SDHCIState sd[XLNX_VERSAL_NR_SDS]; XlnxVersalPmcIouSlcr slcr; + + struct { + XlnxVersalOspi ospi; + XlnxCSUDMA dma_src; + XlnxCSUDMA dma_dst; + MemoryRegion linear_mr; + qemu_or_irq irq; + } ospi; } iou; =20 XlnxZynqMPRTC rtc; @@ -116,6 +126,7 @@ struct Versal { #define VERSAL_BBRAM_APB_IRQ_0 121 #define VERSAL_RTC_APB_ERR_IRQ 121 #define VERSAL_PMC_IOU_SLCR_IRQ 121 +#define VERSAL_OSPI_IRQ 124 #define VERSAL_SD0_IRQ_0 126 #define VERSAL_EFUSE_IRQ 139 #define VERSAL_RTC_ALARM_IRQ 142 @@ -184,6 +195,15 @@ struct Versal { #define MM_PMC_PMC_IOU_SLCR 0xf1060000 #define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000 =20 +#define MM_PMC_OSPI 0xf1010000 +#define MM_PMC_OSPI_SIZE 0x10000 + +#define MM_PMC_OSPI_DAC 0xc0000000 +#define MM_PMC_OSPI_DAC_SIZE 0x20000000 + +#define MM_PMC_OSPI_DMA_DST 0xf1011800 +#define MM_PMC_OSPI_DMA_SRC 0xf1011000 + #define MM_PMC_SD0 0xf1040000U #define MM_PMC_SD0_SIZE 0x10000 #define MM_PMC_BBRAM_CTRL 0xf11f0000 --=20 2.11.0 From nobody Fri Apr 19 16:53:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail(p=none dis=none) header.from=xilinx.com ARC-Seal: i=2; a=rsa-sha256; t=1637663962; cv=pass; d=zohomail.com; s=zohoarc; b=F30UzPKIcxbSD+4OwS8R4Zwx6v1WKPUB6GZj8asNhmEHOfELUODAJ4rmegJ7oFvrhMnD2bASBWfS2ER6Z2sC+LQZQ2Fzu+QjFPe4CR1b2R6eDSXoB78ci/Kg/WxHZ6oW/lD4nVQS8j/zNW9CosEG1/IHlkV+sdVEn9beC/IXE3k= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637663962; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NXWcAGpGYTM1GyWLMa074F/PLliQUrToa7R+JYIFycM=; b=TKKbneG5XOZOgNvQPPK93RA5PBNxnGOxQE4GfEGe8wyX+TreuLIJamEUFEjwzGvAzPPCRkVJAnvOhnO3V/arVTvGiDEV9yNIB50b0GjtwL0EibY9Ko25bURi+R2HoLqfv+vHZwrtAn1pdTnrhwhLtLxy6JNGOvUmhqmJLJ2W76w= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637663962583532.1696002962045; Tue, 23 Nov 2021 02:39:22 -0800 (PST) Received: from localhost ([::1]:43434 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mpTCq-0005Eh-82 for importer@patchew.org; Tue, 23 Nov 2021 05:39:20 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60592) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpT8t-0005Tw-CF for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:35:15 -0500 Received: from mail-dm6nam08on2084.outbound.protection.outlook.com ([40.107.102.84]:24737 helo=NAM04-DM6-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpT8q-0000ju-0Z for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:35:15 -0500 Received: from BN6PR1201CA0023.namprd12.prod.outlook.com (2603:10b6:405:4c::33) by MW2PR02MB3785.namprd02.prod.outlook.com (2603:10b6:907:6::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.22; Tue, 23 Nov 2021 10:35:08 +0000 Received: from BN1NAM02FT062.eop-nam02.prod.protection.outlook.com (2603:10b6:405:4c:cafe::f3) by BN6PR1201CA0023.outlook.office365.com (2603:10b6:405:4c::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.19 via Frontend Transport; Tue, 23 Nov 2021 10:35:08 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (149.199.62.198) by BN1NAM02FT062.mail.protection.outlook.com (10.13.2.168) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4713.19 via Frontend Transport; Tue, 23 Nov 2021 10:35:08 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 23 Nov 2021 02:34:44 -0800 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 23 Nov 2021 02:34:44 -0800 Received: from [10.23.120.28] (port=57995 helo=debian.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mpT8N-000GX6-Vq; Tue, 23 Nov 2021 02:34:44 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=aMSjgK5KIY7Ul5KZENZFI4ZxF63rzo/waWE2nPirFyzrlC6+Aue+vV5O3SE2PoiZ2bcjaV6ZynSthuHXC0LNhohgrRmiJHtEA5OgnJ3+avOIvQeRbjWF5snHgCqWxgJ5J4K3sy+YSlvatoSdvsY0eEGeIbuMC8hztxEryH9p2TBrT39ptsntZghkUAM2DgSVPSsYU6rhzTY5KcsyH/xrFVhrWMl1FF/tmhBJFCk0MWXuOG5+WrFCFq4b1DzgMwdzE7NvMx/Y0qwIn0pCFa0KTTpoetnW0w39cH88xvJlYnfh4CPZFw/TitNemSqzqI/droOmkz1SLG9WS9i1LHcZJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=NXWcAGpGYTM1GyWLMa074F/PLliQUrToa7R+JYIFycM=; b=lM5Abp48v7Pvb6NI4Ic2OmsACSsA6D9NYYJMknYBtEYNgfHv3pSpZ5gpChwCgIqJi3B/+2q5bm+V8OvZULhMWKMWEd3ryvUUEZYh78MuvtWGdQgrB7uBfXqz372GL/MhFOySykf3AkNn6XPM6tjTC7Ya3sExoDibcoNGNMILRbboZEqj6bv+BwTQw1r97B48iMg9/BIUzsqlUiTkO8N+vgF17LiAjGYbOokGlbvFgUGRNZOow/SH7Oi7X4qtyg9UweooGotrLMx1rrFpFUQELcJDjb1hh+WtyLisJL883j/grQPrfEdGx4B5youEcHsvHdCL62V3GWv7p11hcoV8Gg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=nongnu.org smtp.mailfrom=xilinx.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=NXWcAGpGYTM1GyWLMa074F/PLliQUrToa7R+JYIFycM=; b=SE+H95p5VGouZ+bVbS0o/C+gyRr/giLTAlHdT5wyxVdnoBcjtvqVyBaCxAWqEDbUAEc2c7AeYjCis3KLuhRRJJUlLKVKh2UqHZcxcTsZohiFYqP5UXKyEgQzXmU5W/CHGcqc8YGnUNdItVEWO1ZW1u9DwLdUSuZV8kh2JgUV+Vc= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch02.xlnx.xilinx.com; From: Francisco Iglesias To: Subject: [PATCH v2 08/10] hw/block/m25p80: Add support for Micron Xccela flash mt35xu01g Date: Tue, 23 Nov 2021 10:34:26 +0000 Message-ID: <20211123103428.8765-9-francisco.iglesias@xilinx.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20211123103428.8765-1-francisco.iglesias@xilinx.com> References: <20211123103428.8765-1-francisco.iglesias@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f4dac913-a51c-4fe9-6f47-08d9ae6ceb9f X-MS-TrafficTypeDiagnostic: MW2PR02MB3785: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:3044; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0KB3aYV178r4cmI4nlgZfOy7UEIC8mlr2s6uqIXwZhxIzqjEpPu9Pa2gCkYcPjtftGByComd+wjsms0ADA20TkwqIN4B4GhIAPgzHeFpcIbG+B999Ggk6YibKXs1qDi0+y4VImgfViuUlErOmle8+f6AVkSkt3DnPbETCbZH5+xtSuwkmF/B5q+/78WDHYWuBdvPZohkzyqXxA9Le7zBZ86VTUDE3LXJS40HBd1BFoRv6k+/R6Cp8K3+Gf/G4gNLk+K5cCR4I1pDbCeZf53x/e8gi7oG3tgR+0e289pWTY6mL+6FkLgnckcRnVYxrGsHp30nvH2x/J8+P4COUmA67smLQFLdVA8ngEnvxOmZiBN5W1fv7pDV8wN+Lhdy8oAbdJE++wzSkBITsqwPt3xM/G/Mwcy146DWfki3kje4sjkwTPheYd8ynW/Ka7mTHVDQ8gKdBkn5Q38nzljqIdm4xZILa2bYvqxvsEw//IrPySYvak5/eo5+pPMndThiiFm9QJ+m7l6SZrNT3OOaHk4r7pTiRbgy7WYwcgoScDbL0XDC+NKEeA7G26BGQiKyl6Be7mjSCmUyJhYEkhew8QWM3yGfiqn2C3wsE/wRqGSDhG8+Jhbw3kmmc8jXpptDuaYvKW5detjkcyg66wkWGMp0pT7V74p5AySIaRQ3uN0Br31a+8m+yjxAnAMjrhYFaLpDyy13gBazZiZ2qbbZEjQNmFhc2lVZmTDh+cc8G5BhUik= X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(36840700001)(46966006)(2616005)(508600001)(83380400001)(426003)(54906003)(356005)(2906002)(1076003)(4326008)(47076005)(186003)(26005)(6916009)(336012)(44832011)(36860700001)(70206006)(7696005)(8676002)(9786002)(6666004)(4744005)(8936002)(316002)(70586007)(5660300002)(36906005)(36756003)(82310400004)(7636003)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2021 10:35:08.0931 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f4dac913-a51c-4fe9-6f47-08d9ae6ceb9f X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT062.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR02MB3785 Received-SPF: pass client-ip=40.107.102.84; envelope-from=figlesia@xilinx.com; helo=NAM04-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, peter.maydell@linaro.org, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1637663964546100005 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for Micron Xccela flash mt35xu01g. Signed-off-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias --- hw/block/m25p80.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index b77503dc84..c6bf3c6bfa 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -255,6 +255,8 @@ static const FlashPartInfo known_devices[] =3D { { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) }, { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K= ) }, + { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024, + ER_4K | ER_32K, 2) }, { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4= ) }, { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4= ) }, { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2= ) }, --=20 2.11.0 From nobody Fri Apr 19 16:53:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail(p=none dis=none) header.from=xilinx.com ARC-Seal: i=2; a=rsa-sha256; t=1637663953; cv=pass; d=zohomail.com; s=zohoarc; b=dsmWQjl2EiFncuwe0PNSeGOZmpKxOUyhMyN4nVn3s0V6vPm4Cqghm/zLCLmDsD2Eh3HnHB4xin5LdIpCGLAkK6qDdPP1xCHC1MUedrfzceonCn6YEfApPxYtxkyhgqgycvCwIg7UAQVFzD0n+/uu5KKKx1xlbYv96sv8SdhycPk= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637663953; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nTly0d94gic82VG47etT7iSF+7nThg9n+fRtCh2LOd0=; b=NZg/oDFttqD2Ec1rNdE04LCbiILjKi4MXpylL0A/G9quLtj1HNUjBLn2pMK3KrHwvDiljlfdD96qPGqrcks5fQLAaBuaC4mfA2uZQ6dIABxrM51QqYRcPaGIPTpJw85k6wAITH7u0HSpUGVdQKPE5ftmWMBYjVW/jfXsJVCPej4= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637663953586529.3203510082017; Tue, 23 Nov 2021 02:39:13 -0800 (PST) Received: from localhost ([::1]:42534 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mpTCh-0004eH-Ba for importer@patchew.org; Tue, 23 Nov 2021 05:39:11 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60480) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpT8U-0004pk-Qb for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:34:50 -0500 Received: from mail-dm6nam10on2083.outbound.protection.outlook.com ([40.107.93.83]:34657 helo=NAM10-DM6-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpT8S-0000hv-Su for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:34:50 -0500 Received: from DM5PR13CA0050.namprd13.prod.outlook.com (2603:10b6:3:117::12) by DM5PR02MB2827.namprd02.prod.outlook.com (2603:10b6:3:109::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.19; Tue, 23 Nov 2021 10:34:46 +0000 Received: from DM3NAM02FT035.eop-nam02.prod.protection.outlook.com (2603:10b6:3:117:cafe::13) by DM5PR13CA0050.outlook.office365.com (2603:10b6:3:117::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.20 via Frontend Transport; Tue, 23 Nov 2021 10:34:46 +0000 Received: from xsj-pvapexch01.xlnx.xilinx.com (149.199.62.198) by DM3NAM02FT035.mail.protection.outlook.com (10.13.4.78) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4713.19 via Frontend Transport; Tue, 23 Nov 2021 10:34:46 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 23 Nov 2021 02:34:45 -0800 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 23 Nov 2021 02:34:45 -0800 Received: from [10.23.120.28] (port=57995 helo=debian.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mpT8P-000GX6-K3; Tue, 23 Nov 2021 02:34:45 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=FpKdW28makDy+ngtUFoDKP6g/h05bSXX/v9jecwT7fQ70JfcRtonAxHH1ZMu7xbvu80p5gPAD/sRMay6x4W/2HRi1Tf/f9FdvIQUOh9acTaOluGrqrJk/Q3XDs+5NMQ8OLbDnok5LMSh3/ye40yAkGcvNF14CIHm8c94cpT3K1egpBOc/TTkWwpjiU22um+TxwNseEA1ar0OrRi+sJgjOnxR41lDF1QHucqbxrgojUjoiecorF1iyZLIGhogCz8oSUUpO92xvDt+eLIj9CEFUjhgXSQeshXZyxpNcZPXPVEfASa7yFRCQQOL8qskcAaQPo+sHXB8haUhEyPVTAC6Pw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=nTly0d94gic82VG47etT7iSF+7nThg9n+fRtCh2LOd0=; b=c/2fS0dFQhSPWaocDNphBjxCESte8nKRNPR2h3AXEA1PhPOv/BMmtBtUYdInPzsH9nea4oiMEgjXD+TDBJcD861UlTZHK/QKHZacqYFo3TlDwB+64m0QS2lRlwtPtS83nr9VdXGWhqtJOPd3cvlo9K9vHdNilU2vpPTTSEOkKJQ+SCxovotKL2w3eOsWaUwmCxq9UnGaOWWMp727b5J0y0cyH3iqtc9eenArfhXHIOuxMY8ZGa/myJZo5ONc2Pntpe3SjmefRFZuncvmB+lZP6RB2gepT6Lq9sTaZjRUBKWGmbJK3qQChzhd57QOyoiH2MlqVgTJAZ34NOddSZEAdA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=nongnu.org smtp.mailfrom=xilinx.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nTly0d94gic82VG47etT7iSF+7nThg9n+fRtCh2LOd0=; b=jjcTLQG9IXW37RdbRM/WIsujSCPQVHvbZm/VN9pVmmesu8IHMoWxIUvsQhEtPCbkPrNbjeWkFKxAZCO28JMko8W74ZPKukNYqBe4Ij8ipaI8Mupqc4ghyxz0xACnTiiuv59hCRPRWEIR1pCHTC8b1NNC38WtBQ7PoubsFk9ppkg= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch01.xlnx.xilinx.com; From: Francisco Iglesias To: Subject: [PATCH v2 09/10] hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI Date: Tue, 23 Nov 2021 10:34:27 +0000 Message-ID: <20211123103428.8765-10-francisco.iglesias@xilinx.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20211123103428.8765-1-francisco.iglesias@xilinx.com> References: <20211123103428.8765-1-francisco.iglesias@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f5519fd3-4efb-4208-7ecd-08d9ae6cdea7 X-MS-TrafficTypeDiagnostic: DM5PR02MB2827: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:130; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: b7RPNd8okVOMBHJRrSRH2byju65rf/kyYW4MyL1J68OPYFaNr6KYitOnBOeV41VLRUwh1fLmIoBDiP2rjC7j+0JEzu+b3PcyXWVLkuYFg5EUtaD6izmW+xWKodchlsUq5lUAXEn+/78UY/fGtBTdtLyMs5ruMvy/+w1ajErnbmjGC9SPjBHgzPLTMI+O3dSLeWL7yXoeKf5uHuq+SYvPLRDtDdJldBbkJl6dm1WJ/FWDXt8SER6hyBF0q9MWANy3P+79l4PsuqSGXwnCE5erJNkH+obsn0DXVRdmuI6mBXBwEMOghGeEkFZe8HpdDemD3bKnJI1wlhi5NXMtoYU9UowDyyj8FL6jcpXCYN6hPcZJ8r1FUr3E5nz8Fvz7I0cPzRa5ErbNox79W2fWeuxnajpxww0riIElbOPR2oJpftZooPQ+EGsrXomrixkLijp3C44C5oitRE+9lyKt0EteXEHTi9g8aUdDGm34bEGJrXR5UaEM+2QNHiDjzPSluUzJy8DgWcjrlvrAKT2oSkY70nIt6hNyaT1n+jN2PyD0QbRuZ6Mf1BOYk0UvgcsMagiEUpxvgeWRI5No1JqU1SP6JcRQrLdgilytPf8rQcSebbTuJxfPfXeh0Q6pRQtUoJAdKJv+iSxejvo57XG7F5VOLj1y+W0iWhhzm/FWxetUrBA7GqqVUxqp4Ty0TWELc3FfTB+cEWGjig9i8HYn9/yLxnBgewG19IvQb89F5FWeX68= X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch01.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(46966006)(36840700001)(36860700001)(6666004)(83380400001)(44832011)(356005)(186003)(82310400004)(336012)(47076005)(426003)(70206006)(8676002)(70586007)(7696005)(26005)(7636003)(54906003)(9786002)(36756003)(36906005)(316002)(508600001)(5660300002)(6916009)(8936002)(2616005)(1076003)(4326008)(2906002)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2021 10:34:46.3946 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f5519fd3-4efb-4208-7ecd-08d9ae6cdea7 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT035.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR02MB2827 Received-SPF: pass client-ip=40.107.93.83; envelope-from=figlesia@xilinx.com; helo=NAM10-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, peter.maydell@linaro.org, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1637663954756100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory controller. Signed-off-by: Francisco Iglesias --- hw/arm/xlnx-versal-virt.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index d2f55e29b6..47f5914e5d 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -25,6 +25,8 @@ #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt") OBJECT_DECLARE_SIMPLE_TYPE(VersalVirt, XLNX_VERSAL_VIRT_MACHINE) =20 +#define XLNX_VERSAL_NUM_OSPI_FLASH 4 + struct VersalVirt { MachineState parent_obj; =20 @@ -690,6 +692,27 @@ static void versal_virt_init(MachineState *machine) exit(EXIT_FAILURE); } } + + for (i =3D 0; i < XLNX_VERSAL_NUM_OSPI_FLASH; i++) { + BusState *spi_bus; + DeviceState *flash_dev; + qemu_irq cs_line; + DriveInfo *dinfo =3D drive_get(IF_MTD, 0, i); + + spi_bus =3D qdev_get_child_bus(DEVICE(&s->soc.pmc.iou.ospi), "spi0= "); + + flash_dev =3D qdev_new("mt35xu01g"); + if (dinfo) { + qdev_prop_set_drive_err(flash_dev, "drive", + blk_by_legacy_dinfo(dinfo), &error_fat= al); + } + qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal); + + cs_line =3D qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.pmc.iou.ospi), + i + 1, cs_line); + } } =20 static void versal_virt_machine_instance_init(Object *obj) --=20 2.11.0 From nobody Fri Apr 19 16:53:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail(p=none dis=none) header.from=xilinx.com ARC-Seal: i=2; a=rsa-sha256; t=1637663966; cv=pass; d=zohomail.com; s=zohoarc; b=IFgyYQRsuQrgYkl9+1/vBtpOWDlemDfmzrYCvqgbbJrJuolZb7llPaXMZavtNjEDYcCxdg+WaWdXfuY9O5Boci0N59Wy/LpMSJF1bksFtYcLtevYxatEgHMDToS8ec1jO57oy97h3ehepYrPWovwsRv9o/lO72E1LhJfAFFNQrE= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637663966; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cS8mHJY7T0TY8wWVIdrWCkbTICI5nV0X1YkuddzNAuc=; b=kppLtuQZlVikZBEeZBPZU6GMziVLy1XB6xOYFEdFjuyr8aXoG1rIf5ikvisM9ja+1JQnWwW5vkA/UvmjFbSLlFsUhzY7rpgDZf8CrcwTK9EwW/Dak87M5B40tCxx4gV3EEPbmZBMLbMZORiMlBtYKjCkyxYf+zTbpgTNbY66R+4= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637663966111300.1149597472514; Tue, 23 Nov 2021 02:39:26 -0800 (PST) Received: from localhost ([::1]:43806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mpTCu-0005Tx-2D for importer@patchew.org; Tue, 23 Nov 2021 05:39:24 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60624) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpT8v-0005bv-SL for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:35:17 -0500 Received: from mail-co1nam11on2059.outbound.protection.outlook.com ([40.107.220.59]:56160 helo=NAM11-CO1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mpT8t-0000kJ-IS for qemu-devel@nongnu.org; Tue, 23 Nov 2021 05:35:17 -0500 Received: from BN0PR02CA0025.namprd02.prod.outlook.com (2603:10b6:408:e4::30) by SJ0PR02MB8718.namprd02.prod.outlook.com (2603:10b6:a03:3e0::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.21; Tue, 23 Nov 2021 10:35:13 +0000 Received: from BN1NAM02FT051.eop-nam02.prod.protection.outlook.com (2603:10b6:408:e4:cafe::bf) by BN0PR02CA0025.outlook.office365.com (2603:10b6:408:e4::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.19 via Frontend Transport; Tue, 23 Nov 2021 10:35:12 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (149.199.62.198) by BN1NAM02FT051.mail.protection.outlook.com (10.13.2.159) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4713.19 via Frontend Transport; Tue, 23 Nov 2021 10:35:11 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 23 Nov 2021 02:34:47 -0800 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 23 Nov 2021 02:34:47 -0800 Received: from [10.23.120.28] (port=57995 helo=debian.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mpT8R-000GX6-8G; Tue, 23 Nov 2021 02:34:47 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=KYnxxkwscZ2mq1virvd+IIrJmpa02u1Tf7ixhqCm+tvUg1i2r1iHfSMmW0opfC+GZPyNdjWPtgfIfgwIgJz/jUJXHyyo4hIYsARCS4RqxXMsd7UscFCvNF+WIX57Q61BDIVZGDJoMZyeITAXSQHa4TA88m+BfQ2MawHzg2F1J/eTaJbaSRI307aBMIi2P4FsW9pRhBzQHvBDOnrG7u60wSVmfPgIUvgPqxxS4PmIRDvUtvqFx4x7tPqeEshw+OkjnNj2bqwXyxXX/YAl31+i5/NQ5uFkvaWrxCCFWq7Myx8hGuytwRMNfwgt9z4GcGr29SJrb7x5AK641mA31PfqHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=cS8mHJY7T0TY8wWVIdrWCkbTICI5nV0X1YkuddzNAuc=; b=IVOJP29/990rQp+K1REp9lV5rW/Pvlfj3DBq0E8Y8bVaaPwLPHAlHCtgaoAcmFF7d1iMcbRHhEMKCAkFxI3C+j5Klc6a6hCII9uqqCD7E+6DG88rzZDGgs+Sc/eOPVEcT43iKGaEkCeqretH4Z+ir0EziR719DSyK5K22T0rhIUMBWitMHCuT0IEyjZ4qZ7S1IWZleh+CFRQsMPQaopHXw5Yx66qZtK+iagZhDjBB/vocZWUOzuxDN8M3F6gyza0pqq95/Jkx0KXvViK/LnO/zfOGUe2wZQAAeY/4ibTA9D9p080qAiwetBEk1iB6N41/lb9kUvthZdU/+rXU7DJeg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=nongnu.org smtp.mailfrom=xilinx.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cS8mHJY7T0TY8wWVIdrWCkbTICI5nV0X1YkuddzNAuc=; b=QLu6NQqIfBqGf1XVz+OHV5MDibaSqcI0++pB0JPxNr10jqswj7uO94HLWYTjaH36jiiFNKCUHkdIp7amQEbEVmPRB3FA0l8fn6fA2svIknAUoChzJjDWtCHHitk1rReLnhlPgklqwJUJ8+djnDdW8ulgoVJX4OePlSjv8dJ9F4M= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch02.xlnx.xilinx.com; From: Francisco Iglesias To: Subject: [PATCH v2 10/10] MAINTAINERS: Add an entry for Xilinx Versal OSPI Date: Tue, 23 Nov 2021 10:34:28 +0000 Message-ID: <20211123103428.8765-11-francisco.iglesias@xilinx.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20211123103428.8765-1-francisco.iglesias@xilinx.com> References: <20211123103428.8765-1-francisco.iglesias@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 749df3b1-7ce3-48a1-1388-08d9ae6ced96 X-MS-TrafficTypeDiagnostic: SJ0PR02MB8718: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:2958; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: pNQR6/Y7liethSdO6FqYcBgMb56t4ltQDmjCvEtclczUxj3+7rRg2+YyjDpbEhxXEPBkM0WJqOIGmXg1Nd3aNiLgPuqTi+uUmIee2KAXcf3uNqusnCDLFN4s0i2pEQA7XgfBaQCNrdtDmZCba/wh/7nKB6EAK6PbBwo4J/pxsSLfNgwOeEoXC0wkWAkM7ULPe8wIvF+4KUC01YxpePZbkMfTzax/llHLKe0jRj/rXoH6Qh52U8Lcc9I2xcwjlTSqse27vJgp7eP17Xsx9yuK2UYvI3bW3FGgC0uUaNFlStuqCQOPeT6Guuob2Rap6cN6SrrDHnOHYEVk8ddlY7edY9nJvVD4UQ+zkQ513Epc2mL++qv5InKGydIOsM9qJIOWuSmX4eWIrBY3ay8eI5/rw0+C3xrOKUHqhkwpYVCwJnkyoGabjmn+qObnWCqlOWhyvp8IKMRqLe4G/m3IIb6GRQxermD+5oq2BexfMFBSrk+DQLOpANTC2WwD6LJSfRM6H9dqIR41vXbdj3bc7Fx4yYZETXM/KHr+RrZKdAY1uyty1EwRDSHuk3gBX7bX1E8S/sUm0VzWzlsKQv3liQcTkuWrQEVRDfli9igELtko7emPRY+cKHT97WLXN90pa0u1RCfWiHSiuhRmS0XjwfLaKHxRk2nOIme+NavUl5HHrJOSUC4pfPbZuTb/lNLlIzv9nqU6S3Y/wUjEsojv6ed67lzRCEJTBHtNcf60RSiiJSM= X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(36840700001)(46966006)(336012)(6666004)(70586007)(426003)(186003)(36756003)(6916009)(70206006)(8676002)(47076005)(26005)(44832011)(82310400004)(356005)(8936002)(2616005)(1076003)(7696005)(7636003)(36906005)(54906003)(36860700001)(9786002)(5660300002)(4744005)(316002)(2906002)(4326008)(508600001)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2021 10:35:11.3883 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 749df3b1-7ce3-48a1-1388-08d9ae6ced96 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT051.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR02MB8718 Received-SPF: pass client-ip=40.107.220.59; envelope-from=figlesia@xilinx.com; helo=NAM11-CO1-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, peter.maydell@linaro.org, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1637663966991100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" List myself as maintainer for the Xilinx Versal OSPI controller. Signed-off-by: Francisco Iglesias --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d3879aa3c1..8c2b01a282 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -963,6 +963,12 @@ F: hw/display/dpcd.c F: include/hw/display/dpcd.h F: docs/system/arm/xlnx-versal-virt.rst =20 +Xilinx Versal OSPI +M: Francisco Iglesias +S: Maintained +F: hw/ssi/xlnx-versal-ospi.c +F: include/hw/ssi/xlnx-versal-ospi.h + ARM ACPI Subsystem M: Shannon Zhao L: qemu-arm@nongnu.org --=20 2.11.0