From nobody Sat May 4 06:24:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1637497854; cv=none; d=zohomail.com; s=zohoarc; b=ZJJ3O5hdPcExbBj0RWmkL91tt+UYIVmxKChmQLeTcNlHcaxHS48mjHCaT13muURKywzfS6Aw6X3Oyl5Gfj1PRH8//miltjCjmiXXY5/jD3mRrWmiaEc5AiQvlnZgHfWf5xyM8uF7v8cnlSqjZmtIpv5DFWHUADDw3KbfzWCyzAQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637497854; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ooyrJuKyczM0c8Rh1GVy44W4Y+ttWwczgVJf8O2GUzU=; b=C339IvLlpLs9a2pMA6VXHl+2IqP2jWvA1+Lhr/mWjfmgMub5W9f4uLiXDRwaBTnSurJyYoHPnKgotUkQLcQCViyRVgPo8yFDv+x3WzE/wOst80w0tfONL3SP9Uk0LPeNW06BvTYxNyIr8IFDYyVc8L6b7EIPefk/LNFdt6W0U/4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637497854579962.5330025115233; Sun, 21 Nov 2021 04:30:54 -0800 (PST) Received: from localhost ([::1]:37006 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1molzh-0007Av-Fh for importer@patchew.org; Sun, 21 Nov 2021 07:30:53 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52670) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1moluM-0003pG-UG; Sun, 21 Nov 2021 07:25:22 -0500 Received: from szxga08-in.huawei.com ([45.249.212.255]:2906) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1moluH-0005l5-ST; Sun, 21 Nov 2021 07:25:22 -0500 Received: from dggpemm500023.china.huawei.com (unknown [172.30.72.54]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4HxqKq5MX1z1DJQV; Sun, 21 Nov 2021 20:22:39 +0800 (CST) Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Sun, 21 Nov 2021 20:25:07 +0800 To: , CC: Peter Maydell , Andrew Jones , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Paolo Bonzini , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Markus Armbruster , Eric Blake , , Yanan Wang Subject: [PATCH v4 01/10] qemu-options: Improve readability of SMP related Docs Date: Sun, 21 Nov 2021 20:24:53 +0800 Message-ID: <20211121122502.9844-2-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20211121122502.9844-1-wangyanan55@huawei.com> References: <20211121122502.9844-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.255; envelope-from=wangyanan55@huawei.com; helo=szxga08-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Yanan Wang From: Yanan Wang via X-ZM-MESSAGEID: 1637497854945100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We have a description in qemu-options.hx for each CPU topology parameter to explain what it exactly means, and also an extra declaration for the target-specific one, e.g. "for PC only" when describing "dies", and "for PC, it's on one die" when describing "cores". Now we are going to introduce one more non-generic parameter "clusters", it will make the Doc less readable and if we still continue to use the legacy way to describe it. So let's at first make two tweaks of the Docs to improve the readability and also scalability: 1) In the -help text: Delete the extra specific declaration and describe each topology parameter level by level. Then add a note to declare that different machines may support different subsets and the actual meaning of the supported parameters will vary accordingly. 2) In the rST text: List all the sub-hierarchies currently supported in QEMU, and correspondingly give an example of -smp configuration for each of them. Signed-off-by: Yanan Wang --- qemu-options.hx | 76 ++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 59 insertions(+), 17 deletions(-) diff --git a/qemu-options.hx b/qemu-options.hx index ae2c6dbbfc..7a59db7764 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -207,14 +207,26 @@ ERST =20 DEF("smp", HAS_ARG, QEMU_OPTION_smp, "-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus][,sockets=3Dsockets][,dies=3Ddie= s][,cores=3Dcores][,threads=3Dthreads]\n" - " set the number of CPUs to 'n' [default=3D1]\n" + " set the number of initial CPUs to 'n' [default=3D1]\n" " maxcpus=3D maximum number of total CPUs, including\n" " offline CPUs for hotplug, etc\n" - " sockets=3D number of discrete sockets in the system\n" - " dies=3D number of CPU dies on one socket (for PC only= )\n" - " cores=3D number of CPU cores on one socket (for PC, i= t's on one die)\n" - " threads=3D number of threads on one CPU core\n", - QEMU_ARCH_ALL) + " sockets=3D number of sockets on the machine board\n" + " dies=3D number of dies in one socket\n" + " cores=3D number of cores in one die\n" + " threads=3D number of threads in one core\n" + "Note: Different machines may have different subsets of the CPU topolo= gy\n" + " parameters supported, so the actual meaning of the supported pa= rameters\n" + " will vary accordingly. For example, for a machine type that sup= ports a\n" + " three-level CPU hierarchy of sockets/cores/threads, the paramet= ers will\n" + " sequentially mean as below:\n" + " sockets means the number of sockets on the machine bo= ard\n" + " cores means the number of cores in one socket\n" + " threads means the number of threads in one core\n" + " For a particular machine type board, an expected CPU topology h= ierarchy\n" + " can be defined through the supported sub-option. Unsupported pa= rameters\n" + " can also be provided in addition to the sub-option, but their v= alues\n" + " must be set as 1 in the purpose of correct parsing.\n", + QEMU_ARCH_ALL) SRST ``-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus][,sockets=3Dsockets][,dies=3Ddies][= ,cores=3Dcores][,threads=3Dthreads]`` Simulate a SMP system with '\ ``n``\ ' CPUs initially present on @@ -225,27 +237,57 @@ SRST initial CPU count will match the maximum number. When only one of them is given then the omitted one will be set to its counterpart's value. Both parameters may be specified, but the maximum number of CPUs must - be equal to or greater than the initial CPU count. Both parameters are - subject to an upper limit that is determined by the specific machine - type chosen. - - To control reporting of CPU topology information, the number of socket= s, - dies per socket, cores per die, and threads per core can be specified. - The sum `` sockets * cores * dies * threads `` must be equal to the - maximum CPU count. CPU targets may only support a subset of the topolo= gy - parameters. Where a CPU target does not support use of a particular - topology parameter, its value should be assumed to be 1 for the purpose - of computing the CPU maximum count. + be equal to or greater than the initial CPU count. Product of the + CPU topology hierarchy must be equal to the maximum number of CPUs. + Both parameters are subject to an upper limit that is determined by + the specific machine type chosen. + + To control reporting of CPU topology information, values of the topolo= gy + parameters can be specified. Machines may only support a subset of the + parameters and different machines may have different subsets supported + which vary depending on capacity of the corresponding CPU targets. So + for a particular machine type board, an expected topology hierarchy can + be defined through the supported sub-option. Unsupported parameters can + also be provided in addition to the sub-option, but their values must = be + set as 1 in the purpose of correct parsing. =20 Either the initial CPU count, or at least one of the topology paramete= rs must be specified. The specified parameters must be greater than zero, explicit configuration like "cpus=3D0" is not allowed. Values for any omitted parameters will be computed from those which are given. + + For example, the following sub-option defines a CPU topology hierarchy + (2 sockets totally on the machine, 2 cores per socket, 2 threads per + core) for a machine that only supports sockets/cores/threads. + Some members of the option can be omitted but their values will be + automatically computed: + + :: + + -smp 8,sockets=3D2,cores=3D2,threads=3D2,maxcpus=3D8 + + The following sub-option defines a CPU topology hierarchy (2 sockets + totally on the machine, 2 dies per socket, 2 cores per die, 2 threads + per core) for PC machines which support sockets/dies/cores/threads. + Some members of the option can be omitted but their values will be + automatically computed: + + :: + + -smp 16,sockets=3D2,dies=3D2,cores=3D2,threads=3D2,maxcpus=3D16 + Historically preference was given to the coarsest topology parameters when computing missing values (ie sockets preferred over cores, which were preferred over threads), however, this behaviour is considered liable to change. Prior to 6.2 the preference was sockets over cores over threads. Since 6.2 the preference is cores over sockets over thre= ads. + + For example, the following option defines a machine board with 2 socke= ts + of 1 core before 6.2 and 1 socket of 2 cores after 6.2: + + :: + + -smp 2 ERST =20 DEF("numa", HAS_ARG, QEMU_OPTION_numa, --=20 2.19.1 From nobody Sat May 4 06:24:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1637497786; cv=none; d=zohomail.com; s=zohoarc; b=n64JBrDoCBGaZeoMAvNfClwg18tKckHbdH5BnFRXKYztCihWlHVGws/TDQEURDBDPigw0Wiecv+D8zzSIxLb63pdeKYsHX1Vd19TInTg8V+XT2XHRnq1W0+TwnylXosNbXyl7dV+Gp2ofk8tFPB/W2QVe3c5srEDJ4PiDU4alvI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637497786; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=0BmAipZEhx596xvQoQRc+hpmPE6fQzqmQ5vA03E791Y=; b=CwVegZn6YtxzwYik8D7sDnTd6fjynXiDdSPvBQjmYjUDEQvjGduct+ooecdSLJENPaoVz94t7A446Iqn2kVC1Y2Xo4Qu4JLUJ2DH1OBx2r8jjFrdQfWaSWhTfeCwC/yCKj7UafVtW0LZ9CiOZRZ6PBOkXgj8WUhDG+i7JmGv+6M= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637497786566924.0771228382534; Sun, 21 Nov 2021 04:29:46 -0800 (PST) Received: from localhost ([::1]:32828 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1molyb-0004Np-EZ for importer@patchew.org; Sun, 21 Nov 2021 07:29:45 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52666) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1moluM-0003pF-TK; Sun, 21 Nov 2021 07:25:22 -0500 Received: from szxga01-in.huawei.com ([45.249.212.187]:3501) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1moluH-0005lV-TQ; Sun, 21 Nov 2021 07:25:22 -0500 Received: from dggpemm500023.china.huawei.com (unknown [172.30.72.55]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4HxqKr55ypzVfmC; Sun, 21 Nov 2021 20:22:40 +0800 (CST) Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Sun, 21 Nov 2021 20:25:08 +0800 To: , CC: Peter Maydell , Andrew Jones , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Paolo Bonzini , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Markus Armbruster , Eric Blake , , Yanan Wang Subject: [PATCH v4 02/10] hw/core/machine: Introduce CPU cluster topology support Date: Sun, 21 Nov 2021 20:24:54 +0800 Message-ID: <20211121122502.9844-3-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20211121122502.9844-1-wangyanan55@huawei.com> References: <20211121122502.9844-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.187; envelope-from=wangyanan55@huawei.com; helo=szxga01-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Yanan Wang From: Yanan Wang via X-ZM-MESSAGEID: 1637497788069100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The new Cluster-Aware Scheduling support has landed in Linux 5.16, which has been proved to benefit the scheduling performance (e.g. load balance and wake_affine strategy) on both x86_64 and AArch64. So now in Linux 5.16 we have four-level arch-neutral CPU topology definition like below and a new scheduler level for clusters. struct cpu_topology { int thread_id; int core_id; int cluster_id; int package_id; int llc_id; cpumask_t thread_sibling; cpumask_t core_sibling; cpumask_t cluster_sibling; cpumask_t llc_sibling; } A cluster generally means a group of CPU cores which share L2 cache or other mid-level resources, and it is the shared resources that is used to improve scheduler's behavior. From the point of view of the size range, it's between CPU die and CPU core. For example, on some ARM64 Kunpeng servers, we have 6 clusters in each NUMA node, and 4 CPU cores in each cluster. The 4 CPU cores share a separate L2 cache and a L3 cache tag, which brings cache affinity advantage. In virtualization, on the Hosts which have pClusters, if we can design a vCPU topology with cluster level for guest kernel and have a dedicated vCPU pinning. A Cluster-Aware Guest kernel can also make use of the cache affinity of CPU clusters to gain similar scheduling performance. This patch adds infrastructure for CPU cluster level topology configuration and parsing, so that the user can specify cluster parameter if their machines support it. Signed-off-by: Yanan Wang --- hw/core/machine-smp.c | 26 +++++++++++++++++++------- hw/core/machine.c | 3 +++ include/hw/boards.h | 6 +++++- qapi/machine.json | 5 ++++- qemu-options.hx | 7 ++++--- softmmu/vl.c | 3 +++ 6 files changed, 38 insertions(+), 12 deletions(-) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index 116a0cbbfa..87ceb45470 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -37,6 +37,10 @@ static char *cpu_hierarchy_to_string(MachineState *ms) g_string_append_printf(s, " * dies (%u)", ms->smp.dies); } =20 + if (mc->smp_props.clusters_supported) { + g_string_append_printf(s, " * clusters (%u)", ms->smp.clusters); + } + g_string_append_printf(s, " * cores (%u)", ms->smp.cores); g_string_append_printf(s, " * threads (%u)", ms->smp.threads); =20 @@ -69,6 +73,7 @@ void smp_parse(MachineState *ms, SMPConfiguration *config= , Error **errp) unsigned cpus =3D config->has_cpus ? config->cpus : 0; unsigned sockets =3D config->has_sockets ? config->sockets : 0; unsigned dies =3D config->has_dies ? config->dies : 0; + unsigned clusters =3D config->has_clusters ? config->clusters : 0; unsigned cores =3D config->has_cores ? config->cores : 0; unsigned threads =3D config->has_threads ? config->threads : 0; unsigned maxcpus =3D config->has_maxcpus ? config->maxcpus : 0; @@ -80,6 +85,7 @@ void smp_parse(MachineState *ms, SMPConfiguration *config= , Error **errp) if ((config->has_cpus && config->cpus =3D=3D 0) || (config->has_sockets && config->sockets =3D=3D 0) || (config->has_dies && config->dies =3D=3D 0) || + (config->has_clusters && config->clusters =3D=3D 0) || (config->has_cores && config->cores =3D=3D 0) || (config->has_threads && config->threads =3D=3D 0) || (config->has_maxcpus && config->maxcpus =3D=3D 0)) { @@ -95,8 +101,13 @@ void smp_parse(MachineState *ms, SMPConfiguration *conf= ig, Error **errp) error_setg(errp, "dies not supported by this machine's CPU topolog= y"); return; } + if (!mc->smp_props.clusters_supported && clusters > 1) { + error_setg(errp, "clusters not supported by this machine's CPU top= ology"); + return; + } =20 dies =3D dies > 0 ? dies : 1; + clusters =3D clusters > 0 ? clusters : 1; =20 /* compute missing values based on the provided ones */ if (cpus =3D=3D 0 && maxcpus =3D=3D 0) { @@ -111,41 +122,42 @@ void smp_parse(MachineState *ms, SMPConfiguration *co= nfig, Error **errp) if (sockets =3D=3D 0) { cores =3D cores > 0 ? cores : 1; threads =3D threads > 0 ? threads : 1; - sockets =3D maxcpus / (dies * cores * threads); + sockets =3D maxcpus / (dies * clusters * cores * threads); } else if (cores =3D=3D 0) { threads =3D threads > 0 ? threads : 1; - cores =3D maxcpus / (sockets * dies * threads); + cores =3D maxcpus / (sockets * dies * clusters * threads); } } else { /* prefer cores over sockets since 6.2 */ if (cores =3D=3D 0) { sockets =3D sockets > 0 ? sockets : 1; threads =3D threads > 0 ? threads : 1; - cores =3D maxcpus / (sockets * dies * threads); + cores =3D maxcpus / (sockets * dies * clusters * threads); } else if (sockets =3D=3D 0) { threads =3D threads > 0 ? threads : 1; - sockets =3D maxcpus / (dies * cores * threads); + sockets =3D maxcpus / (dies * clusters * cores * threads); } } =20 /* try to calculate omitted threads at last */ if (threads =3D=3D 0) { - threads =3D maxcpus / (sockets * dies * cores); + threads =3D maxcpus / (sockets * dies * clusters * cores); } } =20 - maxcpus =3D maxcpus > 0 ? maxcpus : sockets * dies * cores * threads; + maxcpus =3D maxcpus > 0 ? maxcpus : sockets * dies * clusters * cores = * threads; cpus =3D cpus > 0 ? cpus : maxcpus; =20 ms->smp.cpus =3D cpus; ms->smp.sockets =3D sockets; ms->smp.dies =3D dies; + ms->smp.clusters =3D clusters; ms->smp.cores =3D cores; ms->smp.threads =3D threads; ms->smp.max_cpus =3D maxcpus; =20 /* sanity-check of the computed topology */ - if (sockets * dies * cores * threads !=3D maxcpus) { + if (sockets * dies * clusters * cores * threads !=3D maxcpus) { g_autofree char *topo_msg =3D cpu_hierarchy_to_string(ms); error_setg(errp, "Invalid CPU topology: " "product of the hierarchy must match maxcpus: " diff --git a/hw/core/machine.c b/hw/core/machine.c index 53a99abc56..d4fa6e0306 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -742,10 +742,12 @@ static void machine_get_smp(Object *obj, Visitor *v, = const char *name, .has_cpus =3D true, .cpus =3D ms->smp.cpus, .has_sockets =3D true, .sockets =3D ms->smp.sockets, .has_dies =3D true, .dies =3D ms->smp.dies, + .has_clusters =3D true, .clusters =3D ms->smp.clusters, .has_cores =3D true, .cores =3D ms->smp.cores, .has_threads =3D true, .threads =3D ms->smp.threads, .has_maxcpus =3D true, .maxcpus =3D ms->smp.max_cpus, }; + if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) { return; } @@ -932,6 +934,7 @@ static void machine_initfn(Object *obj) ms->smp.max_cpus =3D mc->default_cpus; ms->smp.sockets =3D 1; ms->smp.dies =3D 1; + ms->smp.clusters =3D 1; ms->smp.cores =3D 1; ms->smp.threads =3D 1; } diff --git a/include/hw/boards.h b/include/hw/boards.h index 9c1c190104..1a136edb0e 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -128,10 +128,12 @@ typedef struct { * SMPCompatProps: * @prefer_sockets - whether sockets are preferred over cores in smp parsi= ng * @dies_supported - whether dies are supported by the machine + * @clusters_supported - whether clusters are supported by the machine */ typedef struct { bool prefer_sockets; bool dies_supported; + bool clusters_supported; } SMPCompatProps; =20 /** @@ -298,7 +300,8 @@ typedef struct DeviceMemoryState { * @cpus: the number of present logical processors on the machine * @sockets: the number of sockets on the machine * @dies: the number of dies in one socket - * @cores: the number of cores in one die + * @clusters: the number of clusters in one die + * @cores: the number of cores in one cluster * @threads: the number of threads in one core * @max_cpus: the maximum number of logical processors on the machine */ @@ -306,6 +309,7 @@ typedef struct CpuTopology { unsigned int cpus; unsigned int sockets; unsigned int dies; + unsigned int clusters; unsigned int cores; unsigned int threads; unsigned int max_cpus; diff --git a/qapi/machine.json b/qapi/machine.json index 067e3f5378..b9dd8f7f90 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -1396,7 +1396,9 @@ # # @dies: number of dies per socket in the CPU topology # -# @cores: number of cores per die in the CPU topology +# @clusters: number of clusters per die in the CPU topology +# +# @cores: number of cores per cluster in the CPU topology # # @threads: number of threads per core in the CPU topology # @@ -1408,6 +1410,7 @@ '*cpus': 'int', '*sockets': 'int', '*dies': 'int', + '*clusters': 'int', '*cores': 'int', '*threads': 'int', '*maxcpus': 'int' } } diff --git a/qemu-options.hx b/qemu-options.hx index 7a59db7764..0f26f7dad7 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -206,13 +206,14 @@ SRST ERST =20 DEF("smp", HAS_ARG, QEMU_OPTION_smp, - "-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus][,sockets=3Dsockets][,dies=3Ddie= s][,cores=3Dcores][,threads=3Dthreads]\n" + "-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus][,sockets=3Dsockets][,dies=3Ddie= s][,clusters=3Dclusters][,cores=3Dcores][,threads=3Dthreads]\n" " set the number of initial CPUs to 'n' [default=3D1]\n" " maxcpus=3D maximum number of total CPUs, including\n" " offline CPUs for hotplug, etc\n" " sockets=3D number of sockets on the machine board\n" " dies=3D number of dies in one socket\n" - " cores=3D number of cores in one die\n" + " clusters=3D number of clusters in one die\n" + " cores=3D number of cores in one cluster\n" " threads=3D number of threads in one core\n" "Note: Different machines may have different subsets of the CPU topolo= gy\n" " parameters supported, so the actual meaning of the supported pa= rameters\n" @@ -228,7 +229,7 @@ DEF("smp", HAS_ARG, QEMU_OPTION_smp, " must be set as 1 in the purpose of correct parsing.\n", QEMU_ARCH_ALL) SRST -``-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus][,sockets=3Dsockets][,dies=3Ddies][= ,cores=3Dcores][,threads=3Dthreads]`` +``-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus][,sockets=3Dsockets][,dies=3Ddies][= ,clusters=3Dclusters][,cores=3Dcores][,threads=3Dthreads]`` Simulate a SMP system with '\ ``n``\ ' CPUs initially present on the machine type board. On boards supporting CPU hotplug, the optional '\ ``maxcpus``\ ' parameter can be set to enable further CPUs to be diff --git a/softmmu/vl.c b/softmmu/vl.c index 1159a64bce..7acf06dace 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -726,6 +726,9 @@ static QemuOptsList qemu_smp_opts =3D { }, { .name =3D "dies", .type =3D QEMU_OPT_NUMBER, + }, { + .name =3D "clusters", + .type =3D QEMU_OPT_NUMBER, }, { .name =3D "cores", .type =3D QEMU_OPT_NUMBER, --=20 2.19.1 From nobody Sat May 4 06:24:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1637497792; cv=none; d=zohomail.com; s=zohoarc; b=iu3XeoYo786JCTr8jNzXuRgbo1KF1wka72g1sgAIYxkmkSbYlvcei8PA3/P0EI79inQ1pH7QjWpsBeRzanCXAdHbocNz/Uhv3wI3+hgN7TU5hkx4glqPpiM7JGbBlrOpAU2g5fXtvn9bVS3I3caw6a/FK66lLV+j52K0mzZ2630= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637497792; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=D11uErHDWrQ5VhxDO3SN2n1bILC2nrof1TU5WeVD6LI=; b=RZcl4MLcs548wu361YqbqjRGQ6Ymbd3BsY30rxHfX3wSYEMCi9qERMeU2Vc78WS5Ouyok16vPKMupFWr43DDesu4DUKKs6NupG2z9fpmOHgBMvhplirCxbpuMTDZmFbh2ihYF5IdcZAh6+U55SXPT+2tm8X8OiSIbZwA2NrUm6A= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637497792491584.7353962035767; Sun, 21 Nov 2021 04:29:52 -0800 (PST) Received: from localhost ([::1]:33534 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1molyh-0004qj-FL for importer@patchew.org; Sun, 21 Nov 2021 07:29:51 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52664) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1moluM-0003pE-R5; Sun, 21 Nov 2021 07:25:22 -0500 Received: from szxga02-in.huawei.com ([45.249.212.188]:2841) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1moluH-0005lb-Sp; Sun, 21 Nov 2021 07:25:22 -0500 Received: from dggpemm500023.china.huawei.com (unknown [172.30.72.53]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4HxqH002M5zbhph; Sun, 21 Nov 2021 20:20:12 +0800 (CST) Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Sun, 21 Nov 2021 20:25:09 +0800 To: , CC: Peter Maydell , Andrew Jones , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Paolo Bonzini , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Markus Armbruster , Eric Blake , , Yanan Wang Subject: [PATCH v4 03/10] hw/core/machine: Wrap target specific parameters together Date: Sun, 21 Nov 2021 20:24:55 +0800 Message-ID: <20211121122502.9844-4-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20211121122502.9844-1-wangyanan55@huawei.com> References: <20211121122502.9844-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.188; envelope-from=wangyanan55@huawei.com; helo=szxga02-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Yanan Wang From: Yanan Wang via X-ZM-MESSAGEID: 1637497794338100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Wrap the CPU target specific parameters together into a single variable, so that we don't need to update the other lines but a single line when new topology parameters are introduced. No functional change intended. Signed-off-by: Yanan Wang --- hw/core/machine-smp.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index 87ceb45470..2a3f16e52b 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -77,6 +77,7 @@ void smp_parse(MachineState *ms, SMPConfiguration *config= , Error **errp) unsigned cores =3D config->has_cores ? config->cores : 0; unsigned threads =3D config->has_threads ? config->threads : 0; unsigned maxcpus =3D config->has_maxcpus ? config->maxcpus : 0; + unsigned others; =20 /* * Specified CPU topology parameters must be greater than zero, @@ -109,6 +110,8 @@ void smp_parse(MachineState *ms, SMPConfiguration *conf= ig, Error **errp) dies =3D dies > 0 ? dies : 1; clusters =3D clusters > 0 ? clusters : 1; =20 + others =3D dies * clusters; + /* compute missing values based on the provided ones */ if (cpus =3D=3D 0 && maxcpus =3D=3D 0) { sockets =3D sockets > 0 ? sockets : 1; @@ -122,30 +125,30 @@ void smp_parse(MachineState *ms, SMPConfiguration *co= nfig, Error **errp) if (sockets =3D=3D 0) { cores =3D cores > 0 ? cores : 1; threads =3D threads > 0 ? threads : 1; - sockets =3D maxcpus / (dies * clusters * cores * threads); + sockets =3D maxcpus / (cores * threads * others); } else if (cores =3D=3D 0) { threads =3D threads > 0 ? threads : 1; - cores =3D maxcpus / (sockets * dies * clusters * threads); + cores =3D maxcpus / (sockets * threads * others); } } else { /* prefer cores over sockets since 6.2 */ if (cores =3D=3D 0) { sockets =3D sockets > 0 ? sockets : 1; threads =3D threads > 0 ? threads : 1; - cores =3D maxcpus / (sockets * dies * clusters * threads); + cores =3D maxcpus / (sockets * threads * others); } else if (sockets =3D=3D 0) { threads =3D threads > 0 ? threads : 1; - sockets =3D maxcpus / (dies * clusters * cores * threads); + sockets =3D maxcpus / (cores * threads * others); } } =20 /* try to calculate omitted threads at last */ if (threads =3D=3D 0) { - threads =3D maxcpus / (sockets * dies * clusters * cores); + threads =3D maxcpus / (sockets * cores * others); } } =20 - maxcpus =3D maxcpus > 0 ? maxcpus : sockets * dies * clusters * cores = * threads; + maxcpus =3D maxcpus > 0 ? maxcpus : sockets * cores * threads * others; cpus =3D cpus > 0 ? cpus : maxcpus; =20 ms->smp.cpus =3D cpus; @@ -157,7 +160,7 @@ void smp_parse(MachineState *ms, SMPConfiguration *conf= ig, Error **errp) ms->smp.max_cpus =3D maxcpus; =20 /* sanity-check of the computed topology */ - if (sockets * dies * clusters * cores * threads !=3D maxcpus) { + if (sockets * cores * threads * others !=3D maxcpus) { g_autofree char *topo_msg =3D cpu_hierarchy_to_string(ms); error_setg(errp, "Invalid CPU topology: " "product of the hierarchy must match maxcpus: " --=20 2.19.1 From nobody Sat May 4 06:24:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1637497624; cv=none; d=zohomail.com; s=zohoarc; b=DJX53byfGjkgT/HC72NlVfeRmPF0F021mX3191a06RYM4/dQSgu9vazzuwaKPxxyav9t0Km8GCOyiKW8L1wxPIW0+PzIbJQd1Ll8EemlRpmHL1jK7GfVRSTYLkkX90s9IzFkMK8jCkZdqmWBNCk8oD0F1o65e/2z1AmKqhAl4IE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637497624; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=SMXPXZ45zVWEPT+ZpBq3G5bygsbDspUEDkqP0tV/JBM=; b=YKwBfQKZqZxCukwXi5HALc4U+ZPbBQrBOUCXxzCWtaB+r4pTqiWLxO1cBSb0xoe/Mfdt8eWTTTaZgpMICqX4LiN5PYLAV+/eQsNnnj3cws1qUofmJ1CIQAWm/V/lNkt8v9DV6X2pNIJqXHVy0RKG5tUoJmDQEOPaEgeEhST8OBk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637497624045829.2867682144888; Sun, 21 Nov 2021 04:27:04 -0800 (PST) Received: from localhost ([::1]:52310 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1molvy-0006nT-PH for importer@patchew.org; Sun, 21 Nov 2021 07:27:02 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52604) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1moluL-0003oi-0H; Sun, 21 Nov 2021 07:25:21 -0500 Received: from szxga01-in.huawei.com ([45.249.212.187]:2955) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1moluH-0005lu-Sh; Sun, 21 Nov 2021 07:25:20 -0500 Received: from dggpemm500023.china.huawei.com (unknown [172.30.72.54]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4HxqH12MTvzcZxK; Sun, 21 Nov 2021 20:20:13 +0800 (CST) Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Sun, 21 Nov 2021 20:25:10 +0800 To: , CC: Peter Maydell , Andrew Jones , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Paolo Bonzini , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Markus Armbruster , Eric Blake , , Yanan Wang Subject: [PATCH v4 04/10] hw/arm/virt: Support clusters on ARM virt machines Date: Sun, 21 Nov 2021 20:24:56 +0800 Message-ID: <20211121122502.9844-5-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20211121122502.9844-1-wangyanan55@huawei.com> References: <20211121122502.9844-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.187; envelope-from=wangyanan55@huawei.com; helo=szxga01-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Yanan Wang From: Yanan Wang via X-ZM-MESSAGEID: 1637497625930100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In implementations of ARM64 architecture, at most there could be a CPU topology hierarchy like "sockets/dies/clusters/cores/threads" defined. For example, some ARM64 server chip Kunpeng 920 totally has 2 sockets, 2 NUMA nodes (also represent CPU dies range) in each socket, 6 clusters in each NUMA node, 4 CPU cores in each cluster. Clusters within the same NUMA share the L3 cache data and cores within the same cluster share a L2 cache and a L3 cache tag. Given that designing a vCPU topology with cluster level for the guest can gain scheduling performance improvement, let's support this new parameter on ARM virt machines. After this, we can define a 4-level CPU topology hierarchy like: cpus=3D*,maxcpus=3D*,sockets=3D*,clusters=3D*,cores=3D*,threads=3D*. Signed-off-by: Yanan Wang --- hw/arm/virt.c | 1 + qemu-options.hx | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 369552ad45..b2129f7ccd 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2698,6 +2698,7 @@ static void virt_machine_class_init(ObjectClass *oc, = void *data) hc->unplug_request =3D virt_machine_device_unplug_request_cb; hc->unplug =3D virt_machine_device_unplug_cb; mc->nvdimm_supported =3D true; + mc->smp_props.clusters_supported =3D true; mc->auto_enable_numa_with_memhp =3D true; mc->auto_enable_numa_with_memdev =3D true; mc->default_ram_id =3D "mach-virt.ram"; diff --git a/qemu-options.hx b/qemu-options.hx index 0f26f7dad7..74d335e4c3 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -277,6 +277,16 @@ SRST =20 -smp 16,sockets=3D2,dies=3D2,cores=3D2,threads=3D2,maxcpus=3D16 =20 + The following sub-option defines a CPU topology hierarchy (2 sockets + totally on the machine, 2 clusters per socket, 2 cores per cluster, + 2 threads per core) for ARM virt machines which support sockets/cluste= rs + /cores/threads. Some members of the option can be omitted but their va= lues + will be automatically computed: + + :: + + -smp 16,sockets=3D2,clusters=3D2,cores=3D2,threads=3D2,maxcpus=3D16 + Historically preference was given to the coarsest topology parameters when computing missing values (ie sockets preferred over cores, which were preferred over threads), however, this behaviour is considered --=20 2.19.1 From nobody Sat May 4 06:24:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1637497624; cv=none; d=zohomail.com; s=zohoarc; b=bfi93dLb+h/0cxpFrF+HwNtlHQytxUYHfRMEzkHgdJyEqQSHX5ln7iEiWK2dz05H6zHDJZcUxSzlf2Va0x0ZkJi1F8sdyeeTVAHeP3yuaSQtIGrTu1+qZtjcDNIbAuk+80eYKZjyEET4XQL7I4JPES/PT+kJ9OFoaGlP3vEteRk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637497624; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=2lHXGVLZK0fpdq9PpyGSc7kt3E/lIvxZxVFLRBF4quE=; b=lzTot+Wiq14dJo++73ENOm8/faIlzoluFA3sbdXC5j7HeryxeoVxbuiUlX3tgpKPGQQgbRySoR2JgEIUxGtXrwn4UVN5z3bWAjWc0vkgOtC+MXyxz2fz9sJzgpBbS4ocAD2i4DMn6LH4FjfBFqI4VuTIdbAGQ7CNr7eBzBr3ObE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637497624140364.6590364013199; Sun, 21 Nov 2021 04:27:04 -0800 (PST) Received: from localhost ([::1]:52182 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1molvy-0006iY-5w for importer@patchew.org; Sun, 21 Nov 2021 07:27:02 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52654) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1moluM-0003p7-Ie; Sun, 21 Nov 2021 07:25:22 -0500 Received: from szxga01-in.huawei.com ([45.249.212.187]:3502) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1moluI-0005mA-IB; Sun, 21 Nov 2021 07:25:22 -0500 Received: from dggpemm500023.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4HxqKw2C25zZd0b; Sun, 21 Nov 2021 20:22:44 +0800 (CST) Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Sun, 21 Nov 2021 20:25:12 +0800 To: , CC: Peter Maydell , Andrew Jones , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Paolo Bonzini , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Markus Armbruster , Eric Blake , , Yanan Wang Subject: [PATCH v4 05/10] hw/arm/virt: Support cluster level in DT cpu-map Date: Sun, 21 Nov 2021 20:24:57 +0800 Message-ID: <20211121122502.9844-6-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20211121122502.9844-1-wangyanan55@huawei.com> References: <20211121122502.9844-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.187; envelope-from=wangyanan55@huawei.com; helo=szxga01-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Yanan Wang From: Yanan Wang via X-ZM-MESSAGEID: 1637497625997100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support one cluster level between core and physical package in the cpu-map of Arm/virt devicetree. This is also consistent with Linux Doc "Documentation/devicetree/bindings/cpu/cpu-topology.txt". Signed-off-by: Yanan Wang --- hw/arm/virt.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b2129f7ccd..dfdc64c4e3 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -430,9 +430,8 @@ static void fdt_add_cpu_nodes(const VirtMachineState *v= ms) * can contain several layers of clustering within a single physic= al * package and cluster nodes can be contained in parent cluster no= des. * - * Given that cluster is not yet supported in the vCPU topology, - * we currently generate one cluster node within each socket node - * by default. + * Note: currently we only support one layer of clustering within + * each physical package. */ qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); =20 @@ -442,14 +441,16 @@ static void fdt_add_cpu_nodes(const VirtMachineState = *vms) =20 if (ms->smp.threads > 1) { map_path =3D g_strdup_printf( - "/cpus/cpu-map/socket%d/cluster0/core%d/thread%d", - cpu / (ms->smp.cores * ms->smp.threads), + "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", + cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.thre= ads), + (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.cl= usters, (cpu / ms->smp.threads) % ms->smp.cores, cpu % ms->smp.threads); } else { map_path =3D g_strdup_printf( - "/cpus/cpu-map/socket%d/cluster0/core%d", - cpu / ms->smp.cores, + "/cpus/cpu-map/socket%d/cluster%d/core%d", + cpu / (ms->smp.clusters * ms->smp.cores), + (cpu / ms->smp.cores) % ms->smp.clusters, cpu % ms->smp.cores); } qemu_fdt_add_path(ms->fdt, map_path); --=20 2.19.1 From nobody Sat May 4 06:24:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1637498079; cv=none; d=zohomail.com; s=zohoarc; b=BCVEmlnNtikYkM1yCzWNc8cUu2KLVyRHYmLUr4eHFuw77WNKefAf5jZ1s+bjkxDH3fnfCuYgVYwg1T3L4BMoeijZsQxDotJFlLZmHwfF6K23hB21ZwlNpT7rkpT/G0rWb77nX433eYoArNRR13IyZDiTg5hhP+FuEIw12yR9964= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637498079; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=FwkhvndTg31owIAVU/F5C5UCe7VnKP2xCeCj2IjpJbk=; b=e4a4pFmtIE8Djq1caeLq7Arzl5ysn0humjtTcvFQxlOyDZuxuvtsEkAwAWcOjKeI9cfk4OinosQ0hz1/laiZK/I9ZoRAre9O6a2dN0EYO1z0F3a3CWHbkZSz77sCLim3CPYqd/7gXpPJLuVpj5kjEfr6yvz8lB+Kj7br+SXvrDA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637498079464841.165599239799; Sun, 21 Nov 2021 04:34:39 -0800 (PST) Received: from localhost ([::1]:46178 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mom3K-0004xD-GG for importer@patchew.org; Sun, 21 Nov 2021 07:34:38 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52722) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1moluO-0003r3-Gt; Sun, 21 Nov 2021 07:25:24 -0500 Received: from szxga01-in.huawei.com ([45.249.212.187]:3503) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1moluJ-0005mN-57; Sun, 21 Nov 2021 07:25:24 -0500 Received: from dggpemm500023.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4HxqKx3pWyzZd1j; Sun, 21 Nov 2021 20:22:45 +0800 (CST) Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Sun, 21 Nov 2021 20:25:13 +0800 To: , CC: Peter Maydell , Andrew Jones , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Paolo Bonzini , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Markus Armbruster , Eric Blake , , Yanan Wang Subject: [PATCH v4 06/10] hw/acpi/aml-build: Improve scalability of PPTT generation Date: Sun, 21 Nov 2021 20:24:58 +0800 Message-ID: <20211121122502.9844-7-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20211121122502.9844-1-wangyanan55@huawei.com> References: <20211121122502.9844-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.187; envelope-from=wangyanan55@huawei.com; helo=szxga01-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Yanan Wang From: Yanan Wang via X-ZM-MESSAGEID: 1637498079952100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently we generate a PPTT table of n-level processor hierarchy with n-level loops in build_pptt(). It works fine as now there are only three CPU topology parameters. But the code may become less scalable with the processor hierarchy levels increasing. This patch only improves the scalability of build_pptt by reducing the loops, and intends to make no functional change. Signed-off-by: Yanan Wang --- hw/acpi/aml-build.c | 50 +++++++++++++++++++++++++++++---------------- 1 file changed, 32 insertions(+), 18 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index b3b3310df3..be3851be36 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -2001,7 +2001,10 @@ static void build_processor_hierarchy_node(GArray *t= bl, uint32_t flags, void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, const char *oem_id, const char *oem_table_id) { - int pptt_start =3D table_data->len; + GQueue *list =3D g_queue_new(); + guint pptt_start =3D table_data->len; + guint father_offset; + guint length, i; int uid =3D 0; int socket; AcpiTable table =3D { .sig =3D "PPTT", .rev =3D 2, @@ -2010,9 +2013,8 @@ void build_pptt(GArray *table_data, BIOSLinker *linke= r, MachineState *ms, acpi_table_begin(&table, table_data); =20 for (socket =3D 0; socket < ms->smp.sockets; socket++) { - uint32_t socket_offset =3D table_data->len - pptt_start; - int core; - + g_queue_push_tail(list, + GUINT_TO_POINTER(table_data->len - pptt_start)); build_processor_hierarchy_node( table_data, /* @@ -2021,35 +2023,47 @@ void build_pptt(GArray *table_data, BIOSLinker *lin= ker, MachineState *ms, */ (1 << 0), 0, socket, NULL, 0); + } =20 - for (core =3D 0; core < ms->smp.cores; core++) { - uint32_t core_offset =3D table_data->len - pptt_start; - int thread; + length =3D g_queue_get_length(list); + for (i =3D 0; i < length; i++) { + int core; =20 + father_offset =3D GPOINTER_TO_UINT(g_queue_pop_head(list)); + for (core =3D 0; core < ms->smp.cores; core++) { if (ms->smp.threads > 1) { + g_queue_push_tail(list, + GUINT_TO_POINTER(table_data->len - pptt_start)); build_processor_hierarchy_node( table_data, (0 << 0), /* not a physical package */ - socket_offset, core, NULL, 0); - - for (thread =3D 0; thread < ms->smp.threads; thread++) { - build_processor_hierarchy_node( - table_data, - (1 << 1) | /* ACPI Processor ID valid */ - (1 << 2) | /* Processor is a Thread */ - (1 << 3), /* Node is a Leaf */ - core_offset, uid++, NULL, 0); - } + father_offset, core, NULL, 0); } else { build_processor_hierarchy_node( table_data, (1 << 1) | /* ACPI Processor ID valid */ (1 << 3), /* Node is a Leaf */ - socket_offset, uid++, NULL, 0); + father_offset, uid++, NULL, 0); } } } =20 + length =3D g_queue_get_length(list); + for (i =3D 0; i < length; i++) { + int thread; + + father_offset =3D GPOINTER_TO_UINT(g_queue_pop_head(list)); + for (thread =3D 0; thread < ms->smp.threads; thread++) { + build_processor_hierarchy_node( + table_data, + (1 << 1) | /* ACPI Processor ID valid */ + (1 << 2) | /* Processor is a Thread */ + (1 << 3), /* Node is a Leaf */ + father_offset, uid++, NULL, 0); + } + } + + g_queue_free(list); acpi_table_end(linker, &table); } =20 --=20 2.19.1 From nobody Sat May 4 06:24:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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Sun, 21 Nov 2021 20:25:14 +0800 To: , CC: Peter Maydell , Andrew Jones , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Paolo Bonzini , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Markus Armbruster , Eric Blake , , Yanan Wang Subject: [PATCH v4 07/10] hw/arm/virt-acpi-build: Make an ARM specific PPTT generator Date: Sun, 21 Nov 2021 20:24:59 +0800 Message-ID: <20211121122502.9844-8-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20211121122502.9844-1-wangyanan55@huawei.com> References: <20211121122502.9844-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.188; envelope-from=wangyanan55@huawei.com; helo=szxga02-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Yanan Wang From: Yanan Wang via X-ZM-MESSAGEID: 1637497984473100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We have a generic build_pptt() in hw/acpi/aml-build.c but it's currently only used in ARM acpi initialization. Now we are going to support the new CPU cluster parameter which is currently only supported by ARM, it won't be a very good idea to add it to the generic build_pptt() as it will make the code complex and hard to maintain especially when we also support CPU cache topology hierarchy in build_pptt() too. Note that the cache topology design also varies between different CPU targets. So an ARM specific PPTT generator becomes necessary now. Given that the generic one is currently only used by ARM, let's just move build_pptt() from aml-build.c to virt-acpi-build.c with minor update. Signed-off-by: Yanan Wang --- hw/acpi/aml-build.c | 80 ++----------------------------------- hw/arm/virt-acpi-build.c | 77 ++++++++++++++++++++++++++++++++++- include/hw/acpi/aml-build.h | 5 ++- 3 files changed, 81 insertions(+), 81 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index be3851be36..040fbc9b4b 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1968,10 +1968,9 @@ void build_slit(GArray *table_data, BIOSLinker *link= er, MachineState *ms, * ACPI spec, Revision 6.3 * 5.2.29.1 Processor hierarchy node structure (Type 0) */ -static void build_processor_hierarchy_node(GArray *tbl, uint32_t flags, - uint32_t parent, uint32_t id, - uint32_t *priv_rsrc, - uint32_t priv_num) +void build_processor_hierarchy_node(GArray *tbl, uint32_t flags, + uint32_t parent, uint32_t id, + uint32_t *priv_rsrc, uint32_t priv_num) { int i; =20 @@ -1994,79 +1993,6 @@ static void build_processor_hierarchy_node(GArray *t= bl, uint32_t flags, } } =20 -/* - * ACPI spec, Revision 6.3 - * 5.2.29 Processor Properties Topology Table (PPTT) - */ -void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, - const char *oem_id, const char *oem_table_id) -{ - GQueue *list =3D g_queue_new(); - guint pptt_start =3D table_data->len; - guint father_offset; - guint length, i; - int uid =3D 0; - int socket; - AcpiTable table =3D { .sig =3D "PPTT", .rev =3D 2, - .oem_id =3D oem_id, .oem_table_id =3D oem_table_id= }; - - acpi_table_begin(&table, table_data); - - for (socket =3D 0; socket < ms->smp.sockets; socket++) { - g_queue_push_tail(list, - GUINT_TO_POINTER(table_data->len - pptt_start)); - build_processor_hierarchy_node( - table_data, - /* - * Physical package - represents the boundary - * of a physical package - */ - (1 << 0), - 0, socket, NULL, 0); - } - - length =3D g_queue_get_length(list); - for (i =3D 0; i < length; i++) { - int core; - - father_offset =3D GPOINTER_TO_UINT(g_queue_pop_head(list)); - for (core =3D 0; core < ms->smp.cores; core++) { - if (ms->smp.threads > 1) { - g_queue_push_tail(list, - GUINT_TO_POINTER(table_data->len - pptt_start)); - build_processor_hierarchy_node( - table_data, - (0 << 0), /* not a physical package */ - father_offset, core, NULL, 0); - } else { - build_processor_hierarchy_node( - table_data, - (1 << 1) | /* ACPI Processor ID valid */ - (1 << 3), /* Node is a Leaf */ - father_offset, uid++, NULL, 0); - } - } - } - - length =3D g_queue_get_length(list); - for (i =3D 0; i < length; i++) { - int thread; - - father_offset =3D GPOINTER_TO_UINT(g_queue_pop_head(list)); - for (thread =3D 0; thread < ms->smp.threads; thread++) { - build_processor_hierarchy_node( - table_data, - (1 << 1) | /* ACPI Processor ID valid */ - (1 << 2) | /* Processor is a Thread */ - (1 << 3), /* Node is a Leaf */ - father_offset, uid++, NULL, 0); - } - } - - g_queue_free(list); - acpi_table_end(linker, &table); -} - /* build rev1/rev3/rev5.1 FADT */ void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, const char *oem_id, const char *oem_table_id) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 674f902652..bef7056213 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -807,6 +807,80 @@ build_madt(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) acpi_table_end(linker, &table); } =20 +/* + * ACPI spec, Revision 6.3 + * 5.2.29 Processor Properties Topology Table (PPTT) + */ +static void +build_pptt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) +{ + MachineState *ms =3D MACHINE(vms); + GQueue *list =3D g_queue_new(); + guint pptt_start =3D table_data->len; + guint father_offset; + guint length, i; + int uid =3D 0; + int socket; + AcpiTable table =3D { .sig =3D "PPTT", .rev =3D 2, .oem_id =3D vms->oe= m_id, + .oem_table_id =3D vms->oem_table_id }; + + acpi_table_begin(&table, table_data); + + for (socket =3D 0; socket < ms->smp.sockets; socket++) { + g_queue_push_tail(list, + GUINT_TO_POINTER(table_data->len - pptt_start)); + build_processor_hierarchy_node( + table_data, + /* + * Physical package - represents the boundary + * of a physical package + */ + (1 << 0), + 0, socket, NULL, 0); + } + + length =3D g_queue_get_length(list); + for (i =3D 0; i < length; i++) { + int core; + + father_offset =3D GPOINTER_TO_UINT(g_queue_pop_head(list)); + for (core =3D 0; core < ms->smp.cores; core++) { + if (ms->smp.threads > 1) { + g_queue_push_tail(list, + GUINT_TO_POINTER(table_data->len - pptt_start)); + build_processor_hierarchy_node( + table_data, + (0 << 0), /* not a physical package */ + father_offset, core, NULL, 0); + } else { + build_processor_hierarchy_node( + table_data, + (1 << 1) | /* ACPI Processor ID valid */ + (1 << 3), /* Node is a Leaf */ + father_offset, uid++, NULL, 0); + } + } + } + + length =3D g_queue_get_length(list); + for (i =3D 0; i < length; i++) { + int thread; + + father_offset =3D GPOINTER_TO_UINT(g_queue_pop_head(list)); + for (thread =3D 0; thread < ms->smp.threads; thread++) { + build_processor_hierarchy_node( + table_data, + (1 << 1) | /* ACPI Processor ID valid */ + (1 << 2) | /* Processor is a Thread */ + (1 << 3), /* Node is a Leaf */ + father_offset, uid++, NULL, 0); + } + } + + g_queue_free(list); + acpi_table_end(linker, &table); +} + /* FADT */ static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms, unsigned dsdt_tbl_offse= t) @@ -952,8 +1026,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildT= ables *tables) =20 if (!vmc->no_cpu_topology) { acpi_add_table(table_offsets, tables_blob); - build_pptt(tables_blob, tables->linker, ms, - vms->oem_id, vms->oem_table_id); + build_pptt(tables_blob, tables->linker, vms); } =20 acpi_add_table(table_offsets, tables_blob); diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 8346003a22..2c457c8f17 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -489,8 +489,9 @@ void build_srat_memory(GArray *table_data, uint64_t bas= e, void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms, const char *oem_id, const char *oem_table_id); =20 -void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, - const char *oem_id, const char *oem_table_id); +void build_processor_hierarchy_node(GArray *tbl, uint32_t flags, + uint32_t parent, uint32_t id, + uint32_t *priv_rsrc, uint32_t priv_num= ); =20 void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, const char *oem_id, const char *oem_table_id); --=20 2.19.1 From nobody Sat May 4 06:24:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Igor Mammedov , Ani Sinha , Markus Armbruster , Eric Blake , , Yanan Wang Subject: [PATCH v4 08/10] tests/acpi/bios-tables-test: Allow changes to virt/PPTT file Date: Sun, 21 Nov 2021 20:25:00 +0800 Message-ID: <20211121122502.9844-9-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20211121122502.9844-1-wangyanan55@huawei.com> References: <20211121122502.9844-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.187; envelope-from=wangyanan55@huawei.com; helo=szxga01-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Yanan Wang From: Yanan Wang via X-ZM-MESSAGEID: 1637497925972100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" List test/data/acpi/virt/PPTT as the expected files allowed to be changed in tests/qtest/bios-tables-test-allowed-diff.h Signed-off-by: Yanan Wang --- tests/qtest/bios-tables-test-allowed-diff.h | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..cb143a55a6 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,2 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/PPTT", --=20 2.19.1 From nobody Sat May 4 06:24:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1637497657; cv=none; d=zohomail.com; s=zohoarc; b=bFseUCjviW9TzOq2MBHt8GxLY2M9N1ZaAOLR8zYCCN9wbFqkuuP9QeHzt8DUSdT8H523JnmzWGFPlNc9yj4sUvLpNH8+XS3u6QLUdrUcHV+rW69jdi8jtS76vQOgSVQuT+bSoet6VF86vfRlDjXIPwep05M8B17GYyboOddHcno= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637497657; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=FA34rbP7P7EG4LEtka3cDq4i57Rmlw6Xu8qcAO43OLs=; b=ZnmHFPJOqQF8sf7QMmcI6YCcVJyBSEsAHxnmQ7LZ5odXq1L9ggIdcEzqztabbk2zYhjvH6W5P1Tb7DqIlN1HDd9BSs4FCvhJy9zi5l/x0rGqhhwBJ5+YI2vWvgfiJ/F0LmlC/JEDec14ASZHJYL0mYoPixAdG91Q5AVilHSw/gc= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637497657854793.3383646939515; Sun, 21 Nov 2021 04:27:37 -0800 (PST) Received: from localhost ([::1]:55530 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1molwW-0000Yc-R5 for importer@patchew.org; Sun, 21 Nov 2021 07:27:36 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52724) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1moluO-0003r4-Gx; Sun, 21 Nov 2021 07:25:24 -0500 Received: from szxga08-in.huawei.com ([45.249.212.255]:2907) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1moluK-0005mx-DP; Sun, 21 Nov 2021 07:25:24 -0500 Received: from dggpemm500023.china.huawei.com (unknown [172.30.72.56]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4HxqL12X9Sz1DJC8; Sun, 21 Nov 2021 20:22:49 +0800 (CST) Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Sun, 21 Nov 2021 20:25:17 +0800 To: , CC: Peter Maydell , Andrew Jones , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Paolo Bonzini , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Markus Armbruster , Eric Blake , , Yanan Wang Subject: [PATCH v4 09/10] hw/acpi/virt-acpi-build: Support cluster level in PPTT generation Date: Sun, 21 Nov 2021 20:25:01 +0800 Message-ID: <20211121122502.9844-10-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20211121122502.9844-1-wangyanan55@huawei.com> References: <20211121122502.9844-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.255; envelope-from=wangyanan55@huawei.com; helo=szxga08-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Yanan Wang From: Yanan Wang via X-ZM-MESSAGEID: 1637497659507100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support cluster level in generation of ACPI Processor Properties Topology Table (PPTT) for ARM virt machines. Signed-off-by: Yanan Wang --- hw/arm/virt-acpi-build.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index bef7056213..b34f0dbee0 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -839,6 +839,21 @@ build_pptt(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) 0, socket, NULL, 0); } =20 + length =3D g_queue_get_length(list); + for (i =3D 0; i < length; i++) { + int cluster; + + father_offset =3D GPOINTER_TO_UINT(g_queue_pop_head(list)); + for (cluster =3D 0; cluster < ms->smp.clusters; cluster++) { + g_queue_push_tail(list, + GUINT_TO_POINTER(table_data->len - pptt_start)); + build_processor_hierarchy_node( + table_data, + (0 << 0), /* not a physical package */ + father_offset, cluster, NULL, 0); + } + } + length =3D g_queue_get_length(list); for (i =3D 0; i < length; i++) { int core; --=20 2.19.1 From nobody Sat May 4 06:24:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1637497835; cv=none; d=zohomail.com; s=zohoarc; b=b9lfGMMzrjX6Nj4vxTamLkMOA2mmIjTrAqaetwBd2tXNGpAuBlxQKRiHTStHMKZ1hNmm49ytn8SWkrvrFonSonM98X+Klr9oNC4PdQ9t38FCqWx00U6VEyZEy2p6QLN/7nmsjD+IDofyE3+IWSg09vF8oRGn6cEYSRfx4vuzvsM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637497835; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=BUfk/p8nHIEemgSv5Xr/OIDiNPCXPKe97h5PcdI06bg=; b=me8Yo+cC6uvlOjaQBrPlEy8jFozIk38oY3nyaqyvSB2ubpNhmxXI9c6tmAaYO7s5obSOhXYkivvaEoWQzsP5oxNOkmV5O/h2CEUoimtYfgYb52Xn9a1+8IrtFa5MTepuclcxQbahu8Y9wQTV5TEJkBM8WgrqkWn5XLWQmcrnsdE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163749783571638.51291046631502; Sun, 21 Nov 2021 04:30:35 -0800 (PST) Received: from localhost ([::1]:35766 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1molzO-0006JQ-L8 for importer@patchew.org; Sun, 21 Nov 2021 07:30:34 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52726) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1moluO-0003s0-Ov; Sun, 21 Nov 2021 07:25:24 -0500 Received: from szxga01-in.huawei.com ([45.249.212.187]:2957) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1moluL-0005nA-Hm; Sun, 21 Nov 2021 07:25:24 -0500 Received: from dggpemm500023.china.huawei.com (unknown [172.30.72.57]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4HxqH854l2zcb4K; Sun, 21 Nov 2021 20:20:20 +0800 (CST) Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Sun, 21 Nov 2021 20:25:18 +0800 To: , CC: Peter Maydell , Andrew Jones , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Paolo Bonzini , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Markus Armbruster , Eric Blake , , Yanan Wang Subject: [PATCH v4 10/10] tests/acpi/bios-table-test: Update expected virt/PPTT file Date: Sun, 21 Nov 2021 20:25:02 +0800 Message-ID: <20211121122502.9844-11-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20211121122502.9844-1-wangyanan55@huawei.com> References: <20211121122502.9844-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.187; envelope-from=wangyanan55@huawei.com; helo=szxga01-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Yanan Wang From: Yanan Wang via X-ZM-MESSAGEID: 1637497836836100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Run ./tests/data/acpi/rebuild-expected-aml.sh from build directory to update PPTT binary. Also empty bios-tables-test-allowed-diff.h. The disassembled differences between actual and expected PPTT: /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180810 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * - * Disassembly of tests/data/acpi/virt/PPTT, Mon Oct 25 20:24:53 2021 + * Disassembly of /tmp/aml-BPI5B1, Mon Oct 25 20:24:53 2021 * * ACPI Data Table [PPTT] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "PPTT" [Processor Proper= ties Topology Table] -[004h 0004 4] Table Length : 0000004C +[004h 0004 4] Table Length : 00000060 [008h 0008 1] Revision : 02 -[009h 0009 1] Checksum : A8 +[009h 0009 1] Checksum : 48 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 1] Subtable Type : 00 [Processor Hierarchy Nod= e] [025h 0037 1] Length : 14 [026h 0038 2] Reserved : 0000 [028h 0040 4] Flags (decoded below) : 00000001 Physical package : 1 ACPI Processor ID valid : 0 [02Ch 0044 4] Parent : 00000000 [030h 0048 4] ACPI Processor ID : 00000000 [034h 0052 4] Private Resource Number : 00000000 [038h 0056 1] Subtable Type : 00 [Processor Hierarchy Nod= e] [039h 0057 1] Length : 14 [03Ah 0058 2] Reserved : 0000 -[03Ch 0060 4] Flags (decoded below) : 0000000A +[03Ch 0060 4] Flags (decoded below) : 00000000 Physical package : 0 - ACPI Processor ID valid : 1 + ACPI Processor ID valid : 0 [040h 0064 4] Parent : 00000024 [044h 0068 4] ACPI Processor ID : 00000000 [048h 0072 4] Private Resource Number : 00000000 -Raw Table Data: Length 76 (0x4C) +[04Ch 0076 1] Subtable Type : 00 [Processor Hierarchy Nod= e] +[04Dh 0077 1] Length : 14 +[04Eh 0078 2] Reserved : 0000 +[050h 0080 4] Flags (decoded below) : 0000000A + Physical package : 0 + ACPI Processor ID valid : 1 +[054h 0084 4] Parent : 00000038 +[058h 0088 4] ACPI Processor ID : 00000000 +[05Ch 0092 4] Private Resource Number : 00000000 + +Raw Table Data: Length 96 (0x60) - 0000: 50 50 54 54 4C 00 00 00 02 A8 42 4F 43 48 53 20 // PPTTL.....BO= CHS + 0000: 50 50 54 54 60 00 00 00 02 48 42 4F 43 48 53 20 // PPTT`....HBO= CHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....= BXPC 0020: 01 00 00 00 00 14 00 00 01 00 00 00 00 00 00 00 // ............= .... - 0030: 00 00 00 00 00 00 00 00 00 14 00 00 0A 00 00 00 // ............= .... - 0040: 24 00 00 00 00 00 00 00 00 00 00 00 // $........... + 0030: 00 00 00 00 00 00 00 00 00 14 00 00 00 00 00 00 // ............= .... + 0040: 24 00 00 00 00 00 00 00 00 00 00 00 00 14 00 00 // $...........= .... + 0050: 0A 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 // ....8.......= .... Signed-off-by: Yanan Wang --- tests/data/acpi/virt/PPTT | Bin 76 -> 96 bytes tests/qtest/bios-tables-test-allowed-diff.h | 1 - 2 files changed, 1 deletion(-) diff --git a/tests/data/acpi/virt/PPTT b/tests/data/acpi/virt/PPTT index 7a1258ecf123555b24462c98ccbb76b4ac1d0c2b..f56ea63b369a604877374ad696c= 396e796ab1c83 100644 GIT binary patch delta 53 zcmV-50LuSNU