From nobody Mon Feb 9 23:58:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637394920803285.415274800015; Fri, 19 Nov 2021 23:55:20 -0800 (PST) Received: from localhost ([::1]:36102 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1moLDT-0002G4-MW for importer@patchew.org; Sat, 20 Nov 2021 02:55:19 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46464) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1moL5e-0004Iz-LA; Sat, 20 Nov 2021 02:47:14 -0500 Received: from szxga08-in.huawei.com ([45.249.212.255]:2903) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1moL5b-0006hK-Tf; Sat, 20 Nov 2021 02:47:14 -0500 Received: from dggemv711-chm.china.huawei.com (unknown [172.30.72.54]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4Hx5CY3Z9Pz1DJSV; Sat, 20 Nov 2021 15:44:41 +0800 (CST) Received: from kwepemm600017.china.huawei.com (7.193.23.234) by dggemv711-chm.china.huawei.com (10.1.198.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Sat, 20 Nov 2021 15:47:08 +0800 Received: from huawei.com (10.174.186.236) by kwepemm600017.china.huawei.com (7.193.23.234) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Sat, 20 Nov 2021 15:47:06 +0800 From: Yifei Jiang To: , Subject: [PATCH v1 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer Date: Sat, 20 Nov 2021 15:46:42 +0800 Message-ID: <20211120074644.729-11-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20211120074644.729-1-jiangyifei@huawei.com> References: <20211120074644.729-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.236] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemm600017.china.huawei.com (7.193.23.234) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.255; envelope-from=jiangyifei@huawei.com; helo=szxga08-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, Mingwang Li , kvm@vger.kernel.org, libvir-list@redhat.com, anup.patel@wdc.com, wanbo13@huawei.com, Yifei Jiang , Alistair.Francis@wdc.com, kvm-riscv@lists.infradead.org, wanghaibin.wang@huawei.com, palmer@dabbelt.com, fanliang@huawei.com, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637394921396100001 Content-Type: text/plain; charset="utf-8" Add kvm_riscv_get/put_regs_timer to synchronize virtual time context from KVM. To set register of RISCV_TIMER_REG(state) will occur a error from KVM on kvm_timer_state =3D=3D 0. It's better to adapt in KVM, but it doesn't ma= tter that adaping in QEMU. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li --- target/riscv/cpu.h | 6 ++++ target/riscv/kvm.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e7dba35acb..dea49e53f0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -259,6 +259,12 @@ struct CPURISCVState { =20 hwaddr kernel_addr; hwaddr fdt_addr; + + /* kvm timer */ + bool kvm_timer_dirty; + uint64_t kvm_timer_time; + uint64_t kvm_timer_compare; + uint64_t kvm_timer_state; }; =20 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 6d419ba02e..e5725770f2 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -64,6 +64,9 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint= 64_t type, uint64_t idx #define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR,= \ KVM_REG_RISCV_CSR_REG(name)) =20 +#define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TI= MER, \ + KVM_REG_RISCV_TIMER_REG(name)) + #define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F= , idx) =20 #define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D= , idx) @@ -310,6 +313,75 @@ static int kvm_riscv_put_regs_fp(CPUState *cs) return ret; } =20 +static void kvm_riscv_get_regs_timer(CPUState *cs) +{ + int ret; + uint64_t reg; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + if (env->kvm_timer_dirty) { + return; + } + + ret =3D kvm_get_one_reg(cs, RISCV_TIMER_REG(env, time), ®); + if (ret) { + abort(); + } + env->kvm_timer_time =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_TIMER_REG(env, compare), ®); + if (ret) { + abort(); + } + env->kvm_timer_compare =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_TIMER_REG(env, state), ®); + if (ret) { + abort(); + } + env->kvm_timer_state =3D reg; + + env->kvm_timer_dirty =3D true; +} + +static void kvm_riscv_put_regs_timer(CPUState *cs) +{ + int ret; + uint64_t reg; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + if (!env->kvm_timer_dirty) { + return; + } + + reg =3D env->kvm_timer_time; + ret =3D kvm_set_one_reg(cs, RISCV_TIMER_REG(env, time), ®); + if (ret) { + abort(); + } + + reg =3D env->kvm_timer_compare; + ret =3D kvm_set_one_reg(cs, RISCV_TIMER_REG(env, compare), ®); + if (ret) { + abort(); + } + + /* + * To set register of RISCV_TIMER_REG(state) will occur a error from K= VM + * on env->kvm_timer_state =3D=3D 0, It's better to adapt in KVM, but = it + * doesn't matter that adaping in QEMU now. + * TODO If KVM changes, adapt here. + */ + if (env->kvm_timer_state) { + reg =3D env->kvm_timer_state; + ret =3D kvm_set_one_reg(cs, RISCV_TIMER_REG(env, state), ®); + if (ret) { + abort(); + } + } + + env->kvm_timer_dirty =3D false; +} =20 const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_LAST_INFO --=20 2.19.1