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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id s13sm13170110wmc.47.2021.11.19.09.12.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 09:12:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Mt9b+5cqbBIgzp6O9dytn7/9Xl0Ujk3opErV/gQqZLs=; b=QvKRb7k4cg3krRjLg5rfJHieJhIouk97Bd0HMqBWG8+AMfSynuHdKM3kCu3V4RvII8 32ZhWMtegJj4z1G6m5LCQUWGyxlXmjwC22I1h1nliHT8AFWl3fQqgHPUOoNjEOM+8YM9 nnqWSfgzRRj3wd/Dig5cJRJHQYexuI8QzNp+IIiq2zkl2wi2fWDkyE7nmU6KeMYf0fcJ ZpobR4u4Cxh2Q4pgGQpJt7nCDncUNQG01vTtEPyvh7ipEB5ve7lV5JpWy4qSkl1sXVMR AOX0v/AG6KXFK7bJGvSF6XTbfTI5b/htEprJ5+9ogx3VWwlsQRiDceO7VtkO4S3snZXB QsEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Mt9b+5cqbBIgzp6O9dytn7/9Xl0Ujk3opErV/gQqZLs=; b=HOPd8+mgFHJ/vHVaXp0bjnu24AB+Zi1Jdt1epZHYgdNEx8Ok9BA732D0DiM80g1wNR 4cM1EmfQjXZT5PTpq3NfHj7gF2+PzcSWTI0MbgjpeM2aiU++lCiUZQHtdDRqnEaSqweL 3+wPg6pGfD+Sc7HL+ErWOXeFPc7ohMjqxP0ST5YGjGm9PWs5C72fWuk4tB9ueWktCPcO hclPz2OgPE9kkcMKgIHiH50XJGzjHCCz0Ky8kPixVQSwmxNNLGwgrzPS4RntnskXuOrC qFGCXvMLvkm2/ZR4WE1RIRQKOj5w7gDcEuPbpE7ZpxiTzbl/RMy9x1iR3neHTExIDVhJ Kh7w== X-Gm-Message-State: AOAM530rYXWuEb91J66szn2snRjtOGTtQb8ClpPjI9af7xVekrvUFm2k AMDHnszgLuOZo+ZCDqhMf6o= X-Google-Smtp-Source: ABdhPJxSYvg82L4HMFpad2FMKqLnfaD1/mG9Bv+O7ymoAbs19NX9KZtZx4qRWoUrDcEcNrpe5rX3DA== X-Received: by 2002:a1c:6a13:: with SMTP id f19mr1430453wmc.89.1637341939121; Fri, 19 Nov 2021 09:12:19 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth Subject: [PATCH-for-7.0 3/5] hw/display/vga-mmio: QOM'ify vga_mmio_init() as TYPE_VGA_MMIO Date: Fri, 19 Nov 2021 18:12:00 +0100 Message-Id: <20211119171202.458919-4-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211119171202.458919-1-f4bug@amsat.org> References: <20211119171202.458919-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1637341943214100001 Introduce TYPE_VGA_MMIO, a sysbus device. While there is no change in the vga_mmio_init() interface, this is a migration compatibility break of the MIPS Acer Pica 61 Jazz machine (pica61). Suggested-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: BALATON Zoltan --- hw/display/vga-mmio.c | 134 +++++++++++++++++++++++++++++------------- 1 file changed, 94 insertions(+), 40 deletions(-) diff --git a/hw/display/vga-mmio.c b/hw/display/vga-mmio.c index 0aefbcf53a0..d1c5f31c134 100644 --- a/hw/display/vga-mmio.c +++ b/hw/display/vga-mmio.c @@ -2,6 +2,7 @@ * QEMU MMIO VGA Emulator. * * Copyright (c) 2003 Fabrice Bellard + * Copyright (c) 2021 Philippe Mathieu-Daud=C3=A9 * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal @@ -23,21 +24,34 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/bitops.h" -#include "qemu/units.h" -#include "migration/vmstate.h" +#include "qapi/error.h" #include "hw/display/vga.h" +#include "hw/sysbus.h" +#include "hw/qdev-properties.h" #include "vga_int.h" -#include "ui/pixel_ops.h" =20 -#define VGA_RAM_SIZE (8 * MiB) +/* + * QEMU interface: + * + sysbus MMIO region 0: VGA I/O registers + * + sysbus MMIO region 1: VGA MMIO registers + * + sysbus MMIO region 2: VGA memory + */ =20 -typedef struct VGAMmioState { +#define TYPE_VGA_MMIO "vga-mmio" +OBJECT_DECLARE_SIMPLE_TYPE(VGAMmioState, VGA_MMIO) + +struct VGAMmioState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ VGACommonState vga; - int it_shift; -} VGAMmioState; + MemoryRegion iomem; + MemoryRegion lowmem; + + uint8_t it_shift; +}; =20 -/* Memory mapped interface */ static uint64_t vga_mm_read(void *opaque, hwaddr addr, unsigned size) { VGAMmioState *s =3D opaque; @@ -65,43 +79,83 @@ static const MemoryRegionOps vga_mm_ctrl_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 +static void vga_mmio_reset(DeviceState *dev) +{ + VGAMmioState *d =3D VGA_MMIO(dev); + VGACommonState *s =3D &d->vga; + + vga_common_reset(s); +} + int vga_mmio_init(hwaddr vram_base, hwaddr ctrl_base, int it_shift, MemoryRegion *address_space) { - VGAMmioState *s; - MemoryRegion *s_ioport_ctrl, *vga_io_memory; + DeviceState *dev; + SysBusDevice *s; =20 - s =3D g_malloc0(sizeof(*s)); + dev =3D qdev_new(TYPE_VGA_MMIO); + qdev_prop_set_uint8(dev, "it_shift", it_shift); + s =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(s, &error_fatal); =20 - s->vga.vram_size_mb =3D VGA_RAM_SIZE / MiB; - s->vga.global_vmstate =3D true; - vga_common_init(&s->vga, NULL); - - s->it_shift =3D it_shift; - s_ioport_ctrl =3D g_malloc(sizeof(*s_ioport_ctrl)); - memory_region_init_io(s_ioport_ctrl, NULL, &vga_mm_ctrl_ops, s, - "vga-mm-ctrl", 0x100000); - memory_region_set_flush_coalesced(s_ioport_ctrl); - - vga_io_memory =3D g_malloc(sizeof(*vga_io_memory)); - /* XXX: endianness? */ - memory_region_init_io(vga_io_memory, NULL, &vga_mem_ops, &s->vga, - "vga-mem", 0x20000); - - vmstate_register(NULL, 0, &vmstate_vga_common, s); - - memory_region_add_subregion(address_space, ctrl_base, s_ioport_ctrl); - s->vga.bank_offset =3D 0; - memory_region_add_subregion(address_space, - vram_base + 0x000a0000, vga_io_memory); - memory_region_set_coalescing(vga_io_memory); - - s->vga.con =3D graphic_console_init(NULL, 0, s->vga.hw_ops, s); - - memory_region_add_subregion(address_space, - VBE_DISPI_LFB_PHYSICAL_ADDRESS, - &s->vga.vram); + sysbus_mmio_map(s, 0, ctrl_base); + sysbus_mmio_map(s, 1, vram_base + 0x000a0000); + sysbus_mmio_map(s, 2, VBE_DISPI_LFB_PHYSICAL_ADDRESS); =20 return 0; } + +static void vga_mmio_realizefn(DeviceState *dev, Error **errp) +{ + VGAMmioState *s =3D VGA_MMIO(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + memory_region_init_io(&s->iomem, OBJECT(dev), &vga_mm_ctrl_ops, s, + "vga-mmio", 0x100000); + memory_region_set_flush_coalesced(&s->iomem); + sysbus_init_mmio(sbd, &s->iomem); + + /* XXX: endianness? */ + memory_region_init_io(&s->lowmem, OBJECT(dev), &vga_mem_ops, &s->vga, + "vga-lowmem", 0x20000); + memory_region_set_coalescing(&s->lowmem); + sysbus_init_mmio(sbd, &s->lowmem); + + s->vga.bank_offset =3D 0; + s->vga.global_vmstate =3D true; + vga_common_init(&s->vga, OBJECT(dev)); + sysbus_init_mmio(sbd, &s->vga.vram); + s->vga.con =3D graphic_console_init(dev, 0, s->vga.hw_ops, &s->vga); +} + +static Property vga_mmio_properties[] =3D { + DEFINE_PROP_UINT8("it_shift", VGAMmioState, it_shift, 0), + DEFINE_PROP_UINT32("vgamem_mb", VGAMmioState, vga.vram_size_mb, 8), + DEFINE_PROP_END_OF_LIST(), +}; + +static void vga_mmio_class_initfn(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D vga_mmio_realizefn; + dc->reset =3D vga_mmio_reset; + dc->vmsd =3D &vmstate_vga_common; + device_class_set_props(dc, vga_mmio_properties); + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); +} + +static const TypeInfo vga_mmio_info =3D { + .name =3D TYPE_VGA_MMIO, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(VGAMmioState), + .class_init =3D vga_mmio_class_initfn, +}; + +static void vga_mmio_register_types(void) +{ + type_register_static(&vga_mmio_info); +} + +type_init(vga_mmio_register_types) --=20 2.31.1