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charset="utf-8" The MPC7450 Family has a software TLB search feature that defines three interrupts at 0x1000, 0x1100 and 0x1200. These are not currently implemented in openbios. Due to an outstanding bug in QEMU[1], the feature is always enabled when emulating the 7450, requiring any software that runs in those cpus to implement the interrupt handlers. Fortunately, the 7450 User Manual provides sample code[2] for the TLB miss handlers so adding support for the feature in openbios is somewhat easy. This patch implements the software TLB search so that we can get the MPC7450 working again on the emulator. 1- https://gitlab.com/qemu-project/qemu/-/issues/86 2- https://www.nxp.com/docs/en/reference-manual/MPC7450UM.pdf (5.5.5.2.2 - Code for Example Exception Handlers) Signed-off-by: Fabiano Rosas --- arch/ppc/qemu/start.S | 236 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 233 insertions(+), 3 deletions(-) diff --git a/arch/ppc/qemu/start.S b/arch/ppc/qemu/start.S index c679230..a09a210 100644 --- a/arch/ppc/qemu/start.S +++ b/arch/ppc/qemu/start.S @@ -25,6 +25,10 @@ #define ILLEGAL_VECTOR( v ) .org __vectors + v ; vector__##v: bl trap_erro= r ; #define VECTOR( v, dummystr ) .org __vectors + v ; vector__##v =20 +#define SPR_TLBMISS 980 +#define SPR_PTEHI 981 +#define SPR_PTELO 982 + #ifdef CONFIG_PPC_64BITSUPPORT =20 /* We're trying to use the same code for the ppc32 and ppc64 handlers here. @@ -164,6 +168,76 @@ EXCEPTION_EPILOGUE_TEMPLATE .endm =20 +.macro ITLB_SEARCH + TLB_SEARCH +.endm + +.macro DTLB_SEARCH + TLB_SEARCH 1 +.endm + +.macro TLB_SEARCH data + mfspr r0,SPR_TLBMISS /* EA of access that missed */ + rlwinm r0,r0,20,16,31 /* mask out lower 16 bits of EA */ + mfspr r1,SPR_PTEHI /* PTEHI[1:24] has the VSID */ + rlwinm r1,r1,25,8,31 /* mask out upper 23 bits of VSID */ + + xor r1,r0,r1 /* primary hash */ + mfsdr1 r3 + rlwinm r0,r3,10,13,31 /* align HTMEXT and HTABMASK fields */ + ori r0,r0,0x3ff /* mask out HTMEXT and HTABMASK */ + and r1,r0,r1 + rlwinm r0,r3,26,13,21 + or r1,r0,r1 + +/* 32-bit PTEG address generation into r2 */ + andis. r2,r3,0xfe00 + rlwimi r2,r1,6,7,25 + + xor r1,r1,r1 + addi r1,r1,8 + mfspr r3,SPR_PTEHI + addi r2,r2,-8 + +1: + mtctr r1 +2: + lwzu r1,8(r2) /* get next pte */ + cmp 0,r1,r3 + bdnzf eq,2b + beq 1f /* found */ + + andi. r1,r3,0x0040 /* see if we have done second hash */ +.ifnb data + bne do_dsi +.else + bne do_isi +.endif + mfspr r0,SPR_TLBMISS /* EA of access that missed */ + rlwinm r0,r0,20,16,3 /* mask out lower 16 bits of EA */ + mfspr r1,SPR_PTEHI /* PTEHI[1:24] has the VSID */ + rlwinm r1,r1,25,8,31 /* mask out uppder 23 bits of VSID */ + + xor r1,r0,r1 /* primary hash */ + mfsdr1 r3 + rlwinm r0,r3,10,13,31 /* align HTMEXT and HTABMASK fields */ + ori r0,r0,0x3ff /* mask out HTMEXT and HTABMASK */ + and r1,r0,r1 + rlwinm r0,r3,26,13,21 + or r1,r0,r1 + +/* 32-bit PTEG address generation into r2 */ + andis. r2,r3,0xfe00 + rlwimi r2,r1,6,7,25 + + ori r3,r3,0x0040 + addi r1,r0,8 + addi r2,r2,-8 + b 1b + +1: +.endm + #undef ULONG_SIZE #undef stl #undef ll @@ -329,9 +403,16 @@ ILLEGAL_VECTOR( 0xd00 ) ILLEGAL_VECTOR( 0xe00 ) ILLEGAL_VECTOR( 0xf00 ) ILLEGAL_VECTOR( 0xf20 ) -ILLEGAL_VECTOR( 0x1000 ) -ILLEGAL_VECTOR( 0x1100 ) -ILLEGAL_VECTOR( 0x1200 ) + +VECTOR( 0x1000, "IFTLB" ): + b insn_tlb_miss + +VECTOR( 0x1100, "DLTLB" ): + b data_load_tlb_miss + +VECTOR( 0x1200, "DSTLB" ): + b data_store_tlb_miss + ILLEGAL_VECTOR( 0x1300 ) ILLEGAL_VECTOR( 0x1400 ) ILLEGAL_VECTOR( 0x1500 ) @@ -373,6 +454,155 @@ real_isi: exception_return: EXCEPTION_EPILOGUE =20 +/* + * Instruction TLB miss + * Entry: + * srr0 -> address of instruction that missed + * srr1 -> 16:31 =3D saved MSR + * TLBMISS -> ea that missed + * PTEHI -> upper 32-bits of pte value + * PTELO -> lower 32-bits of pte value + */ +insn_tlb_miss: + EXCEPTION_PREAMBLE + mtsprg3 r1 /* save ABI frame, we might call into C later */ + + ITLB_SEARCH + +/* pte found*/ + lwz r1,4(r2) /* load tlb entry lower-word */ + andi. r3,r1,8 /* check G-bit */ + bne isi_prot /* if guarded, take an ISI */ + + ori r1,r1,0x100 /* set reference bit */ + mtspr SPR_PTELO,r1 /* put rpn into PTELO */ + mfspr r0,SPR_TLBMISS + tlbli r0 /* load the itlb */ + srwi r1,r1,8 /* get byte 7 of pte */ + stb r1,6(r2) /* update page table */ + + mfsprg3 r1 /* restore C ABI stack */ + b exception_return + +/* Guarded memory protection violation: synthesize an ISI exception */ +isi_prot: + mfsrr1 r3 + andi. r2,r3,0xffff /* clean upper SRR1 */ + addis r2,r2,0x0800 /* protection violation flag */ + b 1f + +do_isi: + mfsrr1 r3 + andi. r2,r3,0xffff + addis r2,r2,0x4000 /* pte not found flag */ + mtsrr1 r2 + mtcrf 0x80,r3 +1: + mfsprg3 r1 /* restore C ABI stack */ + LOAD_REG_FUNC(r3, isi_exception) + mtctr r3 + bctrl + b exception_return + +/* + * Data Load TLB miss + * Entry: + * srr0 -> address of instruction that caused data tlb miss + * srr1 -> 16:31 =3D saved MSR + * TLBMISS -> ea that missed + * PTEHI -> upper 32-bits of pte value + * PTELO -> lower 32-bits of pte value + */ +data_load_tlb_miss: + EXCEPTION_PREAMBLE + mtsprg3 r1 /* save ABI frame, we might call into C later */ + + DTLB_SEARCH + +/* pte found */ + lwz r1,4(r2) /* load tlb entry lower-word */ + ori r1,r1,0x100 /* set reference bit */ + mtspr SPR_PTELO,r1 /* put RPN into PTELO */ + mfspr r0,SPR_TLBMISS + tlbld r0 /* load the dtlb */ + srwi r1,r1,8 /* get byte 7 of pte */ + stb r1,6(r2) /* update page table */ + + mfsprg3 r1 /* restore C ABI stack */ + b exception_return + +/* + * Data Store TLB miss + * Entry: + * srr0 -> address of instruction that caused data tlb miss + * srr1 -> 16:31 =3D saved MSR + * TLBMISS -> ea that missed + * PTEHI -> upper 32-bits of pte value + * PTELO -> lower 32-bits of pte value + */ +data_store_tlb_miss: + EXCEPTION_PREAMBLE + mtsprg3 r1 /* save ABI frame, we might call into C later */ + + DTLB_SEARCH + +/* pte found */ + lwz r1,4(r2) /* load tlb entry lower-word */ + andi. r3,r1,0x80 /* check the C-bit */ + beq data_store_prot_check /* if (C=3D=3D0) go check protection modes */ +3: + ori r1,r1,0x180 /* set reference and change bit */ + mtspr SPR_PTELO,r1 /* put RPN into PTELO */ + mfspr r0,SPR_TLBMISS + xori r0,r0,0x01 /* toggle LRU bit */ + tlbld r0 /* load the dtlb */ + sth r1,6(r2) /* update page table */ + + mfsprg3 r1 /* restore C ABI stack */ + b exception_return + +data_store_prot_check: + rlwinm. r3,r1,30,0,1 /* test PP */ + bge- 1f /* if (PP=3D=3D00 or PP=3D=3D01) go check KEY bit */ + andi. r3,r1,1 /* test PP[0] */ + beq+ 3b /* return if PP[0]=3D=3D0 */ + b dsi_prot +1: + mfsrr1 r3 + andis. r3,r3,0x0008 /* test the KEY bit (SRR1-bit 12) */ + ble 3b + +dsi_prot: + mfsrr1 r3 + rlwinm r1,r3,9,6,6 /* copy load/store bit over */ + addis r1,r1,0x0800 /* protection violation flag */ + b 2f + +do_dsi: + mfsrr1 r3 + rlwinm r1,r3,9,6,6 /* copy load/store bit over */ + addis r1,r1,0x4000 /* pte not found */ + +2: + andis. r2,r3,0x0200 /* save the Altivec Avail. bit in r2 */ + andi. r3,r3,0xffff /* clear upper SRR1 */ + or r2,r2,r3 + mtsrr1 r2 + mtdsisr r1 + mfspr r1,SPR_TLBMISS + rlwinm r1,r1,0,0,30 /* Clear the LRU bit */ + rlwinm. r2,r2,0,31,31 /* test LE bit */ + beq 3f + xori r1,r1,0x07 +3: + mtdar r1 + mtcrf 0x80,r3 + mfsprg3 r1 /* restore C ABI stack */ + LOAD_REG_FUNC(r3, dsi_exception) + mtctr r3 + bctrl + b exception_return + GLOBL(__vectors_end): =20 /************************************************************************/ --=20 2.29.2 From nobody Sat May 18 22:54:15 2024 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(unknown [9.163.29.60]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP; Fri, 19 Nov 2021 13:44:40 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=2FgDclDBFZ0Coo+j3xKpdf9IaUEUknh/O0Fh3T9/3pA=; b=CwOqEJ76Ajl2oaOa4SgmvL8P/qvOJiYPIaSLWYnYd1e5artMz5La1H0q9wQOhcBF1IO3 OkSHycnA9+a9iQX2JQX1Z9nfse0GUaV/lkKEoPJMohdxR6+45Xy2p9cBaT9dGEAu+Wx2 tlQpIC/02T84aV6/rPAlSfISiDMljXH775LyMaDbtk0Rftx28a7iZ4p327d6uCnA0egQ FloXFH0xJbVh6sJnKikr3idxt+4dWXIACPzBfs40yPNWPgMZ7DHftuN5DndgcPylTzQv ejjlV8Fv2DV0JmCXZPuhyTrtgk4ReC77m1XSVilHXU8RW5jYCLc0Jbvib3RhjPP7Fjgm Lg== From: Fabiano Rosas To: qemu-devel@nongnu.org Subject: [RFC PATCH 2/2] ppc: Add PVRs for the MPC7450 family Date: Fri, 19 Nov 2021 10:44:31 -0300 Message-Id: <20211119134431.406753-3-farosas@linux.ibm.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=farosas@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: danielhb413@gmail.com, mark.cave-ayland@ilande.co.uk, qemu-ppc@nongnu.org, clg@kaod.org, openbios@openbios.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1637329752737100001 Content-Type: text/plain; charset="utf-8" This allows the processors from the 7450 family to pass the initial PVR verification. Enables 7441, 7445, 7447, 7447a, 7448, 7450, 7451, 7455, 7457 and 7457a. Signed-off-by: Fabiano Rosas --- arch/ppc/qemu/init.c | 52 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/ppc/qemu/init.c b/arch/ppc/qemu/init.c index 45cd77e..e40385a 100644 --- a/arch/ppc/qemu/init.c +++ b/arch/ppc/qemu/init.c @@ -569,6 +569,58 @@ static const struct cpudef ppc_defs[] =3D { .tlb_size =3D 0x80, .initfn =3D cpu_g4_init, }, + { + .iu_version =3D 0x80000000, + .name =3D "PowerPC,G4", + .icache_size =3D 0x8000, + .dcache_size =3D 0x8000, + .icache_sets =3D 0x80, + .dcache_sets =3D 0x80, + .icache_block_size =3D 0x20, + .dcache_block_size =3D 0x20, + .tlb_sets =3D 0x40, + .tlb_size =3D 0x80, + .initfn =3D cpu_g4_init, + }, + { + .iu_version =3D 0x80010000, + .name =3D "PowerPC,G4", + .icache_size =3D 0x8000, + .dcache_size =3D 0x8000, + .icache_sets =3D 0x80, + .dcache_sets =3D 0x80, + .icache_block_size =3D 0x20, + .dcache_block_size =3D 0x20, + .tlb_sets =3D 0x40, + .tlb_size =3D 0x80, + .initfn =3D cpu_g4_init, + }, + { + .iu_version =3D 0x80020000, + .name =3D "PowerPC,G4", + .icache_size =3D 0x8000, + .dcache_size =3D 0x8000, + .icache_sets =3D 0x80, + .dcache_sets =3D 0x80, + .icache_block_size =3D 0x20, + .dcache_block_size =3D 0x20, + .tlb_sets =3D 0x40, + .tlb_size =3D 0x80, + .initfn =3D cpu_g4_init, + }, + { + .iu_version =3D 0x80030000, + .name =3D "PowerPC,G4", + .icache_size =3D 0x8000, + .dcache_size =3D 0x8000, + .icache_sets =3D 0x80, + .dcache_sets =3D 0x80, + .icache_block_size =3D 0x20, + .dcache_block_size =3D 0x20, + .tlb_sets =3D 0x40, + .tlb_size =3D 0x80, + .initfn =3D cpu_g4_init, + }, { .iu_version =3D 0x00390000, .name =3D "PowerPC,970", --=20 2.29.2