From nobody Tue Apr 15 19:50:38 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1637007700; cv=none; d=zohomail.com; s=zohoarc; b=VW+BzmvwQdySDypM7/gwjZ2zGJxurVMA+4FKtRzuomDHKgVj5NSWUPH4M0t9l+kb3WHGicOE1wXeYJrHWPQzP1f9knuX69Jh6yD/K94g/3+B2RwDoaXja2t3nJiBZc9MFhxWbgqm3vmbiYm6f5g97aPv9S2r/N7zayL73nMJ5eg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637007700; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=f4haQNMdKffh7OjKsAsA/oYe151uxHGwe0eJSkXUzfg=; b=aJx0Aof0o287rn/5N/pK+aperRVlXxi8Y0o3bQZT9MMOqoot4IglpsgWSXSbssiNcGxHxWT8SukNfZWlA+mcYn9jKJgcsV0nFxePdL7ZV/ksqeWUJodpwuj0eLEBXq0tnBxwVFB6Grr7E36NJRFuaRQ7593pl7ZWt/VVOilH2Vk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637007700401575.6669249840991; Mon, 15 Nov 2021 12:21:40 -0800 (PST) Received: from localhost ([::1]:47488 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mmiTx-00007g-8O for importer@patchew.org; Mon, 15 Nov 2021 15:21:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54448) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mmiSI-0006Oy-1V for qemu-devel@nongnu.org; Mon, 15 Nov 2021 15:19:55 -0500 Received: from [2a00:1450:4864:20::42b] (port=43701 helo=mail-wr1-x42b.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mmiSF-0001wU-1I for qemu-devel@nongnu.org; Mon, 15 Nov 2021 15:19:53 -0500 Received: by mail-wr1-x42b.google.com with SMTP id t30so32984124wra.10 for ; Mon, 15 Nov 2021 12:19:49 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm15419033wrs.48.2021.11.15.12.19.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Nov 2021 12:19:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f4haQNMdKffh7OjKsAsA/oYe151uxHGwe0eJSkXUzfg=; b=Rvis4gDxILf1UZPj1gNRar/m44O6hbE4gdlPMj8wvvIxvdxnYW9kGvLI9+1r/h2/3R vlmiW030zacaPc8cmuvpmPIAqBmW3x2L5+lss7swn7RzWseVwIgoeRvTEA0ZErwjWp54 dYIQqKm9dCMVD4OkDqUdx4BB6enmGN7FxRkfISoFyQkoTOeZr8knejFhh+G5bhbRIq5f 7gtE3KSHD62B7W77eC8MDL5Rm8/3HcB5XWRuTVtdXDduaSEB9d9HSxh6Pa2AFhHwV4AM Ddpa7wZhT33G8PeIr0FuDdpA2GfQQvShyHvrwTCJNby3ebsUO8V6wmwX3Zrox3ZxiGqw 266g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f4haQNMdKffh7OjKsAsA/oYe151uxHGwe0eJSkXUzfg=; b=TlIY6as/S2tQKQ+7HRWNiwHrXjHwseITbqzlNfiLtSg8Jy+2HTJM1rilfHDfpMwj0X UOjfIfA0kHfMgM6hvBoB/5/qlv/cEt5jlHoB3Sno7H1pSh03J1VLPnRrHtSVuvI9+kGt apD8eff8+1HOI1YU88xElN0j8iveb/t6Wmkee78K3+LWNos+pfDVVenD0cZ8DMEbWzau EiWDOh11jZrGkNbc/7TgLjd2deLecrobAasFsmsbW9Yv0fTFdZO3HoTpa4dzLXXlUfiP NoETzERNGAU/yKJ3EoQm8RzxJfPz26HysLwcG0mhkC1LMDCpLyBZR2+zO3pVs7oqxhxJ fNrA== X-Gm-Message-State: AOAM531jriz2JdgVu6j/8BjIy1gwxeHY+PxzIdUGBwpe+a6MdmMXrQyz wk7kDvXrac+qr1jNoFvl6jb0VfMVd1sEAw== X-Google-Smtp-Source: ABdhPJzKYTOBCDWTVGptwlRKeFUhXJ8A/1MREBGCmAj2MRLXoaTePmrh1xZY5RQAiCumsmT+vn5sAw== X-Received: by 2002:a5d:64ed:: with SMTP id g13mr2282432wri.222.1637007588874; Mon, 15 Nov 2021 12:19:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 1/4] hw/intc/arm_gicv3: Move checking of redist-region-count to arm_gicv3_common_realize Date: Mon, 15 Nov 2021 20:19:43 +0000 Message-Id: <20211115201946.327770-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211115201946.327770-1-peter.maydell@linaro.org> References: <20211115201946.327770-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42b (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1637007701551100083 Content-Type: text/plain; charset="utf-8" The GICv3 devices have an array property redist-region-count. Currently we check this for errors (bad values) in gicv3_init_irqs_and_mmio(), just before we use it. Move this error checking to the arm_gicv3_common_realize() function, where we sanity-check all of the other base-class properties. (This will always be before gicv3_init_irqs_and_mmio() is called, because that function is called in the subclass realize methods, after they have called the parent-class realize.) The motivation for this refactor is: * we would like to use the redist_region_count[] values in arm_gicv3_common_realize() in a subsequent patch, so we need to have already done the sanity-checking first * this removes the only use of the Error** argument to gicv3_init_irqs_and_mmio(), so we can remove some error-handling boilerplate Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/intc/arm_gicv3_common.h | 2 +- hw/intc/arm_gicv3.c | 6 +----- hw/intc/arm_gicv3_common.c | 26 +++++++++++++------------- hw/intc/arm_gicv3_kvm.c | 6 +----- 4 files changed, 16 insertions(+), 24 deletions(-) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index aa4f0d67703..cb2b0d0ad45 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -306,6 +306,6 @@ struct ARMGICv3CommonClass { }; =20 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, - const MemoryRegionOps *ops, Error **errp); + const MemoryRegionOps *ops); =20 #endif diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 3f24707838c..bcf54a5f0a5 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -393,11 +393,7 @@ static void arm_gic_realize(DeviceState *dev, Error **= errp) return; } =20 - gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } + gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops); =20 gicv3_init_cpuif(s); } diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 223db16feca..8e47809398b 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -250,22 +250,11 @@ static const VMStateDescription vmstate_gicv3 =3D { }; =20 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, - const MemoryRegionOps *ops, Error **errp) + const MemoryRegionOps *ops) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(s); - int rdist_capacity =3D 0; int i; =20 - for (i =3D 0; i < s->nb_redist_regions; i++) { - rdist_capacity +=3D s->redist_region_count[i]; - } - if (rdist_capacity < s->num_cpu) { - error_setg(errp, "Capacity of the redist regions(%d) " - "is less than number of vcpus(%d)", - rdist_capacity, s->num_cpu); - return; - } - /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. * GPIO array layout is thus: * [0..N-1] spi @@ -308,7 +297,7 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_h= andler handler, static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) { GICv3State *s =3D ARM_GICV3_COMMON(dev); - int i; + int i, rdist_capacity; =20 /* revision property is actually reserved and currently used only in o= rder * to keep the interface compatible with GICv2 code, avoiding extra @@ -350,6 +339,17 @@ static void arm_gicv3_common_realize(DeviceState *dev,= Error **errp) return; } =20 + rdist_capacity =3D 0; + for (i =3D 0; i < s->nb_redist_regions; i++) { + rdist_capacity +=3D s->redist_region_count[i]; + } + if (rdist_capacity < s->num_cpu) { + error_setg(errp, "Capacity of the redist regions(%d) " + "is less than number of vcpus(%d)", + rdist_capacity, s->num_cpu); + return; + } + s->cpu =3D g_new0(GICv3CPUState, s->num_cpu); =20 for (i =3D 0; i < s->num_cpu; i++) { diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 5c09f00dec2..ab58c73306d 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -787,11 +787,7 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Er= ror **errp) return; } =20 - gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } + gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL); =20 for (i =3D 0; i < s->num_cpu; i++) { ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(i)); --=20 2.25.1 From nobody Tue Apr 15 19:50:38 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm15419033wrs.48.2021.11.15.12.19.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Nov 2021 12:19:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/FrkFAbtSj7hzBVDrw01oKq3F/1xZxwyEpzR3lX7oDg=; b=Kylfp+Gui4WPeSZsM6GOeYTN0xf/SFLTnkhK6B203QzpZmFP4DwLsVkfxhcDapeoo5 2u8RJm5m3PK8bPdCz16JODMt6njyhiz7NBF4/QMRflDpIHQCaQsWZ9ScpRsmVVmPhhCt aCwJViteF3kUYbrHQRAiC3sseWhGV+aAoK5Z9fLGDoVLUk/vp3SggNBJKde68Zb2b1Np PDug6Lw02dsROY+1Ysvx99yu5LNWgenplBmjrU56FS7beYVgn0boTSEHfyQ7m1Tbp1KP 1ox418c5/VOOEpKbixJtIfj5JIu4fS5V4mlkBTE6/phgaRE0B64x0JFov9MqD27ttxKo sN5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/FrkFAbtSj7hzBVDrw01oKq3F/1xZxwyEpzR3lX7oDg=; b=4/uvZzL4u8/w53KXVGLafgrf9mXQ6V+jnVaOx+h+7C5CXDVeB9SmeQXndQkty4C96r 3qjB2DsKbJN+sXpGwOlGnbXEOcBCRHTvP3z/DVGrCEAXz3vRokBHbQOTwdBmXh8hI8MY 2avrcp8ilyJ1i1bhbIfyFQBr42rM5l9Z7Qgk7Sh05r2mk/cTd4RnrE7uFcRguYZrtSWo 6/BDuv4GFNTRP8aORQuiwp5IQr3H7h6GRJLr6uN7qTAGhUtmjJhi3oN+dgBNXKej/N0f V4NHoj/YeiWpTXPfzojxQLyXhpgF9tVjZfFZwm/Y8aakE5djEVAtm+3EYHf5NjbTQN2f CT/Q== X-Gm-Message-State: AOAM530mJu+lClaaDE8+hyw0FGQUPu7CWBkVslb26ZW7Uq/P3wf8TSZg ZDHAcx+aANmAGLijPUMuG6kDDSiWtp46Ng== X-Google-Smtp-Source: ABdhPJwFl+ImXnDxpOHNJsPs+F3TI4doNAGCttjqJNQuRjvrsV6AvhFpNXM+Tb/BMEQAEuuwpw4Zkg== X-Received: by 2002:a05:600c:4e07:: with SMTP id b7mr59920769wmq.8.1637007589422; Mon, 15 Nov 2021 12:19:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 2/4] hw/intc/arm_gicv3: Set GICR_TYPER.Last correctly when nb_redist_regions > 1 Date: Mon, 15 Nov 2021 20:19:44 +0000 Message-Id: <20211115201946.327770-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211115201946.327770-1-peter.maydell@linaro.org> References: <20211115201946.327770-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::333 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1637007786565100001 Content-Type: text/plain; charset="utf-8" The 'Last' bit in the GICR_TYPER GICv3 redistributor register is supposed to be set to 1 if this is the last redistributor in a series of contiguous redistributor pages. Currently we set Last only for the redistributor for CPU (num_cpu - 1). This only works if there is a single redistributor region; if there are multiple redistributor regions then we need to set the Last bit for the last redistributor in each region. This doesn't cause any problems currently because only the KVM GICv3 supports multiple redistributor regions, and it ignores the value in GICv3State::gicr_typer. But we need to fix this before we can enable support for multiple regions in the emulated GICv3. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_common.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 8e47809398b..8de9205b386 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -297,7 +297,7 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_h= andler handler, static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) { GICv3State *s =3D ARM_GICV3_COMMON(dev); - int i, rdist_capacity; + int i, rdist_capacity, cpuidx; =20 /* revision property is actually reserved and currently used only in o= rder * to keep the interface compatible with GICv2 code, avoiding extra @@ -355,7 +355,6 @@ static void arm_gicv3_common_realize(DeviceState *dev, = Error **errp) for (i =3D 0; i < s->num_cpu; i++) { CPUState *cpu =3D qemu_get_cpu(i); uint64_t cpu_affid; - int last; =20 s->cpu[i].cpu =3D cpu; s->cpu[i].gic =3D s; @@ -375,7 +374,6 @@ static void arm_gicv3_common_realize(DeviceState *dev, = Error **errp) * PLPIS =3D=3D 0 (physical LPIs not supported) */ cpu_affid =3D object_property_get_uint(OBJECT(cpu), "mp-affinity",= NULL); - last =3D (i =3D=3D s->num_cpu - 1); =20 /* The CPU mp-affinity property is in MPIDR register format; squash * the affinity bytes into 32 bits as the GICR_TYPER has them. @@ -384,13 +382,22 @@ static void arm_gicv3_common_realize(DeviceState *dev= , Error **errp) (cpu_affid & 0xFFFFFF); s->cpu[i].gicr_typer =3D (cpu_affid << 32) | (1 << 24) | - (i << 8) | - (last << 4); + (i << 8); =20 if (s->lpi_enable) { s->cpu[i].gicr_typer |=3D GICR_TYPER_PLPIS; } } + + /* + * Now go through and set GICR_TYPER.Last for the final + * redistributor in each region. + */ + cpuidx =3D 0; + for (i =3D 0; i < s->nb_redist_regions; i++) { + cpuidx +=3D s->redist_region_count[i]; + s->cpu[cpuidx - 1].gicr_typer |=3D GICR_TYPER_LAST; + } } =20 static void arm_gicv3_finalize(Object *obj) --=20 2.25.1 From nobody Tue Apr 15 19:50:38 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1637007701; cv=none; d=zohomail.com; s=zohoarc; b=PWOnNZkwtnd/TO6CCZrAs+XZKXGLnRUeSCzg0UZK+cx6HrvUPwr+jW8WMJRKs6lBiM2w957dVSHjhYkucG5ZUd3j/VLrt0F/mJtMfM8Gb4vD75d4cKS6dojzH9n7XfaevDjVnQdo4rXCFiPMv+nIEUFx4jcrpFXpcdq87Eswdy0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637007701; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5DM3N2GiZ5nQ0yywEE7g0QO0v2WNK/EcT7McNX9kK5I=; b=e/ezA/Zm5HUrgPJWpydEu2kSMPAGUzv/5eABVo1m+xPG4NYsSC+Ru4C5s2qNAN9RAwJeHlCBYJKKGfWvY8AfgT5vcNtkAxJjD8hbtM1ZeqbmO9yDOkY2bIBTbREAY6sdviHCoeCv5xYrkpr8cDNMB4VEUmiJXoiiu+oyLzn/nAo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637007701042239.06124799589736; Mon, 15 Nov 2021 12:21:41 -0800 (PST) Received: from localhost ([::1]:47500 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mmiTx-000082-GH for importer@patchew.org; Mon, 15 Nov 2021 15:21:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54454) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mmiSI-0006P0-4G for qemu-devel@nongnu.org; Mon, 15 Nov 2021 15:19:57 -0500 Received: from [2a00:1450:4864:20::435] (port=44953 helo=mail-wr1-x435.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mmiSF-0001we-G9 for qemu-devel@nongnu.org; Mon, 15 Nov 2021 15:19:53 -0500 Received: by mail-wr1-x435.google.com with SMTP id n29so32991534wra.11 for ; Mon, 15 Nov 2021 12:19:51 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm15419033wrs.48.2021.11.15.12.19.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Nov 2021 12:19:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5DM3N2GiZ5nQ0yywEE7g0QO0v2WNK/EcT7McNX9kK5I=; b=PKi56hEpdpUExBPeoVonER5QTQwGwhj2QJKbkHvLT7BK197zdP2lRA4pGWmVMy4AU6 ksSvL4YGwvnj9o4vckDnkuoFBhvqlav1qnzgEB8FE5/LQ4BdoUsEbIWcczrZj67ynOfM 63sAw4eFnTVfyya3LRqzJtui5Oeav1SN0U+VJw+n5iSaMNE1Kn+cZEDgWAnFC/ScJ8Ae SbzCRoNPHGF8LoKvaqIbdPElfZk0TevtB/vxcK2dUFqV06BogppR+KDqfnG9Xm60jPTW 1Wd2qiXjuoUGoKK6g+RMKfuUPPTllVbKD2Jt39SQpEXDo/ble4k8vQAqQbTVCaY48nmb BZ1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5DM3N2GiZ5nQ0yywEE7g0QO0v2WNK/EcT7McNX9kK5I=; b=oxEY+aUzVpUl1s4RNghKhPqmaFDTMsop/0KY9Tjwh9e0pqlyXY87JMXOgpbjz7fCwc 13xJgNbqEmICB6lmc+/KpH1h9WJZSVgzTqJkiAJQXMkqofgWxmBD2uT+6cQDAa4wxpF0 Tl1OHBL51IOfnUnEB0H1DFmA/JvY6Huo5KB4uWY4hkJjE8QABY/Vol5qR2sen/Mzm0Qq rfjYypszI8hE7N9DjdUNp3jaynJQC7AeaTAtlMyPPHN/8OwRJ6gwtcRB+6dbYeU8cZmx E1oqf2KIhCivuRS8oSK9DKmauk5fXJ+zKNatmmWQPfsWtQq/cYwCqwwWclQuVuMe6RMl kV/w== X-Gm-Message-State: AOAM531qpypPS1X61NNF5/ykR6V42QbyGXy8L1P/6s0eeHZrtdIki67b QhypYOGsClTBFD5sqOi6y8/13kCCwT1p6g== X-Google-Smtp-Source: ABdhPJxw4FsyNykZaDYenJtP3yKFrfKpshVVsAz4BB2hmfnnKzS29lGHbUqLkgn203AjcIrVyGNeBA== X-Received: by 2002:adf:dd0d:: with SMTP id a13mr2075352wrm.259.1637007590016; Mon, 15 Nov 2021 12:19:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/4] hw/intc/arm_gicv3: Support multiple redistributor regions Date: Mon, 15 Nov 2021 20:19:45 +0000 Message-Id: <20211115201946.327770-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211115201946.327770-1-peter.maydell@linaro.org> References: <20211115201946.327770-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::435 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1637007701932100085 Content-Type: text/plain; charset="utf-8" Our GICv3 QOM interface includes an array property redist-region-count which allows board models to specify that the registributor registers are not in a single contiguous range, but split into multiple pieces. We implemented this for KVM, but currently the TCG GICv3 model insists that there is only one region. You can see the limit being hit with a setup like: qemu-system-aarch64 -machine virt,gic-version=3D3 -smp 124 Add support for split regions to the TCG GICv3. To do this we switch from allocating a simple array of MemoryRegions to an array of GICv3RedistRegion structs so that we can use the GICv3RedistRegion as the opaque pointer in the MemoryRegion read/write callbacks. Each GICv3RedistRegion contains the MemoryRegion, a backpointer allowing the read/write callback to get hold of the GICv3State, and an index which allows us to calculate which CPU's redistributor is being accessed. Note that arm_gicv3_kvm always passes in NULL as the ops argument to gicv3_init_irqs_and_mmio(), so the only MemoryRegion read/write callbacks we need to update to handle this new scheme are the gicv3_redist_read/write functions used by the emulated GICv3. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/intc/arm_gicv3_common.h | 12 ++++++++- hw/intc/arm_gicv3.c | 6 ----- hw/intc/arm_gicv3_common.c | 15 ++++++++--- hw/intc/arm_gicv3_kvm.c | 4 +-- hw/intc/arm_gicv3_redist.c | 40 ++++++++++++++++-------------- 5 files changed, 46 insertions(+), 31 deletions(-) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index cb2b0d0ad45..fc38e4b7dca 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -215,13 +215,23 @@ struct GICv3CPUState { bool seenbetter; }; =20 +/* + * The redistributor pages might be split into more than one region + * on some machine types if there are many CPUs. + */ +typedef struct GICv3RedistRegion { + GICv3State *gic; + MemoryRegion iomem; + uint32_t cpuidx; /* index of first CPU this region covers */ +} GICv3RedistRegion; + struct GICv3State { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ =20 MemoryRegion iomem_dist; /* Distributor */ - MemoryRegion *iomem_redist; /* Redistributor Regions */ + GICv3RedistRegion *redist_regions; /* Redistributor Regions */ uint32_t *redist_region_count; /* redistributor count within each regi= on */ uint32_t nb_redist_regions; /* number of redist regions */ =20 diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index bcf54a5f0a5..c6282984b1e 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -387,12 +387,6 @@ static void arm_gic_realize(DeviceState *dev, Error **= errp) return; } =20 - if (s->nb_redist_regions !=3D 1) { - error_setg(errp, "VGICv3 redist region number(%d) not equal to 1", - s->nb_redist_regions); - return; - } - gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops); =20 gicv3_init_cpuif(s); diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 8de9205b386..9884d2e39b9 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -254,6 +254,7 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_h= andler handler, { SysBusDevice *sbd =3D SYS_BUS_DEVICE(s); int i; + int cpuidx; =20 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. * GPIO array layout is thus: @@ -282,14 +283,20 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq= _handler handler, "gicv3_dist", 0x10000); sysbus_init_mmio(sbd, &s->iomem_dist); =20 - s->iomem_redist =3D g_new0(MemoryRegion, s->nb_redist_regions); + s->redist_regions =3D g_new0(GICv3RedistRegion, s->nb_redist_regions); + cpuidx =3D 0; for (i =3D 0; i < s->nb_redist_regions; i++) { char *name =3D g_strdup_printf("gicv3_redist_region[%d]", i); + GICv3RedistRegion *region =3D &s->redist_regions[i]; =20 - memory_region_init_io(&s->iomem_redist[i], OBJECT(s), - ops ? &ops[1] : NULL, s, name, + region->gic =3D s; + region->cpuidx =3D cpuidx; + cpuidx +=3D s->redist_region_count[i]; + + memory_region_init_io(®ion->iomem, OBJECT(s), + ops ? &ops[1] : NULL, region, name, s->redist_region_count[i] * GICV3_REDIST_SIZ= E); - sysbus_init_mmio(sbd, &s->iomem_redist[i]); + sysbus_init_mmio(sbd, ®ion->iomem); g_free(name); } } diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index ab58c73306d..5ec5ff9ef6e 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -825,7 +825,7 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Err= or **errp) KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0); =20 if (!multiple_redist_region_allowed) { - kvm_arm_register_device(&s->iomem_redist[0], -1, + kvm_arm_register_device(&s->redist_regions[0].iomem, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0= ); } else { @@ -838,7 +838,7 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Err= or **errp) uint64_t addr_ormask =3D i | ((uint64_t)s->redist_region_count[i] << 52); =20 - kvm_arm_register_device(&s->iomem_redist[i], -1, + kvm_arm_register_device(&s->redist_regions[i].iomem, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION, s->dev_fd, addr_ormask); diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 7072bfcbb1d..424e7e28a86 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -425,22 +425,24 @@ static MemTxResult gicr_writell(GICv3CPUState *cs, hw= addr offset, MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data, unsigned size, MemTxAttrs attrs) { - GICv3State *s =3D opaque; + GICv3RedistRegion *region =3D opaque; + GICv3State *s =3D region->gic; GICv3CPUState *cs; MemTxResult r; int cpuidx; =20 assert((offset & (size - 1)) =3D=3D 0); =20 - /* This region covers all the redistributor pages; there are - * (for GICv3) two 64K pages per CPU. At the moment they are - * all contiguous (ie in this one region), though we might later - * want to allow splitting of redistributor pages into several - * blocks so we can support more CPUs. + /* + * There are (for GICv3) two 64K redistributor pages per CPU. + * In some cases the redistributor pages for all CPUs are not + * contiguous (eg on the virt board they are split into two + * parts if there are too many CPUs to all fit in the same place + * in the memory map); if so then the GIC has multiple MemoryRegions + * for the redistributors. */ - cpuidx =3D offset / 0x20000; - offset %=3D 0x20000; - assert(cpuidx < s->num_cpu); + cpuidx =3D region->cpuidx + offset / GICV3_REDIST_SIZE; + offset %=3D GICV3_REDIST_SIZE; =20 cs =3D &s->cpu[cpuidx]; =20 @@ -482,22 +484,24 @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr of= fset, uint64_t *data, MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data, unsigned size, MemTxAttrs attrs) { - GICv3State *s =3D opaque; + GICv3RedistRegion *region =3D opaque; + GICv3State *s =3D region->gic; GICv3CPUState *cs; MemTxResult r; int cpuidx; =20 assert((offset & (size - 1)) =3D=3D 0); =20 - /* This region covers all the redistributor pages; there are - * (for GICv3) two 64K pages per CPU. At the moment they are - * all contiguous (ie in this one region), though we might later - * want to allow splitting of redistributor pages into several - * blocks so we can support more CPUs. + /* + * There are (for GICv3) two 64K redistributor pages per CPU. + * In some cases the redistributor pages for all CPUs are not + * contiguous (eg on the virt board they are split into two + * parts if there are too many CPUs to all fit in the same place + * in the memory map); if so then the GIC has multiple MemoryRegions + * for the redistributors. */ - cpuidx =3D offset / 0x20000; - offset %=3D 0x20000; - assert(cpuidx < s->num_cpu); + cpuidx =3D region->cpuidx + offset / GICV3_REDIST_SIZE; + offset %=3D GICV3_REDIST_SIZE; =20 cs =3D &s->cpu[cpuidx]; =20 --=20 2.25.1 From nobody Tue Apr 15 19:50:38 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1637007880; cv=none; d=zohomail.com; s=zohoarc; b=OsdUPf+i3TizIdTKCIp7+y+RyoC8LIHU5zmpQJE4kCbWmZMRhfHuWPcH5M12+fGpiC+X0K+Z1C0v2HtKAPIZpF75dfFNm9IK6bxKxE8J4cTspSta/+azYCRfvBrSMl6tDV/T590OZ0bH/4T2e8eDWdQzvgl+d0oSrMsH0iOcibw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1637007880; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CFmTiNbFo097ebi7K9NxSL9BNaZOJ1x8cr0AzAxsLFE=; b=dBLmIkFGlzlR1F9B0TtPwSRN59Z7sTCtQWo1fmfFo3VFOJd6LXyfsDGTnQmwHChtdAmGt9PHAfQqEtmlyMH03iKMog0NVPVHlDXfKa7W2BRuOCfYyrjDcCdq/cMqKllctCwgpfBV4ySIgmUjplN0WO2w5wT/yMhIuqlX+q3LGqk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637007880288615.1142911240524; Mon, 15 Nov 2021 12:24:40 -0800 (PST) Received: from localhost ([::1]:56316 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mmiWt-00069j-BD for importer@patchew.org; Mon, 15 Nov 2021 15:24:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54456) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mmiSI-0006P3-TS for qemu-devel@nongnu.org; Mon, 15 Nov 2021 15:19:57 -0500 Received: from [2a00:1450:4864:20::332] (port=38534 helo=mail-wm1-x332.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mmiSG-0001wj-1n for qemu-devel@nongnu.org; Mon, 15 Nov 2021 15:19:54 -0500 Received: by mail-wm1-x332.google.com with SMTP id p3-20020a05600c1d8300b003334fab53afso186910wms.3 for ; Mon, 15 Nov 2021 12:19:51 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm15419033wrs.48.2021.11.15.12.19.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Nov 2021 12:19:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CFmTiNbFo097ebi7K9NxSL9BNaZOJ1x8cr0AzAxsLFE=; b=fmu+cbtnISakcs63Attx7wFpqMGLl3ofQs+kyDx81/YDbPpi2Bx/lqRckHPGcyz50V X/2NBIpuMl7N4UUBJPApR5o2mDfXaa9DGYwGp7T2TXoW8rzDkHar7xl2I0mT6BCRkgw3 tKSqD0nwUrQMurNEnQFdCsh3peX10fFgpA0m/564A2n1PAgsJE8/gYJ+GpJZGN3FtQgF FbAPy+b49DV+Uszgqde53N2idGz+sQy46xQcQD13rGfmPPRrf5o4dwYamuYmj0xGbeqo ZgQ/+qqK89YyFQ/AtjcMwU7y5FyHQw1m+anckzVOU7vc0wHrbng/HPu2QrlBg32FAalH KvjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CFmTiNbFo097ebi7K9NxSL9BNaZOJ1x8cr0AzAxsLFE=; b=WtCglg6FSUNPFz/M0xp0pXN75KgrvzpDA9C/9vQmETNd99mOlcwB6nLlglvpvkHjZj fYbXGqiY/+BZVtB38RV3z7e8q0IMYvl4kXmvKy6zR6dL6Q5GeVD87IQ+xuzsfGwXwtZv QYcMVjEVN49gmNdC4QRwjJGSfp5tjTCIoUMTFYb2bEYQQOrpQdoq6eq7LbD+gluYNnZk KGvUXaeyDX8vl623KNLNesXmsCU9BZye+zZhxYrl/peVAfn58LaHckHzQgiNaR52gbxD bcilfBDO4VCFIoPYCxXw4ekrXRWjr2S+rvQKsgTxrYJGcqjyvLJnXaWGN0qg79vkYwTZ AvwQ== X-Gm-Message-State: AOAM530gPBe2hwcyrR+3Vh9bR8nCsmNoq8JjP88XFd9NBZQ9qD0ksS7Z QDo1ZhMLN6Moco2gsoyKUzLjd76tNMfNqQ== X-Google-Smtp-Source: ABdhPJzfGuwGP5UPKlNYijluXwjN2Le1AKns7flRln5U1DCQJLyUXI4tZ65Y8J2wN9jmwINI3yfi7g== X-Received: by 2002:a7b:c389:: with SMTP id s9mr1322722wmj.133.1637007590555; Mon, 15 Nov 2021 12:19:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 4/4] hw/rtc/pl031: Send RTC_CHANGE QMP event Date: Mon, 15 Nov 2021 20:19:46 +0000 Message-Id: <20211115201946.327770-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211115201946.327770-1-peter.maydell@linaro.org> References: <20211115201946.327770-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::332 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1637007882328100001 Content-Type: text/plain; charset="utf-8" From: Eric Auger The PL031 currently is not able to report guest RTC change to the QMP monitor as opposed to mc146818 or spapr RTCs. This patch adds the call to qapi_event_send_rtc_change() when the Load Register is written. The value which is reported corresponds to the difference between the guest reference time and the reference time kept in softmmu/rtc.c. For instance adding 20s to the guest RTC value will report 20. Adding an extra 20s to the guest RTC value will report 20 + 20 =3D 40. The inclusion of qapi/qapi-types-misc-target.h in hw/rtl/pl031.c require to compile the PL031 with specific_ss.add() to avoid ./qapi/qapi-types-misc-target.h:18:13: error: attempt to use poisoned "TARGET_". Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 20210920122535.269988-1-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/rtc/pl031.c | 10 +++++++++- hw/rtc/meson.build | 2 +- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/rtc/pl031.c b/hw/rtc/pl031.c index 2bbb2062ac8..e7ced90b025 100644 --- a/hw/rtc/pl031.c +++ b/hw/rtc/pl031.c @@ -24,6 +24,7 @@ #include "qemu/log.h" #include "qemu/module.h" #include "trace.h" +#include "qapi/qapi-events-misc-target.h" =20 #define RTC_DR 0x00 /* Data read register */ #define RTC_MR 0x04 /* Match register */ @@ -136,10 +137,17 @@ static void pl031_write(void * opaque, hwaddr offset, trace_pl031_write(offset, value); =20 switch (offset) { - case RTC_LR: + case RTC_LR: { + struct tm tm; + s->tick_offset +=3D value - pl031_get_count(s); + + qemu_get_timedate(&tm, s->tick_offset); + qapi_event_send_rtc_change(qemu_timedate_diff(&tm)); + pl031_set_alarm(s); break; + } case RTC_MR: s->mr =3D value; pl031_set_alarm(s); diff --git a/hw/rtc/meson.build b/hw/rtc/meson.build index 7cecdee5ddb..8fd8d8f9a71 100644 --- a/hw/rtc/meson.build +++ b/hw/rtc/meson.build @@ -2,7 +2,7 @@ softmmu_ss.add(when: 'CONFIG_DS1338', if_true: files('ds1338.c')) softmmu_ss.add(when: 'CONFIG_M41T80', if_true: files('m41t80.c')) softmmu_ss.add(when: 'CONFIG_M48T59', if_true: files('m48t59.c')) -softmmu_ss.add(when: 'CONFIG_PL031', if_true: files('pl031.c')) +specific_ss.add(when: 'CONFIG_PL031', if_true: files('pl031.c')) softmmu_ss.add(when: 'CONFIG_TWL92230', if_true: files('twl92230.c')) softmmu_ss.add(when: ['CONFIG_ISA_BUS', 'CONFIG_M48T59'], if_true: files('= m48t59-isa.c')) softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-rtc= .c')) --=20 2.25.1