From nobody Tue Feb 10 07:23:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636611105554511.47087583401594; Wed, 10 Nov 2021 22:11:45 -0800 (PST) Received: from localhost ([::1]:55872 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml3JI-0005jS-HJ for importer@patchew.org; Thu, 11 Nov 2021 01:11:44 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48482) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3Ba-0006FN-SC; Thu, 11 Nov 2021 01:03:47 -0500 Received: from out28-218.mail.aliyun.com ([115.124.28.218]:36157) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3BZ-0003pH-3S; Thu, 11 Nov 2021 01:03:46 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr1ZjwY_1636610619) by smtp.aliyun-inc.com(10.147.43.95); Thu, 11 Nov 2021 14:03:39 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07439946|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.00511344-3.239e-05-0.994854; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047193; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr1ZjwY_1636610619; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 11/20] target/riscv: Split pm_enabled into mask and base Date: Thu, 11 Nov 2021 13:57:51 +0800 Message-Id: <20211111055800.42672-12-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.218; envelope-from=zhiwei_liu@c-sky.com; helo=out28-218.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636611107915100003 Content-Type: text/plain; charset="utf-8" Use cached cur_pmmask and cur_pmbase to infer the current PM mode. This may decrease the TCG IR by one when pm_enabled is true and pm_base_enabled is false. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 3 ++- target/riscv/cpu_helper.c | 25 +++++++------------------ target/riscv/translate.c | 12 ++++++++---- 3 files changed, 17 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fa5a6ba1c8..9fba876e08 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -411,7 +411,8 @@ FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ FIELD(TB_FLAGS, XL, 13, 2) /* If PointerMasking should be applied */ -FIELD(TB_FLAGS, PM_ENABLED, 15, 1) +FIELD(TB_FLAGS, PM_MASK_ENABLED, 15, 1) +FIELD(TB_FLAGS, PM_BASE_ENABLED, 16, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8320f56d9f..a40ed6d748 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -108,26 +108,15 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_= ulong *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, get_field(env->mstatus_hs, MSTATUS_FS)); } - if (riscv_has_ext(env, RVJ)) { - int priv =3D flags & TB_FLAGS_PRIV_MMU_MASK; - bool pm_enabled =3D false; - switch (priv) { - case PRV_U: - pm_enabled =3D env->mmte & U_PM_ENABLE; - break; - case PRV_S: - pm_enabled =3D env->mmte & S_PM_ENABLE; - break; - case PRV_M: - pm_enabled =3D env->mmte & M_PM_ENABLE; - break; - default: - g_assert_not_reached(); - } - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled); - } #endif =20 + if (env->cur_pmmask < (xl =3D=3D MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); + } + if (env->cur_pmbase !=3D 0) { + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); + } + flags =3D FIELD_DP32(flags, TB_FLAGS, XL, xl); =20 *pflags =3D flags; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index fd75f7c4bc..10c16e759d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -87,7 +87,8 @@ typedef struct DisasContext { /* Space for 3 operands plus 1 extra for address computation. */ TCGv temp[4]; /* PointerMasking extension */ - bool pm_enabled; + bool pm_mask_enabled; + bool pm_base_enabled; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -291,12 +292,14 @@ static TCGv get_address(DisasContext *ctx, int rs1, i= nt imm) TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_addi_tl(addr, src1, imm); - if (ctx->pm_enabled) { + if (ctx->pm_mask_enabled) { tcg_gen_and_tl(addr, addr, pm_mask); - tcg_gen_or_tl(addr, addr, pm_base); } else if (get_xl(ctx) =3D=3D MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } + if (ctx->pm_base_enabled) { + tcg_gen_or_tl(addr, addr, pm_base); + } return addr; } =20 @@ -643,7 +646,8 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->cs =3D cs; ctx->ntemp =3D 0; memset(ctx->temp, 0, sizeof(ctx->temp)); - ctx->pm_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); + ctx->pm_mask_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLE= D); + ctx->pm_base_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLE= D); ctx->zero =3D tcg_constant_tl(0); } =20 --=20 2.25.1