From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636610486349514.7588416963434; Wed, 10 Nov 2021 22:01:26 -0800 (PST) Received: from localhost ([::1]:39644 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml39J-0002vH-6b for importer@patchew.org; Thu, 11 Nov 2021 01:01:25 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml36g-0000UH-Pp; Thu, 11 Nov 2021 00:58:42 -0500 Received: from out28-197.mail.aliyun.com ([115.124.28.197]:54253) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml36e-0003AF-Be; Thu, 11 Nov 2021 00:58:42 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr1f.Tc_1636610313) by smtp.aliyun-inc.com(10.147.40.2); Thu, 11 Nov 2021 13:58:33 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.0745289|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0106131-0.000399075-0.988988; FP=3095924200578694771|2|2|6|0|-1|-1|-1; HT=ay29a033018047207; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr1f.Tc_1636610313; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 01/20] target/riscv: Don't save pc when exception return Date: Thu, 11 Nov 2021 13:57:41 +0800 Message-Id: <20211111055800.42672-2-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.197; envelope-from=zhiwei_liu@c-sky.com; helo=out28-197.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636610487687100001 Content-Type: text/plain; charset="utf-8" As pc will be written by the xepc in exception return, just ignore pc in translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 4 ++-- target/riscv/insn_trans/trans_privileged.c.inc | 7 ++----- target/riscv/op_helper.c | 4 ++-- 3 files changed, 6 insertions(+), 9 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c7a5376227..c5098380dd 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -67,8 +67,8 @@ DEF_HELPER_2(csrr, tl, env, int) DEF_HELPER_3(csrw, void, env, int, tl) DEF_HELPER_4(csrrw, tl, env, int, tl, tl) #ifndef CONFIG_USER_ONLY -DEF_HELPER_2(sret, tl, env, tl) -DEF_HELPER_2(mret, tl, env, tl) +DEF_HELPER_1(sret, tl, env) +DEF_HELPER_1(mret, tl, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(tlb_flush, void, env) #endif diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index 75c6ef80a6..6077bbbf11 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -74,10 +74,8 @@ static bool trans_uret(DisasContext *ctx, arg_uret *a) static bool trans_sret(DisasContext *ctx, arg_sret *a) { #ifndef CONFIG_USER_ONLY - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - if (has_ext(ctx, RVS)) { - gen_helper_sret(cpu_pc, cpu_env, cpu_pc); + gen_helper_sret(cpu_pc, cpu_env); tcg_gen_exit_tb(NULL, 0); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; } else { @@ -92,8 +90,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - gen_helper_mret(cpu_pc, cpu_env, cpu_pc); + gen_helper_mret(cpu_pc, cpu_env); tcg_gen_exit_tb(NULL, 0); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; return true; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index ee7c24efe7..095d39671b 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -71,7 +71,7 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr, =20 #ifndef CONFIG_USER_ONLY =20 -target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) +target_ulong helper_sret(CPURISCVState *env) { uint64_t mstatus; target_ulong prev_priv, prev_virt; @@ -132,7 +132,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) return retpc; } =20 -target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) +target_ulong helper_mret(CPURISCVState *env) { if (!(env->priv >=3D PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636610506790807.2364989982924; Wed, 10 Nov 2021 22:01:46 -0800 (PST) Received: from localhost ([::1]:40362 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml39d-0003Oy-QS for importer@patchew.org; Thu, 11 Nov 2021 01:01:45 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47892) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml379-00014Q-TN; Thu, 11 Nov 2021 00:59:13 -0500 Received: from out28-171.mail.aliyun.com ([115.124.28.171]:46249) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml377-0003BX-CF; Thu, 11 Nov 2021 00:59:11 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr0jnTY_1636610343) by smtp.aliyun-inc.com(10.147.42.241); Thu, 11 Nov 2021 13:59:04 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1101835|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0320985-0.000647087-0.967254; FP=4212412425320115155|2|2|6|0|-1|-1|-1; HT=ay29a033018047194; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr0jnTY_1636610343; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 02/20] target/riscv: Sign extend pc for different XLEN Date: Thu, 11 Nov 2021 13:57:42 +0800 Message-Id: <20211111055800.42672-3-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.171; envelope-from=zhiwei_liu@c-sky.com; helo=out28-171.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636610508657100003 Content-Type: text/plain; charset="utf-8" When pc is written, it is sign-extended to fill the widest supported XLEN. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/translate.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1d57bc97b5..a6a73ced9e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -150,16 +150,24 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64= in) tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); } =20 +static void gen_set_pc(DisasContext *ctx, target_ulong dest) +{ + if (get_xl(ctx) =3D=3D MXL_RV32) { + dest =3D (int32_t)dest; + } + tcg_gen_movi_tl(cpu_pc, dest); +} + static void generate_exception(DisasContext *ctx, int excp) { - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + gen_set_pc(ctx, ctx->base.pc_next); gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); ctx->base.is_jmp =3D DISAS_NORETURN; } =20 static void generate_exception_mtval(DisasContext *ctx, int excp) { - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + gen_set_pc(ctx, ctx->base.pc_next); tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); ctx->base.is_jmp =3D DISAS_NORETURN; @@ -179,10 +187,10 @@ static void gen_goto_tb(DisasContext *ctx, int n, tar= get_ulong dest) { if (translator_use_goto_tb(&ctx->base, dest)) { tcg_gen_goto_tb(n); - tcg_gen_movi_tl(cpu_pc, dest); + gen_set_pc(ctx, dest); tcg_gen_exit_tb(ctx->base.tb, n); } else { - tcg_gen_movi_tl(cpu_pc, dest); + gen_set_pc(ctx, dest); tcg_gen_lookup_and_goto_ptr(); } } --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636610749463882.8668829017695; Wed, 10 Nov 2021 22:05:49 -0800 (PST) Received: from localhost ([::1]:46190 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml3DW-0007Ps-K2 for importer@patchew.org; Thu, 11 Nov 2021 01:05:48 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47968) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml37e-00021i-9d; Thu, 11 Nov 2021 00:59:42 -0500 Received: from out28-170.mail.aliyun.com ([115.124.28.170]:52793) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml37b-0003G5-NG; Thu, 11 Nov 2021 00:59:42 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr0nyfO_1636610374) by smtp.aliyun-inc.com(10.147.41.231); Thu, 11 Nov 2021 13:59:35 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1117904|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.013589-0.000341692-0.986069; FP=3134215141809239407|2|2|6|0|-1|-1|-1; HT=ay29a033018047199; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr0nyfO_1636610374; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 03/20] target/riscv: Ignore the pc bits above XLEN Date: Thu, 11 Nov 2021 13:57:43 +0800 Message-Id: <20211111055800.42672-4-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.170; envelope-from=zhiwei_liu@c-sky.com; helo=out28-170.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636610751541100001 Content-Type: text/plain; charset="utf-8" The read from PC for translation is in cpu_get_tb_cpu_state, before transla= tion. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/cpu_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9eeed38c7e..4c048cc266 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -70,8 +70,9 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, target_ulong *cs_base, uint32_t *pflags) { uint32_t flags =3D 0; + RISCVMXL xl =3D cpu_get_xl(env); =20 - *pc =3D env->pc; + *pc =3D xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; *cs_base =3D 0; =20 if (riscv_has_ext(env, RVV)) { @@ -127,7 +128,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ul= ong *pc, } #endif =20 - flags =3D FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, XL, xl); =20 *pflags =3D flags; } --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636610867310101.75556100780727; Wed, 10 Nov 2021 22:07:47 -0800 (PST) Received: from localhost ([::1]:48922 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml3FS-0000y0-9U for importer@patchew.org; Thu, 11 Nov 2021 01:07:46 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48070) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml38A-0002el-QL; Thu, 11 Nov 2021 01:00:16 -0500 Received: from out28-50.mail.aliyun.com ([115.124.28.50]:37033) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml387-0003Ib-KU; Thu, 11 Nov 2021 01:00:14 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr1AFTT_1636610405) by smtp.aliyun-inc.com(10.147.44.129); Thu, 11 Nov 2021 14:00:05 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07465442|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.081855-0.000518238-0.917627; FP=12841426174990123083|2|2|6|0|-1|-1|-1; HT=ay29a033018047213; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr1AFTT_1636610405; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 04/20] target/riscv: Extend pc for runtime pc write Date: Thu, 11 Nov 2021 13:57:44 +0800 Message-Id: <20211111055800.42672-5-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.50; envelope-from=zhiwei_liu@c-sky.com; helo=out28-50.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636610867858100001 Content-Type: text/plain; charset="utf-8" In some cases, we must restore the guest PC to the address of the start of the TB, such as when the instruction counter hits zero. So extend pc regist= er according to current xlen for these cases. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 22 +++++++++++++++++++--- target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 2 +- 3 files changed, 22 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f812998123..0d2d175fa2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -319,7 +319,12 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - env->pc =3D value; + + if (cpu_get_xl(env) =3D=3D MXL_RV32) { + env->pc =3D (int32_t)value; + } else { + env->pc =3D value; + } } =20 static void riscv_cpu_synchronize_from_tb(CPUState *cs, @@ -327,7 +332,13 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - env->pc =3D tb->pc; + RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); + + if (xl =3D=3D MXL_RV32) { + env->pc =3D (int32_t)tb->pc; + } else { + env->pc =3D tb->pc; + } } =20 static bool riscv_cpu_has_work(CPUState *cs) @@ -348,7 +359,12 @@ static bool riscv_cpu_has_work(CPUState *cs) void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, target_ulong *data) { - env->pc =3D data[0]; + RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); + if (xl =3D=3D MXL_RV32) { + env->pc =3D (int32_t)data[0]; + } else { + env->pc =3D data[0]; + } } =20 static void riscv_cpu_reset(DeviceState *dev) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0760c0af93..8befff0166 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -420,6 +420,8 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) } #endif =20 +RISCVMXL cpu_get_xl(CPURISCVState *env); + /* * A simplification for VLMAX * =3D (1 << LMUL) * VLEN / (8 * (1 << SEW)) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4c048cc266..79aba9c880 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -35,7 +35,7 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } =20 -static RISCVMXL cpu_get_xl(CPURISCVState *env) +RISCVMXL cpu_get_xl(CPURISCVState *env) { #if defined(TARGET_RISCV32) return MXL_RV32; --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636611127429531.5045647991326; Wed, 10 Nov 2021 22:12:07 -0800 (PST) Received: from localhost ([::1]:57404 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml3Je-0006lB-5x for importer@patchew.org; Thu, 11 Nov 2021 01:12:06 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48198) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml38e-0002rj-0o; Thu, 11 Nov 2021 01:00:44 -0500 Received: from out28-121.mail.aliyun.com ([115.124.28.121]:58497) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml38a-0003TQ-Qx; Thu, 11 Nov 2021 01:00:43 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr0nzHO_1636610436) by smtp.aliyun-inc.com(10.147.41.231); Thu, 11 Nov 2021 14:00:36 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07453308|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0231685-0.000144035-0.976687; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047212; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr0nzHO_1636610436; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 05/20] target/riscv: Use gdb xml according to max mxlen Date: Thu, 11 Nov 2021 13:57:45 +0800 Message-Id: <20211111055800.42672-6-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.121; envelope-from=zhiwei_liu@c-sky.com; helo=out28-121.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636611129308100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/gdbstub.c | 71 +++++++++++++++++++++++++++++++----------- 1 file changed, 52 insertions(+), 19 deletions(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 23429179e2..8d0f9139d7 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -24,11 +24,23 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArra= y *mem_buf, int n) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; + target_ulong tmp; =20 if (n < 32) { - return gdb_get_regl(mem_buf, env->gpr[n]); + tmp =3D env->gpr[n]; } else if (n =3D=3D 32) { - return gdb_get_regl(mem_buf, env->pc); + tmp =3D env->pc; + } else { + return 0; + } + + switch (env->misa_mxl_max) { + case MXL_RV32: + return gdb_get_reg32(mem_buf, tmp); + case MXL_RV64: + return gdb_get_reg64(mem_buf, tmp); + default: + g_assert_not_reached(); } return 0; } @@ -37,18 +49,32 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - - if (n =3D=3D 0) { - /* discard writes to x0 */ - return sizeof(target_ulong); - } else if (n < 32) { - env->gpr[n] =3D ldtul_p(mem_buf); - return sizeof(target_ulong); + int length =3D 0; + target_ulong tmp; + + switch (env->misa_mxl_max) { + case MXL_RV32: + tmp =3D (int32_t)ldl_p(mem_buf); + length =3D 4; + break; + case MXL_RV64: + if (cpu_get_xl(env) < MXL_RV64) { + tmp =3D (int32_t)ldq_p(mem_buf); + } else { + tmp =3D ldq_p(mem_buf); + } + length =3D 8; + break; + default: + g_assert_not_reached(); + } + if (n > 0 && n < 32) { + env->gpr[n] =3D tmp; } else if (n =3D=3D 32) { - env->pc =3D ldtul_p(mem_buf); - return sizeof(target_ulong); + env->pc =3D tmp; } - return 0; + + return length; } =20 static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) @@ -198,13 +224,20 @@ void riscv_cpu_register_gdb_regs_for_features(CPUStat= e *cs) gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-32bit-fpu.xml", 0); } -#if defined(TARGET_RISCV32) - gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virt= ual, - 1, "riscv-32bit-virtual.xml", 0); -#elif defined(TARGET_RISCV64) - gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virt= ual, - 1, "riscv-64bit-virtual.xml", 0); -#endif + switch (env->misa_mxl_max) { + case MXL_RV32: + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, + riscv_gdb_set_virtual, + 1, "riscv-32bit-virtual.xml", 0); + break; + case MXL_RV64: + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, + riscv_gdb_set_virtual, + 1, "riscv-64bit-virtual.xml", 0); + break; + default: + g_assert_not_reached(); + } =20 gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_reg= s), --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636611077506221.31498552399876; Wed, 10 Nov 2021 22:11:17 -0800 (PST) Received: from localhost ([::1]:54900 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml3Io-0004zf-GP for importer@patchew.org; Thu, 11 Nov 2021 01:11:14 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48304) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml398-0003dp-5t; Thu, 11 Nov 2021 01:01:14 -0500 Received: from out28-169.mail.aliyun.com ([115.124.28.169]:36971) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml395-0003bg-7t; Thu, 11 Nov 2021 01:01:13 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr1-t1N_1636610466) by smtp.aliyun-inc.com(10.147.41.143); Thu, 11 Nov 2021 14:01:06 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.2787421|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0189165-0.00166077-0.979423; FP=2590121777638770114|2|2|6|0|-1|-1|-1; HT=ay29a033018047211; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr1-t1N_1636610466; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 06/20] target/riscv: Relax debug check for pm write Date: Thu, 11 Nov 2021 13:57:46 +0800 Message-Id: <20211111055800.42672-7-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.169; envelope-from=zhiwei_liu@c-sky.com; helo=out28-169.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636611080168100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/csr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9f41954894..74c0b788fd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1445,6 +1445,9 @@ static bool check_pm_current_disabled(CPURISCVState *= env, int csrno) int csr_priv =3D get_field(csrno, 0x300); int pm_current; =20 + if (env->debugger) { + return false; + } /* * If priv lvls differ that means we're accessing csr from higher priv= lvl, * so allow the access --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636610962063561.1239254877873; Wed, 10 Nov 2021 22:09:22 -0800 (PST) Received: from localhost ([::1]:51066 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml3Gx-0002Ph-MT for importer@patchew.org; Thu, 11 Nov 2021 01:09:19 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48348) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml39c-0004S3-WB; Thu, 11 Nov 2021 01:01:45 -0500 Received: from out28-221.mail.aliyun.com ([115.124.28.221]:45563) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml39Z-0003dO-PW; Thu, 11 Nov 2021 01:01:44 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr0rn9S_1636610497) by smtp.aliyun-inc.com(10.147.42.197); Thu, 11 Nov 2021 14:01:37 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.09586921|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.00303542-0.000152183-0.996812; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047209; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr0rn9S_1636610497; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 07/20] target/riscv: Adjust csr write mask with XLEN Date: Thu, 11 Nov 2021 13:57:47 +0800 Message-Id: <20211111055800.42672-8-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.221; envelope-from=zhiwei_liu@c-sky.com; helo=out28-221.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636610963399100001 Content-Type: text/plain; charset="utf-8" Write mask is representing the bits we care about. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/op_helper.c | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index e51dbc41c5..40c81421f2 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -486,7 +486,7 @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a) return do_csrw(ctx, a->csr, src); } =20 - TCGv mask =3D tcg_constant_tl(-1); + TCGv mask =3D tcg_constant_tl(get_xl(ctx) =3D=3D MXL_RV32 ? UINT32_MAX= : -1); return do_csrrw(ctx, a->rd, a->csr, src, mask); } =20 @@ -537,7 +537,7 @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi = *a) return do_csrw(ctx, a->csr, src); } =20 - TCGv mask =3D tcg_constant_tl(-1); + TCGv mask =3D tcg_constant_tl(get_xl(ctx) =3D=3D MXL_RV32 ? UINT32_MAX= : -1); return do_csrrw(ctx, a->rd, a->csr, src, mask); } =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 095d39671b..561e156bec 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -50,7 +50,8 @@ target_ulong helper_csrr(CPURISCVState *env, int csr) =20 void helper_csrw(CPURISCVState *env, int csr, target_ulong src) { - RISCVException ret =3D riscv_csrrw(env, csr, NULL, src, -1); + target_ulong mask =3D cpu_get_xl(env) =3D=3D MXL_RV32 ? UINT32_MAX : -= 1; + RISCVException ret =3D riscv_csrrw(env, csr, NULL, src, mask); =20 if (ret !=3D RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC()); --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636611221957332.9508107828707; Wed, 10 Nov 2021 22:13:41 -0800 (PST) Received: from localhost ([::1]:59612 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml3LA-0008EO-Se for importer@patchew.org; Thu, 11 Nov 2021 01:13:40 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48366) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3AH-00055X-Bz; Thu, 11 Nov 2021 01:02:28 -0500 Received: from out28-173.mail.aliyun.com ([115.124.28.173]:37744) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3A4-0003jR-5O; Thu, 11 Nov 2021 01:02:24 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr0wK1B_1636610527) by smtp.aliyun-inc.com(10.147.42.22); Thu, 11 Nov 2021 14:02:07 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436283|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0897631-0.00291113-0.907326; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047211; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr0wK1B_1636610527; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 08/20] target/riscv: Create current pm fields in env Date: Thu, 11 Nov 2021 13:57:48 +0800 Message-Id: <20211111055800.42672-9-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.173; envelope-from=zhiwei_liu@c-sky.com; helo=out28-173.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636611224183100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 4 ++++ target/riscv/cpu_helper.c | 43 +++++++++++++++++++++++++++++++++++++++ target/riscv/csr.c | 19 +++++++++++++++++ target/riscv/machine.c | 10 +++++++++ 5 files changed, 77 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0d2d175fa2..886388f066 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -378,6 +378,7 @@ static void riscv_cpu_reset(DeviceState *dev) #ifndef CONFIG_USER_ONLY env->misa_mxl =3D env->misa_mxl_max; env->priv =3D PRV_M; + riscv_cpu_update_mask(env); env->mstatus &=3D ~(MSTATUS_MIE | MSTATUS_MPRV); if (env->misa_mxl > MXL_RV32) { /* diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8befff0166..fa5a6ba1c8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -250,6 +250,8 @@ struct CPURISCVState { target_ulong upmmask; target_ulong upmbase; #endif + target_ulong cur_pmmask; + target_ulong cur_pmbase; =20 float_status fp_status; =20 @@ -441,6 +443,8 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, ta= rget_ulong vtype) void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags); =20 +void riscv_cpu_update_mask(CPURISCVState *env); + RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask= ); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 79aba9c880..8320f56d9f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -133,6 +133,48 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_u= long *pc, *pflags =3D flags; } =20 +void riscv_cpu_update_mask(CPURISCVState *env) +{ + target_ulong mask =3D -1, base =3D 0; + /* + * TODO: Current RVJ spec does not specify + * how the extension interacts with XLEN. + */ +#ifndef CONFIG_USER_ONLY + if (riscv_has_ext(env, RVJ)) { + switch (env->priv) { + case PRV_M: + if (env->mmte & M_PM_ENABLE) { + mask =3D env->mpmmask; + base =3D env->mpmbase; + } + break; + case PRV_S: + if (env->mmte & S_PM_ENABLE) { + mask =3D env->spmmask; + base =3D env->spmbase; + } + break; + case PRV_U: + if (env->mmte & U_PM_ENABLE) { + mask =3D env->upmmask; + base =3D env->upmbase; + } + break; + default: + g_assert_not_reached(); + } + } +#endif + if (cpu_get_xl(env) =3D=3D MXL_RV32) { + env->cur_pmmask =3D mask & UINT32_MAX; + env->cur_pmbase =3D base & UINT32_MAX; + } else { + env->cur_pmmask =3D mask; + env->cur_pmbase =3D base; + } +} + #ifndef CONFIG_USER_ONLY static int riscv_cpu_local_irq_pending(CPURISCVState *env) { @@ -331,6 +373,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulon= g newpriv) } /* tlb_flush is unnecessary as mode is contained in mmu_idx */ env->priv =3D newpriv; + riscv_cpu_update_mask(env); =20 /* * Clear the load reservation - otherwise a reservation placed in one diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 74c0b788fd..6bb2d09519 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1496,6 +1496,7 @@ static RISCVException write_mmte(CPURISCVState *env, = int csrno, /* hardwiring pm.instruction bit to 0, since it's not supported yet */ wpri_val &=3D ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); env->mmte =3D wpri_val | PM_EXT_DIRTY; + riscv_cpu_update_mask(env); =20 /* Set XS and SD bits, since PM CSRs are dirty */ mstatus =3D env->mstatus | MSTATUS_XS; @@ -1571,6 +1572,9 @@ static RISCVException write_mpmmask(CPURISCVState *en= v, int csrno, uint64_t mstatus; =20 env->mpmmask =3D val; + if ((env->priv =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE)) { + env->cur_pmmask =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1596,6 +1600,9 @@ static RISCVException write_spmmask(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } env->spmmask =3D val; + if ((env->priv =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE)) { + env->cur_pmmask =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1621,6 +1628,9 @@ static RISCVException write_upmmask(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } env->upmmask =3D val; + if ((env->priv =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE)) { + env->cur_pmmask =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1642,6 +1652,9 @@ static RISCVException write_mpmbase(CPURISCVState *en= v, int csrno, uint64_t mstatus; =20 env->mpmbase =3D val; + if ((env->priv =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE)) { + env->cur_pmbase =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1667,6 +1680,9 @@ static RISCVException write_spmbase(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } env->spmbase =3D val; + if ((env->priv =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE)) { + env->cur_pmbase =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1692,6 +1708,9 @@ static RISCVException write_upmbase(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } env->upmbase =3D val; + if ((env->priv =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE)) { + env->cur_pmbase =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 7b4c739564..19e982d3f0 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -164,10 +164,20 @@ static const VMStateDescription vmstate_hyper =3D { } }; =20 +static int riscv_cpu_post_load(void *opaque, int version_id) +{ + RISCVCPU *cpu =3D opaque; + CPURISCVState *env =3D &cpu->env; + + riscv_cpu_update_mask(env); + return 0; +} + const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", .version_id =3D 3, .minimum_version_id =3D 3, + .post_load =3D riscv_cpu_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636610825099822.288228874809; Wed, 10 Nov 2021 22:07:05 -0800 (PST) Received: from localhost ([::1]:47294 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml3El-0008Ct-Tc for importer@patchew.org; Thu, 11 Nov 2021 01:07:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48398) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3Aa-0005L0-Uv; Thu, 11 Nov 2021 01:02:45 -0500 Received: from out28-97.mail.aliyun.com ([115.124.28.97]:45475) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3AY-0003lM-IQ; Thu, 11 Nov 2021 01:02:44 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr1vm3P_1636610558) by smtp.aliyun-inc.com(10.147.40.7); Thu, 11 Nov 2021 14:02:38 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07453424|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0061735-0.00216247-0.991664; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047192; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr1vm3P_1636610558; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base] Date: Thu, 11 Nov 2021 13:57:49 +0800 Message-Id: <20211111055800.42672-10-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.97; envelope-from=zhiwei_liu@c-sky.com; helo=out28-97.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636610826166100003 Content-Type: text/plain; charset="utf-8" Replace the array of pm_mask/pm_base with scalar variables. Remove the cached array value in DisasContext. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/translate.c | 32 ++++++++------------------------ 1 file changed, 8 insertions(+), 24 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a6a73ced9e..6cb74c6355 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -37,8 +37,8 @@ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions= */ static TCGv load_res; static TCGv load_val; /* globals for PM CSRs */ -static TCGv pm_mask[4]; -static TCGv pm_base[4]; +static TCGv pm_mask; +static TCGv pm_base; =20 #include "exec/gen-icount.h" =20 @@ -88,8 +88,6 @@ typedef struct DisasContext { TCGv temp[4]; /* PointerMasking extension */ bool pm_enabled; - TCGv pm_mask; - TCGv pm_base; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -297,8 +295,8 @@ static TCGv gen_pm_adjust_address(DisasContext *s, TCGv= src) return src; } else { temp =3D temp_new(s); - tcg_gen_andc_tl(temp, src, s->pm_mask); - tcg_gen_or_tl(temp, temp, s->pm_base); + tcg_gen_andc_tl(temp, src, pm_mask); + tcg_gen_or_tl(temp, temp, pm_base); return temp; } } @@ -647,10 +645,6 @@ static void riscv_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->ntemp =3D 0; memset(ctx->temp, 0, sizeof(ctx->temp)); ctx->pm_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); - int priv =3D tb_flags & TB_FLAGS_PRIV_MMU_MASK; - ctx->pm_mask =3D pm_mask[priv]; - ctx->pm_base =3D pm_base[priv]; - ctx->zero =3D tcg_constant_tl(0); } =20 @@ -763,19 +757,9 @@ void riscv_translate_init(void) "load_res"); load_val =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_= val), "load_val"); -#ifndef CONFIG_USER_ONLY /* Assign PM CSRs to tcg globals */ - pm_mask[PRV_U] =3D - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmma= sk"); - pm_base[PRV_U] =3D - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmba= se"); - pm_mask[PRV_S] =3D - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmma= sk"); - pm_base[PRV_S] =3D - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmba= se"); - pm_mask[PRV_M] =3D - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmma= sk"); - pm_base[PRV_M] =3D - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmba= se"); -#endif + pm_mask =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pm= mask), + "pmmask"); + pm_base =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pm= base), + "pmbase"); } --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636611421845166.23171685776413; Wed, 10 Nov 2021 22:17:01 -0800 (PST) Received: from localhost ([::1]:38914 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml3OO-0004yH-Qy for importer@patchew.org; Thu, 11 Nov 2021 01:17:00 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48460) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3BB-0005f8-P7; Thu, 11 Nov 2021 01:03:21 -0500 Received: from out28-98.mail.aliyun.com ([115.124.28.98]:42063) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3B6-0003mM-Tx; Thu, 11 Nov 2021 01:03:21 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr1SVUN_1636610588) by smtp.aliyun-inc.com(10.147.44.145); Thu, 11 Nov 2021 14:03:08 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0116271-0.000182734-0.98819; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047206; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr1SVUN_1636610588; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 10/20] target/riscv: Calculate address according to XLEN Date: Thu, 11 Nov 2021 13:57:50 +0800 Message-Id: <20211111055800.42672-11-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.98; envelope-from=zhiwei_liu@c-sky.com; helo=out28-98.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636611423126100001 Content-Type: text/plain; charset="utf-8" Define one common function to compute a canonical address from a register plus offset. Merge gen_pm_adjust_address into this function. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rva.c.inc | 9 +++------ target/riscv/insn_trans/trans_rvd.c.inc | 19 ++--------------- target/riscv/insn_trans/trans_rvf.c.inc | 19 ++--------------- target/riscv/insn_trans/trans_rvi.c.inc | 18 ++--------------- target/riscv/translate.c | 27 ++++++++++++------------- 5 files changed, 22 insertions(+), 70 deletions(-) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index 40fe132b04..1f64b8d332 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -20,12 +20,11 @@ =20 static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) { - TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); + TCGv src1 =3D get_address(ctx, a->rs1, 0); =20 if (a->rl) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - src1 =3D gen_pm_adjust_address(ctx, src1); tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop); if (a->aq) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -44,8 +43,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemO= p mop) TCGLabel *l1 =3D gen_new_label(); TCGLabel *l2 =3D gen_new_label(); =20 - src1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); - src1 =3D gen_pm_adjust_address(ctx, src1); + src1 =3D get_address(ctx, a->rs1, 0); tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); =20 /* @@ -83,10 +81,9 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, MemOp mop) { TCGv dest =3D dest_gpr(ctx, a->rd); - TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src1 =3D get_address(ctx, a->rs1, 0); TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 - src1 =3D gen_pm_adjust_address(ctx, src1); func(dest, src1, src2, ctx->mem_idx, mop); =20 gen_set_gpr(ctx, a->rd, dest); diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 64fb0046f7..88a491375c 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -25,14 +25,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - + addr =3D get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEQ); =20 mark_fs_dirty(ctx); @@ -46,16 +39,8 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - + addr =3D get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEQ); - return true; } =20 diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index b5459249c4..0aac87f7db 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -31,14 +31,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - + addr =3D get_address(ctx, a->rs1, a->imm); dest =3D cpu_fpr[a->rd]; tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL); gen_nanbox_s(dest, dest); @@ -54,16 +47,8 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - if (a->imm) { - TCGv temp =3D tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - + addr =3D get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL); - return true; } =20 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 40c81421f2..cb73a2f1ee 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -137,14 +137,7 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) { TCGv dest =3D dest_gpr(ctx, a->rd); - TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); + TCGv addr =3D get_address(ctx, a->rs1, a->imm); =20 tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop); gen_set_gpr(ctx, a->rd, dest); @@ -178,16 +171,9 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a) =20 static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) { - TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv addr =3D get_address(ctx, a->rs1, a->imm); TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); return true; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6cb74c6355..fd75f7c4bc 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -284,21 +284,20 @@ static void gen_jal(DisasContext *ctx, int rd, target= _ulong imm) ctx->base.is_jmp =3D DISAS_NORETURN; } =20 -/* - * Generates address adjustment for PointerMasking - */ -static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src) -{ - TCGv temp; - if (!s->pm_enabled) { - /* Load unmodified address */ - return src; - } else { - temp =3D temp_new(s); - tcg_gen_andc_tl(temp, src, pm_mask); - tcg_gen_or_tl(temp, temp, pm_base); - return temp; +/* Compute a canonical address from a register plus offset. */ +static TCGv get_address(DisasContext *ctx, int rs1, int imm) +{ + TCGv addr =3D temp_new(ctx); + TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); + + tcg_gen_addi_tl(addr, src1, imm); + if (ctx->pm_enabled) { + tcg_gen_and_tl(addr, addr, pm_mask); + tcg_gen_or_tl(addr, addr, pm_base); + } else if (get_xl(ctx) =3D=3D MXL_RV32) { + tcg_gen_ext32u_tl(addr, addr); } + return addr; } =20 #ifndef CONFIG_USER_ONLY --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636611105554511.47087583401594; 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MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr1ZjwY_1636610619; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 11/20] target/riscv: Split pm_enabled into mask and base Date: Thu, 11 Nov 2021 13:57:51 +0800 Message-Id: <20211111055800.42672-12-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.218; envelope-from=zhiwei_liu@c-sky.com; helo=out28-218.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636611107915100003 Content-Type: text/plain; charset="utf-8" Use cached cur_pmmask and cur_pmbase to infer the current PM mode. This may decrease the TCG IR by one when pm_enabled is true and pm_base_enabled is false. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 3 ++- target/riscv/cpu_helper.c | 25 +++++++------------------ target/riscv/translate.c | 12 ++++++++---- 3 files changed, 17 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fa5a6ba1c8..9fba876e08 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -411,7 +411,8 @@ FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ FIELD(TB_FLAGS, XL, 13, 2) /* If PointerMasking should be applied */ -FIELD(TB_FLAGS, PM_ENABLED, 15, 1) +FIELD(TB_FLAGS, PM_MASK_ENABLED, 15, 1) +FIELD(TB_FLAGS, PM_BASE_ENABLED, 16, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8320f56d9f..a40ed6d748 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -108,26 +108,15 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_= ulong *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, get_field(env->mstatus_hs, MSTATUS_FS)); } - if (riscv_has_ext(env, RVJ)) { - int priv =3D flags & TB_FLAGS_PRIV_MMU_MASK; - bool pm_enabled =3D false; - switch (priv) { - case PRV_U: - pm_enabled =3D env->mmte & U_PM_ENABLE; - break; - case PRV_S: - pm_enabled =3D env->mmte & S_PM_ENABLE; - break; - case PRV_M: - pm_enabled =3D env->mmte & M_PM_ENABLE; - break; - default: - g_assert_not_reached(); - } - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled); - } #endif =20 + if (env->cur_pmmask < (xl =3D=3D MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); + } + if (env->cur_pmbase !=3D 0) { + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); + } + flags =3D FIELD_DP32(flags, TB_FLAGS, XL, xl); =20 *pflags =3D flags; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index fd75f7c4bc..10c16e759d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -87,7 +87,8 @@ typedef struct DisasContext { /* Space for 3 operands plus 1 extra for address computation. */ TCGv temp[4]; /* PointerMasking extension */ - bool pm_enabled; + bool pm_mask_enabled; + bool pm_base_enabled; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -291,12 +292,14 @@ static TCGv get_address(DisasContext *ctx, int rs1, i= nt imm) TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_addi_tl(addr, src1, imm); - if (ctx->pm_enabled) { + if (ctx->pm_mask_enabled) { tcg_gen_and_tl(addr, addr, pm_mask); - tcg_gen_or_tl(addr, addr, pm_base); } else if (get_xl(ctx) =3D=3D MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } + if (ctx->pm_base_enabled) { + tcg_gen_or_tl(addr, addr, pm_base); + } return addr; } =20 @@ -643,7 +646,8 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->cs =3D cs; ctx->ntemp =3D 0; memset(ctx->temp, 0, sizeof(ctx->temp)); - ctx->pm_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); + ctx->pm_mask_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLE= D); + ctx->pm_base_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLE= D); ctx->zero =3D tcg_constant_tl(0); } =20 --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163661148047418.51907614498191; Wed, 10 Nov 2021 22:18:00 -0800 (PST) Received: from localhost ([::1]:41280 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml3PL-0006ay-4c for importer@patchew.org; Thu, 11 Nov 2021 01:17:59 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48572) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3C6-0006mi-45; Thu, 11 Nov 2021 01:04:18 -0500 Received: from out28-1.mail.aliyun.com ([115.124.28.1]:51600) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3C3-0003sa-Lz; Thu, 11 Nov 2021 01:04:17 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr22uTb_1636610649) by smtp.aliyun-inc.com(10.147.42.16); Thu, 11 Nov 2021 14:04:10 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07437331|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0599752-0.000428917-0.939596; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047203; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr22uTb_1636610649; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 12/20] target/riscv: Split out the vill from vtype Date: Thu, 11 Nov 2021 13:57:52 +0800 Message-Id: <20211111055800.42672-13-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.1; envelope-from=zhiwei_liu@c-sky.com; helo=out28-1.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636611482627100001 Content-Type: text/plain; charset="utf-8" We need not specially process vtype when XLEN changes. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 3 +-- target/riscv/csr.c | 13 ++++++++++++- target/riscv/machine.c | 1 + target/riscv/vector_helper.c | 3 ++- 5 files changed, 17 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9fba876e08..52ce670cbe 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -119,6 +119,7 @@ struct CPURISCVState { target_ulong vl; target_ulong vstart; target_ulong vtype; + bool vill; =20 target_ulong pc; target_ulong load_res; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index a40ed6d748..9b9dc83ab9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -78,8 +78,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, if (riscv_has_ext(env, RVV)) { uint32_t vlmax =3D vext_get_vlmax(env_archcpu(env), env->vtype); bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl); - flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, - FIELD_EX64(env->vtype, VTYPE, VILL)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, FIELD_EX64(env->vtype, VTYPE, VSEW)); flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6bb2d09519..8f8f170768 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -286,7 +286,18 @@ static RISCVException write_fcsr(CPURISCVState *env, i= nt csrno, static RISCVException read_vtype(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->vtype; + uint64_t vill; + switch (cpu_get_xl(env)) { + case MXL_RV32: + vill =3D (uint32_t)env->vill << 31; + break; + case MXL_RV64: + vill =3D (uint64_t)env->vill << 63; + break; + default: + g_assert_not_reached(); + } + *val =3D (target_ulong)vill | env->vtype; return RISCV_EXCP_NONE; } =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 19e982d3f0..2161bc80ca 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -104,6 +104,7 @@ static const VMStateDescription vmstate_vector =3D { VMSTATE_UINTTL(env.vl, RISCVCPU), VMSTATE_UINTTL(env.vstart, RISCVCPU), VMSTATE_UINTTL(env.vtype, RISCVCPU), + VMSTATE_BOOL(env.vill, RISCVCPU), VMSTATE_END_OF_LIST() } }; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 12c31aa4b4..b02ccefa4d 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -38,7 +38,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ul= ong s1, =20 if ((sew > cpu->cfg.elen) || vill || (ediv !=3D 0) || (reserved !=3D 0= )) { /* only set vill bit. */ - env->vtype =3D FIELD_DP64(0, VTYPE, VILL, 1); + env->vill =3D 1; + env->vtype =3D 0; env->vl =3D 0; env->vstart =3D 0; return 0; --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163661136763258.64648786943417; Wed, 10 Nov 2021 22:16:07 -0800 (PST) Received: from localhost ([::1]:36636 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml3NW-0003Io-IA for importer@patchew.org; Thu, 11 Nov 2021 01:16:06 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48654) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3Cb-0007M7-QH; Thu, 11 Nov 2021 01:04:51 -0500 Received: from out28-50.mail.aliyun.com ([115.124.28.50]:58238) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3Ca-0003vH-0G; Thu, 11 Nov 2021 01:04:49 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr1vOzq_1636610680) by smtp.aliyun-inc.com(10.147.44.118); Thu, 11 Nov 2021 14:04:40 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1031801|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.102492-0.000803447-0.896705; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047193; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr1vOzq_1636610680; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE Date: Thu, 11 Nov 2021 13:57:53 +0800 Message-Id: <20211111055800.42672-14-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.50; envelope-from=zhiwei_liu@c-sky.com; helo=out28-50.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636611368964100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 52ce670cbe..b48c7c346c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -105,7 +105,7 @@ typedef struct CPURISCVState CPURISCVState; FIELD(VTYPE, VLMUL, 0, 2) FIELD(VTYPE, VSEW, 2, 3) FIELD(VTYPE, VEDIV, 5, 2) -FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) +FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8) FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) =20 struct CPURISCVState { --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636611569601711.4133714821581; Wed, 10 Nov 2021 22:19:29 -0800 (PST) Received: from localhost ([::1]:45442 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml3Qm-000116-JF for importer@patchew.org; Thu, 11 Nov 2021 01:19:28 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48776) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3D6-0008Ar-5r; Thu, 11 Nov 2021 01:05:20 -0500 Received: from out28-75.mail.aliyun.com ([115.124.28.75]:52357) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3D3-0003yH-9V; Thu, 11 Nov 2021 01:05:19 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr1vPH6_1636610711) by smtp.aliyun-inc.com(10.147.44.118); Thu, 11 Nov 2021 14:05:11 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07520969|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0341477-0.00223256-0.96362; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047198; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr1vPH6_1636610711; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN Date: Thu, 11 Nov 2021 13:57:54 +0800 Message-Id: <20211111055800.42672-15-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.75; envelope-from=zhiwei_liu@c-sky.com; helo=out28-75.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636611570499100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c | 8 +++++--- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c5098380dd..a67965efe5 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -82,7 +82,7 @@ DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl) #endif =20 /* Vector functions */ -DEF_HELPER_3(vsetvl, tl, env, tl, tl) +DEF_HELPER_4(vsetvl, tl, env, tl, tl, tl) DEF_HELPER_5(vlb_v_b, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlb_v_b_mask, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlb_v_h, void, ptr, ptr, tl, env, i32) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 17ee3babef..f5aabd5263 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -37,7 +37,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) } else { s1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); } - gen_helper_vsetvl(dst, cpu_env, s1, s2); + gen_helper_vsetvl(dst, cpu_env, s1, s2, tcg_constant_tl(get_xlen(ctx))= ); gen_set_gpr(ctx, a->rd, dst); =20 tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); @@ -64,7 +64,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli = *a) } else { s1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); } - gen_helper_vsetvl(dst, cpu_env, s1, s2); + gen_helper_vsetvl(dst, cpu_env, s1, s2, tcg_constant_tl(get_xlen(ctx))= ); gen_set_gpr(ctx, a->rd, dst); =20 gen_goto_tb(ctx, 0, ctx->pc_succ_insn); diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index b02ccefa4d..1a7ee46d46 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -27,14 +27,16 @@ #include =20 target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, - target_ulong s2) + target_ulong s2, target_ulong xlen) { int vlmax, vl; RISCVCPU *cpu =3D env_archcpu(env); uint16_t sew =3D 8 << FIELD_EX64(s2, VTYPE, VSEW); uint8_t ediv =3D FIELD_EX64(s2, VTYPE, VEDIV); - bool vill =3D FIELD_EX64(s2, VTYPE, VILL); - target_ulong reserved =3D FIELD_EX64(s2, VTYPE, RESERVED); + bool vill =3D (s2 >> (xlen - 1)) & 0x1; + target_ulong reserved =3D s2 & + MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, + xlen - 1 - R_VTYPE_RESERVED_SH= IFT); =20 if ((sew > cpu->cfg.elen) || vill || (ediv !=3D 0) || (reserved !=3D 0= )) { /* only set vill bit. */ --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636611631349463.8706323141971; Wed, 10 Nov 2021 22:20:31 -0800 (PST) Received: from localhost ([::1]:50034 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml3Rm-00046z-7p for importer@patchew.org; Thu, 11 Nov 2021 01:20:30 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48960) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3Dq-0000fF-DP; Thu, 11 Nov 2021 01:06:06 -0500 Received: from out28-218.mail.aliyun.com ([115.124.28.218]:36141) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3Da-00045Y-Jr; Thu, 11 Nov 2021 01:06:06 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr1RmV._1636610741) by smtp.aliyun-inc.com(10.147.41.178); Thu, 11 Nov 2021 14:05:42 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1839589|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0861623-0.000514328-0.913323; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047206; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr1RmV._1636610741; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE Date: Thu, 11 Nov 2021 13:57:55 +0800 Message-Id: <20211111055800.42672-16-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.218; envelope-from=zhiwei_liu@c-sky.com; helo=out28-218.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636611632901100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Acked-by: Richard Henderson --- target/riscv/cpu.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b48c7c346c..5f35217f7d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -106,7 +106,6 @@ FIELD(VTYPE, VLMUL, 0, 2) FIELD(VTYPE, VSEW, 2, 3) FIELD(VTYPE, VEDIV, 5, 2) FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8) -FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) =20 struct CPURISCVState { target_ulong gpr[32]; --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636611632589867.2139657895667; Wed, 10 Nov 2021 22:20:32 -0800 (PST) Received: from localhost ([::1]:50066 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml3Rn-00048X-G8 for importer@patchew.org; Thu, 11 Nov 2021 01:20:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49178) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3EF-0000ns-1E; Thu, 11 Nov 2021 01:06:33 -0500 Received: from out28-195.mail.aliyun.com ([115.124.28.195]:44523) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3E9-00049s-7R; Thu, 11 Nov 2021 01:06:30 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr1f42V_1636610772) by smtp.aliyun-inc.com(10.147.40.2); Thu, 11 Nov 2021 14:06:12 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.2425905|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0184311-7.11308e-05-0.981498; FP=3094954652002229690|2|2|6|0|-1|-1|-1; HT=ay29a033018047201; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr1f42V_1636610772; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 16/20] target/riscv: Ajdust vector atomic check with XLEN Date: Thu, 11 Nov 2021 13:57:56 +0800 Message-Id: <20211111055800.42672-17-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.195; envelope-from=zhiwei_liu@c-sky.com; helo=out28-195.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636611633028100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index f5aabd5263..41c7c88904 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -739,7 +739,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a) (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) && vext_check_reg(s, a->rd, false) && vext_check_reg(s, a->rs2, false) && - ((1 << s->sew) <=3D sizeof(target_ulong)) && + /* TODO: RV128 could allow 128-bit atomics */ + ((1 << s->sew) <=3D (get_xl(s) =3D=3D MXL_RV32 ? 4 : 8)) && ((1 << s->sew) >=3D 4)); } =20 --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636611731310601.4061000486396; Wed, 10 Nov 2021 22:22:11 -0800 (PST) Received: from localhost ([::1]:54230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml3TO-00072l-4W for importer@patchew.org; Thu, 11 Nov 2021 01:22:10 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49272) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3Ey-0001ZS-Fx; Thu, 11 Nov 2021 01:07:18 -0500 Received: from out28-195.mail.aliyun.com ([115.124.28.195]:33131) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3Er-0004Hk-2N; Thu, 11 Nov 2021 01:07:16 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr1Zlm._1636610803) by smtp.aliyun-inc.com(10.147.43.95); Thu, 11 Nov 2021 14:06:43 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1766042|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0508009-0.000453744-0.948745; FP=8779059357981805943|2|2|6|0|-1|-1|-1; HT=ay29a033018047208; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr1Zlm._1636610803; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 17/20] target/riscv: Fix check range for first fault only Date: Thu, 11 Nov 2021 13:57:57 +0800 Message-Id: <20211111055800.42672-18-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.195; envelope-from=zhiwei_liu@c-sky.com; helo=out28-195.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636611732107100001 Content-Type: text/plain; charset="utf-8" Only check the range that has passed the address translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 1a7ee46d46..ee58187d26 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -630,12 +630,12 @@ vext_ldff(void *vd, void *v0, target_ulong base, cpu_mmu_index(env, false)); if (host) { #ifdef CONFIG_USER_ONLY - if (page_check_range(addr, nf * msz, PAGE_READ) < 0) { + if (page_check_range(addr, offset, PAGE_READ) < 0) { vl =3D i; goto ProbeSuccess; } #else - probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD); + probe_pages(env, addr, offset, ra, MMU_DATA_LOAD); #endif } else { vl =3D i; --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636611356966240.6115493095208; Wed, 10 Nov 2021 22:15:56 -0800 (PST) Received: from localhost ([::1]:35850 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml3NL-0002mJ-UH for importer@patchew.org; Thu, 11 Nov 2021 01:15:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49312) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3FE-0001mA-UO; Thu, 11 Nov 2021 01:07:32 -0500 Received: from out28-124.mail.aliyun.com ([115.124.28.124]:53097) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3F7-0004J8-Mo; Thu, 11 Nov 2021 01:07:32 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr2-MGQ_1636610834) by smtp.aliyun-inc.com(10.147.42.253); Thu, 11 Nov 2021 14:07:14 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07445978|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.0042601-0.000557924-0.995182; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047209; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr2-MGQ_1636610834; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 18/20] target/riscv: Adjust vector address with mask Date: Thu, 11 Nov 2021 13:57:58 +0800 Message-Id: <20211111055800.42672-19-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.124; envelope-from=zhiwei_liu@c-sky.com; helo=out28-124.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636611358253100001 Content-Type: text/plain; charset="utf-8" The mask comes from the pointer masking extension, or the max value corresponding to XLEN bits. Signed-off-by: LIU Zhiwei --- target/riscv/vector_helper.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index ee58187d26..2667cae63b 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -115,6 +115,11 @@ static inline uint32_t vext_maxsz(uint32_t desc) return simd_maxsz(desc) << vext_lmul(desc); } =20 +static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong ad= dr) +{ + return (addr & env->cur_pmmask) | env->cur_pmbase; +} + /* * This function checks watchpoint before real load operation. * @@ -132,12 +137,12 @@ static void probe_pages(CPURISCVState *env, target_ul= ong addr, target_ulong pagelen =3D -(addr | TARGET_PAGE_MASK); target_ulong curlen =3D MIN(pagelen, len); =20 - probe_access(env, addr, curlen, access_type, + probe_access(env, adjust_addr(env, addr), curlen, access_type, cpu_mmu_index(env, false), ra); if (len > curlen) { addr +=3D curlen; curlen =3D len - curlen; - probe_access(env, addr, curlen, access_type, + probe_access(env, adjust_addr(env, addr), curlen, access_type, cpu_mmu_index(env, false), ra); } } @@ -298,7 +303,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, } while (k < nf) { target_ulong addr =3D base + stride * i + k * msz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra); k++; } } @@ -391,7 +396,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState= *env, uint32_t desc, k =3D 0; while (k < nf) { target_ulong addr =3D base + (i * nf + k) * msz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra); k++; } } @@ -528,7 +533,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, } while (k < nf) { abi_ptr addr =3D get_index_addr(base, i, vs2) + k * msz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra); k++; } } @@ -618,7 +623,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, if (!vm && !vext_elem_mask(v0, mlen, i)) { continue; } - addr =3D base + nf * i * msz; + addr =3D adjust_addr(env, base + nf * i * msz); if (i =3D=3D 0) { probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD); } else { @@ -645,7 +650,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, break; } remain -=3D offset; - addr +=3D offset; + addr =3D adjust_addr(env, addr + offset); } } } @@ -661,7 +666,7 @@ ProbeSuccess: } while (k < nf) { target_ulong addr =3D base + (i * nf + k) * msz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra); k++; } } @@ -800,7 +805,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong bas= e, continue; } addr =3D get_index_addr(base, i, vs2); - noatomic_op(vs3, addr, wd, i, env, ra); + noatomic_op(vs3, adjust_addr(env, addr), wd, i, env, ra); } clear_elem(vs3, env->vl, env->vl * esz, vlmax * esz); } --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16366119083384.2002886083947715; Wed, 10 Nov 2021 22:25:08 -0800 (PST) Received: from localhost ([::1]:58806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml3WF-0001lc-2N for importer@patchew.org; Thu, 11 Nov 2021 01:25:07 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49362) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3Ff-0002Mv-2v; Thu, 11 Nov 2021 01:08:00 -0500 Received: from out28-121.mail.aliyun.com ([115.124.28.121]:54592) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3Fa-0004LU-V5; Thu, 11 Nov 2021 01:07:58 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr1vQny_1636610864) by smtp.aliyun-inc.com(10.147.44.118); Thu, 11 Nov 2021 14:07:45 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07609346|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.411451-0.000991827-0.587557; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047211; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr1vQny_1636610864; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN Date: Thu, 11 Nov 2021 13:57:59 +0800 Message-Id: <20211111055800.42672-20-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.121; envelope-from=zhiwei_liu@c-sky.com; helo=out28-121.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636611908916100001 Content-Type: text/plain; charset="utf-8" When sew <=3D 32bits, not need to extend scalar reg. When sew > 32bits, if xlen is less that sew, we should sign extend the scalar register, except explicitly specified by the spec. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvv.c.inc | 44 ++++++++++++++++++------- 1 file changed, 32 insertions(+), 12 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 41c7c88904..7301992f82 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -833,7 +833,7 @@ typedef void gen_helper_opivx(TCGv_ptr, TCGv_ptr, TCGv,= TCGv_ptr, TCGv_env, TCGv_i32); =20 static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t = vm, - gen_helper_opivx *fn, DisasContext *s) + gen_helper_opivx *fn, DisasContext *s, DisasExtend= ext) { TCGv_ptr dest, src2, mask; TCGv src1; @@ -846,7 +846,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint= 32_t vs2, uint32_t vm, dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); - src1 =3D get_gpr(s, rs1, EXT_NONE); + src1 =3D get_gpr(s, rs1, ext); =20 data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, vm); @@ -895,7 +895,7 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn= *gvec_fn, tcg_temp_free_i64(src1); return true; } - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, EXT_SIGN); } =20 /* OPIVX with GVEC IR */ @@ -1128,7 +1128,7 @@ static bool do_opivx_widen(DisasContext *s, arg_rmrr = *a, gen_helper_opivx *fn) { if (opivx_widen_check(s, a)) { - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, EXT_SIGN); } return false; } @@ -1213,7 +1213,7 @@ static bool do_opiwx_widen(DisasContext *s, arg_rmrr = *a, gen_helper_opivx *fn) { if (opiwx_widen_check(s, a)) { - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, EXT_SIGN); } return false; } @@ -1312,7 +1312,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ }; \ \ - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\ + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \ + fns[s->sew], s, EXT_SIGN); \ } \ return false; \ } @@ -1386,7 +1387,7 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVe= cGen2sFn32 *gvec_fn, tcg_temp_free_i32(src1); return true; } - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, EXT_SIGN); } =20 #define GEN_OPIVX_GVEC_SHIFT_TRANS(NAME, SUF) \ @@ -1472,7 +1473,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_h, \ gen_helper_##NAME##_w, \ }; \ - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\ + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \ + fns[s->sew], s, EXT_SIGN); \ } \ return false; \ } @@ -2670,6 +2672,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_= x *a) /* This instruction ignores LMUL and vector register groups */ int maxsz =3D s->vlen >> 3; TCGv_i64 t1; + TCGv src1 =3D get_gpr(s, a->rs1, EXT_ZERO); TCGLabel *over =3D gen_new_label(); =20 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); @@ -2679,7 +2682,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_= x *a) } =20 t1 =3D tcg_temp_new_i64(); - tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]); + tcg_gen_extu_tl_i64(t1, src1); vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); done: @@ -2748,12 +2751,28 @@ static bool slideup_check(DisasContext *s, arg_rmrr= *a) (a->rd !=3D a->rs2)); } =20 +/* OPIVXU without GVEC IR */ +#define GEN_OPIVXU_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + static gen_helper_opivx * const fns[4] =3D { = \ + gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ + }; \ + \ + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \ + fns[s->sew], s, EXT_ZERO); \ + } \ + return false; \ +} + GEN_OPIVX_TRANS(vslideup_vx, slideup_check) -GEN_OPIVX_TRANS(vslide1up_vx, slideup_check) +GEN_OPIVXU_TRANS(vslide1up_vx, slideup_check) GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check) =20 GEN_OPIVX_TRANS(vslidedown_vx, opivx_check) -GEN_OPIVX_TRANS(vslide1down_vx, opivx_check) +GEN_OPIVXU_TRANS(vslide1down_vx, opivx_check) GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check) =20 /* Vector Register Gather Instruction */ @@ -2803,7 +2822,8 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rm= rr *a) gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h, gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d }; - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s); + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, + fns[s->sew], s, EXT_SIGN); } return true; } --=20 2.25.1 From nobody Mon Feb 9 14:27:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636611830766132.72751160148835; Wed, 10 Nov 2021 22:23:50 -0800 (PST) Received: from localhost ([::1]:56870 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ml3Uz-0000Si-Ge for importer@patchew.org; Thu, 11 Nov 2021 01:23:49 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49462) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3G6-0002ti-Kt; Thu, 11 Nov 2021 01:08:26 -0500 Received: from out28-101.mail.aliyun.com ([115.124.28.101]:46462) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ml3G3-0004NU-P4; Thu, 11 Nov 2021 01:08:26 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Lr211Ee_1636610895) by smtp.aliyun-inc.com(10.147.42.241); Thu, 11 Nov 2021 14:08:15 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.4542212|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0476513-0.00068219-0.951667; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047192; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.Lr211Ee_1636610895; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 20/20] target/riscv: Enable uxl field write Date: Thu, 11 Nov 2021 13:58:00 +0800 Message-Id: <20211111055800.42672-21-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com> References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.101; envelope-from=zhiwei_liu@c-sky.com; helo=out28-101.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636611832197100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei --- target/riscv/csr.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8f8f170768..43eaa6c710 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -553,15 +553,14 @@ static RISCVException write_mstatus(CPURISCVState *en= v, int csrno, * RV32: MPV and GVA are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. */ - mask |=3D MSTATUS_MPV | MSTATUS_GVA; + mask |=3D MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL; } =20 mstatus =3D (mstatus & ~mask) | (val & mask); =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { - /* SXL and UXL fields are for now read only */ + /* SXL fields are for now read only */ mstatus =3D set_field(mstatus, MSTATUS64_SXL, MXL_RV64); - mstatus =3D set_field(mstatus, MSTATUS64_UXL, MXL_RV64); } env->mstatus =3D mstatus; =20 --=20 2.25.1