From nobody Tue Feb 10 08:04:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636528403377581.2120326993688; Tue, 9 Nov 2021 23:13:23 -0800 (PST) Received: from localhost ([::1]:60310 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkhnO-0005aK-JZ for importer@patchew.org; Wed, 10 Nov 2021 02:13:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39214) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhlI-0002Dx-1d; Wed, 10 Nov 2021 02:11:12 -0500 Received: from out28-99.mail.aliyun.com ([115.124.28.99]:34714) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhlF-0004t4-Up; Wed, 10 Nov 2021 02:11:11 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LqV1pok_1636528264) by smtp.aliyun-inc.com(10.147.40.233); Wed, 10 Nov 2021 15:11:04 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07457498|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0446471-0.000322164-0.955031; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047194; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.LqV1pok_1636528264; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 12/14] target/riscv: Split out the vill from vtype Date: Wed, 10 Nov 2021 15:04:50 +0800 Message-Id: <20211110070452.48539-13-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211110070452.48539-1-zhiwei_liu@c-sky.com> References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.99; envelope-from=zhiwei_liu@c-sky.com; helo=out28-99.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636528404723000001 Content-Type: text/plain; charset="utf-8" We need not specially process vtype when XLEN changes. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 1 + target/riscv/csr.c | 15 ++++++++++++++- target/riscv/machine.c | 1 + target/riscv/vector_helper.c | 7 ++----- 4 files changed, 18 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 73d7aa9ad7..e67531deab 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -121,6 +121,7 @@ struct CPURISCVState { target_ulong vl; target_ulong vstart; target_ulong vtype; + target_ulong vill; =20 target_ulong pc; target_ulong load_res; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 59e368f004..33e342f529 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -286,7 +286,20 @@ static RISCVException write_fcsr(CPURISCVState *env, i= nt csrno, static RISCVException read_vtype(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->vtype; + target_ulong vill; + switch (cpu_get_xl(env)) { + case MXL_RV32: + vill =3D env->vill << 31; + break; +#ifdef TARGET_RISCV64 + case MXL_RV64: + vill =3D env->vill << 63; + break; +#endif + default: + g_assert_not_reached(); + } + *val =3D vill | env->vtype; return RISCV_EXCP_NONE; } =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 19e982d3f0..cc4dda4b93 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -104,6 +104,7 @@ static const VMStateDescription vmstate_vector =3D { VMSTATE_UINTTL(env.vl, RISCVCPU), VMSTATE_UINTTL(env.vstart, RISCVCPU), VMSTATE_UINTTL(env.vtype, RISCVCPU), + VMSTATE_UINTTL(env.vill, RISCVCPU), VMSTATE_END_OF_LIST() } }; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 51bcf63d65..7d7b554789 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -45,11 +45,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_u= long s1, } if ((sew > cpu->cfg.elen) || vill || (ediv !=3D 0) || (reserved !=3D 0= )) { /* only set vill bit. */ - if (xlen < TARGET_LONG_BITS) { - env->vtype =3D FIELD_DP64(0, VTYPE, VILL_XLEN32, 1); - } else { - env->vtype =3D FIELD_DP64(0, VTYPE, VILL, 1); - } + env->vill =3D 1; + env->vtype =3D 0; env->vl =3D 0; env->vstart =3D 0; return 0; --=20 2.25.1