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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=paolo.bonzini@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Levitsky Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635952592067100001 Content-Type: text/plain; charset="utf-8" From: Maxim Levitsky Signed-off-by: Maxim Levitsky Message-Id: <20211101132300.192584-4-mlevitsk@redhat.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 5 +++++ target/i386/cpu.h | 4 ++++ target/i386/kvm/kvm.c | 15 +++++++++++++++ target/i386/machine.c | 22 ++++++++++++++++++++++ 4 files changed, 46 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 598d451dcf..53a23ca006 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5928,6 +5928,11 @@ static void x86_cpu_reset(DeviceState *dev) } =20 x86_cpu_set_sgxlepubkeyhash(env); + + if (env->features[FEAT_SVM] & CPUID_SVM_TSCSCALE) { + env->amd_tsc_scale_msr =3D MSR_AMD64_TSC_RATIO_DEFAULT; + } + #endif } =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 3edaad7688..04f2b790c9 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -499,6 +499,9 @@ typedef enum X86Seg { #define MSR_GSBASE 0xc0000101 #define MSR_KERNELGSBASE 0xc0000102 #define MSR_TSC_AUX 0xc0000103 +#define MSR_AMD64_TSC_RATIO 0xc0000104 + +#define MSR_AMD64_TSC_RATIO_DEFAULT 0x100000000ULL =20 #define MSR_VM_HSAVE_PA 0xc0010117 =20 @@ -1536,6 +1539,7 @@ typedef struct CPUX86State { uint32_t tsx_ctrl; =20 uint64_t spec_ctrl; + uint64_t amd_tsc_scale_msr; uint64_t virt_ssbd; =20 /* End of state preserved by INIT (dummy marker). */ diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 0eb7a0340c..5a698bde19 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -105,6 +105,7 @@ static bool has_msr_hv_reenlightenment; static bool has_msr_xss; static bool has_msr_umwait; static bool has_msr_spec_ctrl; +static bool has_tsc_scale_msr; static bool has_msr_tsx_ctrl; static bool has_msr_virt_ssbd; static bool has_msr_smi_count; @@ -2216,6 +2217,9 @@ static int kvm_get_supported_msrs(KVMState *s) case MSR_IA32_SPEC_CTRL: has_msr_spec_ctrl =3D true; break; + case MSR_AMD64_TSC_RATIO: + has_tsc_scale_msr =3D true; + break; case MSR_IA32_TSX_CTRL: has_msr_tsx_ctrl =3D true; break; @@ -2972,6 +2976,10 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (has_msr_spec_ctrl) { kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl); } + if (has_tsc_scale_msr) { + kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, env->amd_tsc_scale_msr= ); + } + if (has_msr_tsx_ctrl) { kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl); } @@ -3377,6 +3385,10 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_spec_ctrl) { kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0); } + if (has_tsc_scale_msr) { + kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, 0); + } + if (has_msr_tsx_ctrl) { kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0); } @@ -3788,6 +3800,9 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_IA32_SPEC_CTRL: env->spec_ctrl =3D msrs[i].data; break; + case MSR_AMD64_TSC_RATIO: + env->amd_tsc_scale_msr =3D msrs[i].data; + break; case MSR_IA32_TSX_CTRL: env->tsx_ctrl =3D msrs[i].data; break; diff --git a/target/i386/machine.c b/target/i386/machine.c index 4367931623..83c2b91529 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1280,6 +1280,27 @@ static const VMStateDescription vmstate_spec_ctrl = =3D { } }; =20 + +static bool amd_tsc_scale_msr_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return (env->features[FEAT_SVM] & CPUID_SVM_TSCSCALE); +} + +static const VMStateDescription amd_tsc_scale_msr_ctrl =3D { + .name =3D "cpu/amd_tsc_scale_msr", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D amd_tsc_scale_msr_needed, + .fields =3D (VMStateField[]){ + VMSTATE_UINT64(env.amd_tsc_scale_msr, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + + static bool intel_pt_enable_needed(void *opaque) { X86CPU *cpu =3D opaque; @@ -1558,6 +1579,7 @@ const VMStateDescription vmstate_x86_cpu =3D { &vmstate_pkru, &vmstate_pkrs, &vmstate_spec_ctrl, + &amd_tsc_scale_msr_ctrl, &vmstate_mcg_ext_ctl, &vmstate_msr_intel_pt, &vmstate_msr_virt_ssbd, --=20 2.31.1