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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id a1sm9053281wri.89.2021.11.02.06.44.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:44:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sNrUNW9aVz2ixvALVPGW8JPx1J4reeP0whjPhiYCgSg=; b=XtGDsNL70IJSHDlbXlqwA7X063T5p1gOImjA2QLjBPqHwT5fi5ZFY3iO/2nvONJB4L miN9CV7rMLTaLJUiCDn+eS4TKbOCuTMQb3LNd7gbtaNOS0+Wxz7x2fx/ba+YuOFuPQpW q4rUMwOy9skidcjmWHzxhEcrvhaK5NmOceMO/n8iPuGJWJSWoODsbPO2dt7EnedThNZE ZbRr1VNWvm4yNa8gVrSB8YtznrA+5whBioTNaMxJl3FPX+S011mdnZYwMGuF3XE50/9H UhEVUwNA3t4cFZq10JHyM+VXgWF2uZQF0+paxrd9yjv6p9DZu4KtDRv95O8UgyZlU8cF wu1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sNrUNW9aVz2ixvALVPGW8JPx1J4reeP0whjPhiYCgSg=; b=QZGO2LIB6t30Q7UBuS6PJrSmYe/jmC9j5KV44UN20UvcwPo1SRUJrukpT5LPfHMPH5 7PHrfEbndxVE1l7wRhY1+3K2M6AWcNFMmIE8C1Op7wc7NMEn7BGs7nzG4O8gidXp+YiV uAJnTyIx9Y+zhIR6q8WpkdKrTaoCswaNWkUbclPNWBHKYewvNtpuTqtFAHgS2UI+MnXE UPJIn/eXKNPnlNVPb7KXl5wGJQZDjIeqLsasOObhFKXDaMBs7a6FsnYwrwOKHtot+Gu+ MEAaK0hLFoMHhLUnZiZLantiJlMzkAwx447swiy8IJEP/+l9UBZRsn+CuNhcIxTsnp3x kURQ== X-Gm-Message-State: AOAM5302MqPbR3dlhi2v46ggT1DtiPmvKzx99JPeJG3Rpuom0GX1qNV4 N0wS28uNoSYuukBkRtvJmP0= X-Google-Smtp-Source: ABdhPJzV3/KYbRd5Ex+klrLidenNOqJlN2UCxmW6n1L7Q95T90F0ZiOeGd+EyPSPHDLUbG+1TK8Pdw== X-Received: by 2002:adf:f681:: with SMTP id v1mr26088243wrp.367.1635860691418; Tue, 02 Nov 2021 06:44:51 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 27/41] target/mips: Convert MSA ELM instruction format to decodetree Date: Tue, 2 Nov 2021 14:42:26 +0100 Message-Id: <20211102134240.3036524-28-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860693966100003 Convert instructions with an immediate element index and data format df/n to decodetree. Since the 'data format' and 'n' fields are constant values, use tcg_constant_i32() instead of a TCG temporaries. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-25-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 8 +++++ target/mips/tcg/msa_translate.c | 57 +++++++++++++++++++++++++-------- 2 files changed, 52 insertions(+), 13 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 391261109a5..bf014524eed 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -18,7 +18,10 @@ &msa_ldi df wd sa &msa_i df wd ws sa &msa_bit df wd ws m +&msa_elm_df df wd ws n =20 +%elm_df 16:6 !function=3Delm_df +%elm_n 16:6 !function=3Delm_n %bit_df 16:7 !function=3Dbit_df %bit_m 16:7 !function=3Dbit_m %2r_df_w 16:1 !function=3Dplus_2 @@ -29,6 +32,7 @@ @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3D3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@elm_df ...... .... ...... ws:5 wd:5 ...... &msa_elm_df df= =3D%elm_df n=3D%elm_n @vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=3D0 @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=3D0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=3D0 = df=3D%2r_df_w @@ -161,6 +165,10 @@ BNZ 010001 111 .. ..... ..............= .. @bz HSUB_S 011110 110.. ..... ..... ..... 010101 @3r HSUB_U 011110 111.. ..... ..... ..... 010101 @3r =20 + SLDI 011110 0000 ...... ..... ..... 011001 @elm_df + SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df + INSVE 011110 0101 ...... ..... ..... 011001 @elm_df + FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf_w diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 3b95e081a04..14e0a8879c4 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -17,6 +17,8 @@ #include "fpu_helper.h" #include "internal.h" =20 +static int elm_n(DisasContext *ctx, int x); +static int elm_df(DisasContext *ctx, int x); static int bit_m(DisasContext *ctx, int x); static int bit_df(DisasContext *ctx, int x); =20 @@ -42,15 +44,12 @@ enum { =20 enum { /* ELM instructions df(bits 21..16) =3D _b, _h, _w, _d */ - OPC_SLDI_df =3D (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_CTCMSA =3D (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_SPLATI_df =3D (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_CFCMSA =3D (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, OPC_COPY_S_df =3D (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_MOVE_V =3D (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM, OPC_COPY_U_df =3D (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_INSERT_df =3D (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM, - OPC_INSVE_df =3D (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM, }; =20 static const char msaregnames[][6] =3D { @@ -107,6 +106,24 @@ static int df_extract_df(DisasContext *ctx, int x, con= st struct dfe *s) return -1; } =20 +static const struct dfe df_elm[] =3D { + /* Table 3.26 ELM Instruction Format */ + [DF_BYTE] =3D {4, 2, 0b00}, + [DF_HALF] =3D {3, 3, 0b100}, + [DF_WORD] =3D {2, 4, 0b1100}, + [DF_DOUBLE] =3D {1, 5, 0b11100} +}; + +static int elm_n(DisasContext *ctx, int x) +{ + return df_extract_val(ctx, x, df_elm); +} + +static int elm_df(DisasContext *ctx, int x) +{ + return df_extract_df(ctx, x, df_elm); +} + static const struct dfe df_bit[] =3D { /* Table 3.28 BIT Instruction Format */ [DF_BYTE] =3D {3, 4, 0b1110}, @@ -551,6 +568,30 @@ static void gen_msa_elm_3e(DisasContext *ctx) tcg_temp_free_i32(tsr); } =20 +static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a, + gen_helper_piiii *gen_msa_elm_df) +{ + if (a->df < 0) { + return false; + } + + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_msa_elm_df(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->n)); + + return true; +} + +TRANS(SLDI, trans_msa_elm, gen_helper_msa_sldi_df); +TRANS(SPLATI, trans_msa_elm, gen_helper_msa_splati_df); +TRANS(INSVE, trans_msa_elm, gen_helper_msa_insve_df); + static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) { #define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) @@ -560,18 +601,8 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t= df, uint32_t n) TCGv_i32 tws =3D tcg_const_i32(ws); TCGv_i32 twd =3D tcg_const_i32(wd); TCGv_i32 tn =3D tcg_const_i32(n); - TCGv_i32 tdf =3D tcg_constant_i32(df); =20 switch (MASK_MSA_ELM(ctx->opcode)) { - case OPC_SLDI_df: - gen_helper_msa_sldi_df(cpu_env, tdf, twd, tws, tn); - break; - case OPC_SPLATI_df: - gen_helper_msa_splati_df(cpu_env, tdf, twd, tws, tn); - break; - case OPC_INSVE_df: - gen_helper_msa_insve_df(cpu_env, tdf, twd, tws, tn); - break; case OPC_COPY_S_df: case OPC_COPY_U_df: case OPC_INSERT_df: --=20 2.31.1