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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id u6sm2510348wmc.29.2021.11.02.06.44.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:44:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jRFqNue7p0Qm34S0HJ0qJjQT9HmvoceQ86OEjAtLFvk=; b=pqiteujifMRhice6OOFylkLmfsiNwBB0OVa/FNYPS920yjVbn8728dL3eO6B/eacHw ZfG/UWnfXQBRFN5AKXmvvNiEGSXfiHoK3K4/XQjeOeGBQtpTVNIFDS5u115WP19DJ0CR cAvy+RKUCTXTqvTCqFV7mRUSNJ0KJsXVUtx93pxoYloFKwFBBZ6iRcK0CQl5TZbzK1Yt OLRB+TzHe5w1HXkq13rpQf4NaMsmxUxbQJOt0P7RN8FkRrM/UcdTdShmYeFqQTVbbBxl A+ZyVtv0CzMBy9IoJJ1z2vzewHFhG/R+EJw0gjiE2ROBt5CMOcy0cTgqYd+iLvPYn7tg oEbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=jRFqNue7p0Qm34S0HJ0qJjQT9HmvoceQ86OEjAtLFvk=; b=V06z/bfC0nkjKkNBwnpVZJiZZm05rW8g3Jkcfk6BvD4yl+1gizHTigoSyJ17w01uQp qlMX2KyrUqjxU7kGf7K7Q/xaShAaCcwS0tJayeI1MFfNaV6F2es/rNePucg8VldYaHPI RCQUqV2i7qErWJisenqx+0ccP6ygm8MiBwd3uXHQfo68f0dcVjWJtJSeAnoBI/rgoklq JPGEwyhQ5DNvQiJOimlZqd/8R+/Z9+JmvVbBfNoJ5uP7wsC3K4UC6M5PKmW7lQ/w/JBT MHpeARZCZZGL6qqZ0sZX9UxuZ6e93xkNV3pq0LmwF4WBM/U9m7SOtjRoHecxcaz8o5H9 M6MQ== X-Gm-Message-State: AOAM530YqBKt4zHFUw6l0o9NIv5vWonfcVOyEqGIwTxEQZtW/UpaP/mw 1Lf802eHVyqM1V88hfipoLI= X-Google-Smtp-Source: ABdhPJyw5l5nufgzy3+ok/UdzExCChrGpBkSiznPrES6SNvG82VFuouUX01oqVau6lC9Md5NH0a0fA== X-Received: by 2002:a05:6000:1868:: with SMTP id d8mr10860423wri.285.1635860662644; Tue, 02 Nov 2021 06:44:22 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 21/41] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Date: Tue, 2 Nov 2021 14:42:20 +0100 Message-Id: <20211102134240.3036524-22-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860666846100001 Convert 3-register floating-point or fixed-point operations to decodetree. Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20211028210843.2120802-19-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 9 +++++ target/mips/tcg/msa_translate.c | 68 ++++++++++++++------------------- 2 files changed, 38 insertions(+), 39 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index afcb868aade..f90b2d21c92 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -22,6 +22,7 @@ %bit_df 16:7 !function=3Dbit_df %bit_m 16:7 !function=3Dbit_m %2r_df_w 16:1 !function=3Dplus_2 +%3r_df_h 21:1 !function=3Dplus_1 =20 @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @@ -30,6 +31,7 @@ @vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=3D0 @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=3D0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=3D0 = df=3D%2r_df_w +@3rf_h ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=3D%3= r_df_h @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i @i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i @@ -84,6 +86,13 @@ BNZ 010001 111 .. ..... ................= @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit =20 + MUL_Q 011110 0100 . ..... ..... ..... 011100 @3rf_h + MADD_Q 011110 0101 . ..... ..... ..... 011100 @3rf_h + MSUB_Q 011110 0110 . ..... ..... ..... 011100 @3rf_h + MULR_Q 011110 1100 . ..... ..... ..... 011100 @3rf_h + MADDR_Q 011110 1101 . ..... ..... ..... 011100 @3rf_h + MSUBR_Q 011110 1110 . ..... ..... ..... 011100 @3rf_h + AND_V 011110 00000 ..... ..... ..... 011110 @vec OR_V 011110 00001 ..... ..... ..... 011110 @vec NOR_V 011110 00010 ..... ..... ..... 011110 @vec diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 45a6b60d547..65e56b23171 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -20,6 +20,11 @@ static int bit_m(DisasContext *ctx, int x); static int bit_df(DisasContext *ctx, int x); =20 +static inline int plus_1(DisasContext *s, int x) +{ + return x + 1; +} + static inline int plus_2(DisasContext *s, int x) { return x + 2; @@ -138,12 +143,9 @@ enum { OPC_FCNE_df =3D (0x3 << 22) | OPC_MSA_3RF_1C, OPC_FCLT_df =3D (0x4 << 22) | OPC_MSA_3RF_1A, OPC_FMADD_df =3D (0x4 << 22) | OPC_MSA_3RF_1B, - OPC_MUL_Q_df =3D (0x4 << 22) | OPC_MSA_3RF_1C, OPC_FCULT_df =3D (0x5 << 22) | OPC_MSA_3RF_1A, OPC_FMSUB_df =3D (0x5 << 22) | OPC_MSA_3RF_1B, - OPC_MADD_Q_df =3D (0x5 << 22) | OPC_MSA_3RF_1C, OPC_FCLE_df =3D (0x6 << 22) | OPC_MSA_3RF_1A, - OPC_MSUB_Q_df =3D (0x6 << 22) | OPC_MSA_3RF_1C, OPC_FCULE_df =3D (0x7 << 22) | OPC_MSA_3RF_1A, OPC_FEXP2_df =3D (0x7 << 22) | OPC_MSA_3RF_1B, OPC_FSAF_df =3D (0x8 << 22) | OPC_MSA_3RF_1A, @@ -157,13 +159,10 @@ enum { OPC_FSNE_df =3D (0xB << 22) | OPC_MSA_3RF_1C, OPC_FSLT_df =3D (0xC << 22) | OPC_MSA_3RF_1A, OPC_FMIN_df =3D (0xC << 22) | OPC_MSA_3RF_1B, - OPC_MULR_Q_df =3D (0xC << 22) | OPC_MSA_3RF_1C, OPC_FSULT_df =3D (0xD << 22) | OPC_MSA_3RF_1A, OPC_FMIN_A_df =3D (0xD << 22) | OPC_MSA_3RF_1B, - OPC_MADDR_Q_df =3D (0xD << 22) | OPC_MSA_3RF_1C, OPC_FSLE_df =3D (0xE << 22) | OPC_MSA_3RF_1A, OPC_FMAX_df =3D (0xE << 22) | OPC_MSA_3RF_1B, - OPC_MSUBR_Q_df =3D (0xE << 22) | OPC_MSA_3RF_1C, OPC_FSULE_df =3D (0xF << 22) | OPC_MSA_3RF_1A, OPC_FMAX_A_df =3D (0xF << 22) | OPC_MSA_3RF_1B, }; @@ -507,6 +506,22 @@ TRANS(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df= ); TRANS(SRARI, trans_msa_bit, gen_helper_msa_srari_df); TRANS(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df); =20 +static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a, + gen_helper_piiii *gen_msa_3rf) +{ + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_msa_3rf(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->wt)); + + return true; +} + static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a, gen_helper_piii *gen_msa_3r) { @@ -1682,6 +1697,13 @@ static void gen_msa_elm(DisasContext *ctx) gen_msa_elm_df(ctx, df, n); } =20 +TRANS(MUL_Q, trans_msa_3rf, gen_helper_msa_mul_q_df); +TRANS(MADD_Q, trans_msa_3rf, gen_helper_msa_madd_q_df); +TRANS(MSUB_Q, trans_msa_3rf, gen_helper_msa_msub_q_df); +TRANS(MULR_Q, trans_msa_3rf, gen_helper_msa_mulr_q_df); +TRANS(MADDR_Q, trans_msa_3rf, gen_helper_msa_maddr_q_df); +TRANS(MSUBR_Q, trans_msa_3rf, gen_helper_msa_msubr_q_df); + static void gen_msa_3rf(DisasContext *ctx) { #define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) @@ -1693,22 +1715,8 @@ static void gen_msa_3rf(DisasContext *ctx) TCGv_i32 twd =3D tcg_const_i32(wd); TCGv_i32 tws =3D tcg_const_i32(ws); TCGv_i32 twt =3D tcg_const_i32(wt); - TCGv_i32 tdf; - /* adjust df value for floating-point instruction */ - switch (MASK_MSA_3RF(ctx->opcode)) { - case OPC_MUL_Q_df: - case OPC_MADD_Q_df: - case OPC_MSUB_Q_df: - case OPC_MULR_Q_df: - case OPC_MADDR_Q_df: - case OPC_MSUBR_Q_df: - tdf =3D tcg_constant_i32(DF_HALF + df); - break; - default: - tdf =3D tcg_constant_i32(DF_WORD + df); - break; - } + TCGv_i32 tdf =3D tcg_constant_i32(DF_WORD + df); =20 switch (MASK_MSA_3RF(ctx->opcode)) { case OPC_FCAF_df: @@ -1750,24 +1758,15 @@ static void gen_msa_3rf(DisasContext *ctx) case OPC_FMADD_df: gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MUL_Q_df: - gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FCULT_df: gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt); break; case OPC_FMSUB_df: gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MADD_Q_df: - gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FCLE_df: gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MSUB_Q_df: - gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FCULE_df: gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt); break; @@ -1807,27 +1806,18 @@ static void gen_msa_3rf(DisasContext *ctx) case OPC_FMIN_df: gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MULR_Q_df: - gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FSULT_df: gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt); break; case OPC_FMIN_A_df: gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MADDR_Q_df: - gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FSLE_df: gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt); break; case OPC_FMAX_df: gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MSUBR_Q_df: - gen_helper_msa_msubr_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FSULE_df: gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.31.1