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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id o2sm17709609wrg.1.2021.11.02.06.44.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:44:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ITK2jAKvKvh2aGzj1uYLx351dgZJw7ejqPzY8bO8NZY=; b=ci17iVaYK2XvvuPEYq1vLOK21LudqxnYQTP1/CsCugU7g3GQIw7nNeErCtfVbnLDFE 5cU9D/J9gWnqWnpimYQL15ghaJe21FpQf6AN4OBKXSSSmddEaudLzuEDwOFnw30DFbEJ BGR8XLnD1mwENOqN1YZm8AzKpmmcrhabfrtagZtRbUzy49uzbnl9LfhrGS6KZroXD1NV nFFQSTmUpwGXRIHlpGAIyBWlYLjZJGu+ZXW/88lW09k8NAdRNBJokewZLSIUnCsJJL8W P1ziBBWOxitYYRO8O+hqgxSOZRMDYk4fS8rnRHbdX7+xUQLKlcC1VESaGN1ZMwsCVD3e hVRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ITK2jAKvKvh2aGzj1uYLx351dgZJw7ejqPzY8bO8NZY=; b=X6QcDwMtR/1QUQlva4M1+5nt7JMGogXtuTJrJYLE2OX1pjlLI0AdI3DzPsrf526F8m X/Jksilk1dGOEXQ3iJS76WUyByZeExI0+H2FwXaG3hCLC88P301DbF/sC1bj8JKsEOHJ A0dL8pK5+pXqCJwyrt0PAxOUhk1IEXrq378N/6GmVxYSps8JfWr7WnUxEytBuIWOpAn4 vB8TLdoEsR+gwUZF0L6Y6B41eMPRWZsBMnQn3PK+Dg1UtaQcYjrngMe+kcRRMhAvFuIe txuMr1nfz8AEL+/NXIkm5kyvQHEumlxlyatCVxrEhx9yjgFqrfCJNI+lSJVuX9G1Fh+W 7xPQ== X-Gm-Message-State: AOAM532RvGT3h67iQtFZGYzP0+TpKqRXLyXlvhw0pzBWyOft8FmoCYdx cvul7jb4Y610pob/n3Ks+tM= X-Google-Smtp-Source: ABdhPJyYqC2zC3R7c/rj/45vkENLjiyOOrJagYXSEr0dqOfO7IpbK+fKMEOMfUhvyeDA7LnlaqWhNA== X-Received: by 2002:a5d:6481:: with SMTP id o1mr47703211wri.60.1635860658032; Tue, 02 Nov 2021 06:44:18 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 20/41] target/mips: Convert MSA VEC instruction format to decodetree Date: Tue, 2 Nov 2021 14:42:19 +0100 Message-Id: <20211102134240.3036524-21-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860662073100001 Convert 3-register instructions with implicit data formats to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-18-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 8 +++ target/mips/tcg/msa_translate.c | 98 ++++++++------------------------- 2 files changed, 31 insertions(+), 75 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index b6ac80560f6..afcb868aade 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -27,6 +27,7 @@ @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3D3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=3D0 @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=3D0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=3D0 = df=3D%2r_df_w @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @@ -83,6 +84,13 @@ BNZ 010001 111 .. ..... ................= @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit =20 + AND_V 011110 00000 ..... ..... ..... 011110 @vec + OR_V 011110 00001 ..... ..... ..... 011110 @vec + NOR_V 011110 00010 ..... ..... ..... 011110 @vec + XOR_V 011110 00011 ..... ..... ..... 011110 @vec + BMNZ_V 011110 00100 ..... ..... ..... 011110 @vec + BMZ_V 011110 00101 ..... ..... ..... 011110 @vec + BSEL_V 011110 00110 ..... ..... ..... 011110 @vec FILL 011110 11000000 .. ..... ..... 011110 @2r PCNT 011110 11000001 .. ..... ..... 011110 @2r NLOC 011110 11000010 .. ..... ..... 011110 @2r diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index c6e38281a64..45a6b60d547 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -45,19 +45,9 @@ enum { OPC_MSA_3RF_1A =3D 0x1A | OPC_MSA, OPC_MSA_3RF_1B =3D 0x1B | OPC_MSA, OPC_MSA_3RF_1C =3D 0x1C | OPC_MSA, - OPC_MSA_VEC =3D 0x1E | OPC_MSA, }; =20 enum { - /* VEC instruction */ - OPC_AND_V =3D (0x00 << 21) | OPC_MSA_VEC, - OPC_OR_V =3D (0x01 << 21) | OPC_MSA_VEC, - OPC_NOR_V =3D (0x02 << 21) | OPC_MSA_VEC, - OPC_XOR_V =3D (0x03 << 21) | OPC_MSA_VEC, - OPC_BMNZ_V =3D (0x04 << 21) | OPC_MSA_VEC, - OPC_BMZ_V =3D (0x05 << 21) | OPC_MSA_VEC, - OPC_BSEL_V =3D (0x06 << 21) | OPC_MSA_VEC, - /* 3R instruction df(bits 22..21) =3D _b, _h, _w, d */ OPC_SLL_df =3D (0x0 << 23) | OPC_MSA_3R_0D, OPC_ADDV_df =3D (0x0 << 23) | OPC_MSA_3R_0E, @@ -517,6 +507,29 @@ TRANS(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df= ); TRANS(SRARI, trans_msa_bit, gen_helper_msa_srari_df); TRANS(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df); =20 +static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a, + gen_helper_piii *gen_msa_3r) +{ + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_msa_3r(cpu_env, + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->wt)); + + return true; +} + +TRANS(AND_V, trans_msa_3r, gen_helper_msa_and_v); +TRANS(OR_V, trans_msa_3r, gen_helper_msa_or_v); +TRANS(NOR_V, trans_msa_3r, gen_helper_msa_nor_v); +TRANS(XOR_V, trans_msa_3r, gen_helper_msa_xor_v); +TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa_bmnz_v); +TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v); +TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v); + static void gen_msa_3r(DisasContext *ctx) { #define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) @@ -1899,68 +1912,6 @@ TRANS(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_= u_df); TRANS(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df); TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df); =20 -static void gen_msa_vec_v(DisasContext *ctx) -{ -#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21))) - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - - switch (MASK_MSA_VEC(ctx->opcode)) { - case OPC_AND_V: - gen_helper_msa_and_v(cpu_env, twd, tws, twt); - break; - case OPC_OR_V: - gen_helper_msa_or_v(cpu_env, twd, tws, twt); - break; - case OPC_NOR_V: - gen_helper_msa_nor_v(cpu_env, twd, tws, twt); - break; - case OPC_XOR_V: - gen_helper_msa_xor_v(cpu_env, twd, tws, twt); - break; - case OPC_BMNZ_V: - gen_helper_msa_bmnz_v(cpu_env, twd, tws, twt); - break; - case OPC_BMZ_V: - gen_helper_msa_bmz_v(cpu_env, twd, tws, twt); - break; - case OPC_BSEL_V: - gen_helper_msa_bsel_v(cpu_env, twd, tws, twt); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); -} - -static void gen_msa_vec(DisasContext *ctx) -{ - switch (MASK_MSA_VEC(ctx->opcode)) { - case OPC_AND_V: - case OPC_OR_V: - case OPC_NOR_V: - case OPC_XOR_V: - case OPC_BMNZ_V: - case OPC_BMZ_V: - case OPC_BSEL_V: - gen_msa_vec_v(ctx); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } -} - static bool trans_MSA(DisasContext *ctx, arg_MSA *a) { uint32_t opcode =3D ctx->opcode; @@ -1989,9 +1940,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) case OPC_MSA_3RF_1C: gen_msa_3rf(ctx); break; - case OPC_MSA_VEC: - gen_msa_vec(ctx); - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); --=20 2.31.1