From nobody Tue Feb 10 20:28:03 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860645; cv=none; d=zohomail.com; s=zohoarc; b=n9ZUSkgomGe02xOkalvoPZ5loxz7iTRHDa9XhbSB6f25AyLt9/F6Pd0QOE6N0knPmkWtAskYrkrvJ8YVcn9TIhjxq/k05czPxU4DVU3EkXS6WgetwXqWqrrpO+k2uS2AZvT/mrEu3hT0qvVsPlfjKnfPGHaARP8Yl2biLHW97Bs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860645; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=37CQJH1M7mLS2C9WYzcFC/BbmOyawPZjqzGXIWjjpAA=; b=nT0a1vQAogRvJQ77pW9Xyo36QUBq97HHDiyDeC/XPYGJCDNh4ysSU854/eusq7YLnhM3AqMbiLJBrejNHK5gip1O5nEXEoS+1fKF4bFViDaiwnz5zIPK4z6gPm4CM3Hh4Ukc8PPBNW3T7SgdCosov7pj2EbUgF0MWdDU6d3QyPc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by mx.zohomail.com with SMTPS id 1635860645753145.2022865327242; Tue, 2 Nov 2021 06:44:05 -0700 (PDT) Received: by mail-wr1-f44.google.com with SMTP id s13so26254827wrb.3 for ; Tue, 02 Nov 2021 06:44:05 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. (62.red-83-57-168.dynamicip.rima-tde.net. [83.57.168.62]) by smtp.gmail.com with ESMTPSA id m125sm2584374wmm.39.2021.11.02.06.44.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:44:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=37CQJH1M7mLS2C9WYzcFC/BbmOyawPZjqzGXIWjjpAA=; b=EYM1M6wqAgpwSwapnkFnwh6zA6aUlaJk2LrffekmNTAjSAiTRs3sGR4ajyHEHwZXpl CKSJhjuqKQVAsKNJafHeIYA0NaICAHPnp4nZ53OvOW3RLoSXCbcGSs8HNee/Fi6yPmhQ JThdK7NF1/LW3EGIpS3rcV7kDtE4T57q59gZ7rjCzsqo/eeHI+2FKMoT8f2nSBE0W91G Ep5H+yswk/cgv7+IAOffLm3AcvSSIdIQS6GCZ5AkzNohRSj2mIqRAASgfftvwEHHtbM/ HQ4U982DAuSIZIWiiV8fB12DWawyi8iKXrXkE4zEomelxOWXO9Kmjt98msau/VSsd5+4 fTCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=37CQJH1M7mLS2C9WYzcFC/BbmOyawPZjqzGXIWjjpAA=; b=QeAWDAmN1j5O7X8tHpI/9wCsB7ZmKertI2P3/97avwXJBso29OpiBD7q45s0Sr3Y+m ZoMjiL+L5PBm2Pws/bCoCzK6nrjPk0zzJ0PHVyPg5wAZk99V5dBYSTS/JdjGW4r8nJ6Y FQjmvgnnXROGk/iq5g36ahVxebduHL1C16tixPJFrWuoylJDSsuvadmuIsov8cZjFPkr /3Wq53E5pYSjTPw8ULPOvs2/8diHxjcQ10yQbb6J8Jv5fWQTZkckqd4BbaHLXQtk8UoW mmlrUMtseU3byuId+uwDi0iiVEF8trnUxaPpOV+vy/+ChMu1noT1yio7zm26m/b2ZEd5 wxaw== X-Gm-Message-State: AOAM533Xl7XoanRo1gEmatflSWoSKAC//F38D/ZptJfBv5e4+x1j3Ctt KBTb0QXXFNla+GqrDnuU49o= X-Google-Smtp-Source: ABdhPJwTyZQdWvITQGfuQNlOWHWupw3kcjLRKH4piHjRvXI4eBSSyC6JfWxagt70uuIEZko/SxmvqQ== X-Received: by 2002:a05:6000:181:: with SMTP id p1mr25116662wrx.292.1635860643952; Tue, 02 Nov 2021 06:44:03 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 17/41] target/mips: Convert MSA 2RF instruction format to decodetree Date: Tue, 2 Nov 2021 14:42:16 +0100 Message-Id: <20211102134240.3036524-18-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860646169100001 Convert 2-register floating-point operations to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-15-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 20 ++++++ target/mips/tcg/msa_translate.c | 118 +++++++++----------------------- 2 files changed, 53 insertions(+), 85 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 0aeb83d5c5b..33288b50355 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -13,6 +13,7 @@ =20 &r rs rt rd sa =20 +&msa_r df wd ws wt &msa_bz df wt sa &msa_ldi df wd sa &msa_i df wd ws sa @@ -20,11 +21,13 @@ =20 %bit_df 16:7 !function=3Dbit_df %bit_m 16:7 !function=3Dbit_m +%2r_df_w 16:1 !function=3Dplus_2 =20 @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3D3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=3D0 = df=3D%2r_df_w @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i @i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i @@ -79,6 +82,23 @@ BNZ 010001 111 .. ..... ................= @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit =20 + FCLASS 011110 110010000 . ..... ..... 011110 @2rf + FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf + FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf + FSQRT 011110 110010011 . ..... ..... 011110 @2rf + FRSQRT 011110 110010100 . ..... ..... 011110 @2rf + FRCP 011110 110010101 . ..... ..... 011110 @2rf + FRINT 011110 110010110 . ..... ..... 011110 @2rf + FLOG2 011110 110010111 . ..... ..... 011110 @2rf + FEXUPL 011110 110011000 . ..... ..... 011110 @2rf + FEXUPR 011110 110011001 . ..... ..... 011110 @2rf + FFQL 011110 110011010 . ..... ..... 011110 @2rf + FFQR 011110 110011011 . ..... ..... 011110 @2rf + FTINT_S 011110 110011100 . ..... ..... 011110 @2rf + FTINT_U 011110 110011101 . ..... ..... 011110 @2rf + FFINT_S 011110 110011110 . ..... ..... 011110 @2rf + FFINT_U 011110 110011111 . ..... ..... 011110 @2rf + LD 011110 .......... ..... ..... 1000 .. @ldst ST 011110 .......... ..... ..... 1001 .. @ldst =20 diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 2a7fb925b07..704273dfd2f 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -20,6 +20,11 @@ static int bit_m(DisasContext *ctx, int x); static int bit_df(DisasContext *ctx, int x); =20 +static inline int plus_2(DisasContext *s, int x) +{ + return x + 2; +} + /* Include the auto-generated decoder. */ #include "decode-msa.c.inc" =20 @@ -44,7 +49,7 @@ enum { }; =20 enum { - /* VEC/2R/2RF instruction */ + /* VEC/2R instruction */ OPC_AND_V =3D (0x00 << 21) | OPC_MSA_VEC, OPC_OR_V =3D (0x01 << 21) | OPC_MSA_VEC, OPC_NOR_V =3D (0x02 << 21) | OPC_MSA_VEC, @@ -54,7 +59,6 @@ enum { OPC_BSEL_V =3D (0x06 << 21) | OPC_MSA_VEC, =20 OPC_MSA_2R =3D (0x18 << 21) | OPC_MSA_VEC, - OPC_MSA_2RF =3D (0x19 << 21) | OPC_MSA_VEC, =20 /* 2R instruction df(bits 17..16) =3D _b, _h, _w, _d */ OPC_FILL_df =3D (0x00 << 18) | OPC_MSA_2R, @@ -62,24 +66,6 @@ enum { OPC_NLOC_df =3D (0x02 << 18) | OPC_MSA_2R, OPC_NLZC_df =3D (0x03 << 18) | OPC_MSA_2R, =20 - /* 2RF instruction df(bit 16) =3D _w, _d */ - OPC_FCLASS_df =3D (0x00 << 17) | OPC_MSA_2RF, - OPC_FTRUNC_S_df =3D (0x01 << 17) | OPC_MSA_2RF, - OPC_FTRUNC_U_df =3D (0x02 << 17) | OPC_MSA_2RF, - OPC_FSQRT_df =3D (0x03 << 17) | OPC_MSA_2RF, - OPC_FRSQRT_df =3D (0x04 << 17) | OPC_MSA_2RF, - OPC_FRCP_df =3D (0x05 << 17) | OPC_MSA_2RF, - OPC_FRINT_df =3D (0x06 << 17) | OPC_MSA_2RF, - OPC_FLOG2_df =3D (0x07 << 17) | OPC_MSA_2RF, - OPC_FEXUPL_df =3D (0x08 << 17) | OPC_MSA_2RF, - OPC_FEXUPR_df =3D (0x09 << 17) | OPC_MSA_2RF, - OPC_FFQL_df =3D (0x0A << 17) | OPC_MSA_2RF, - OPC_FFQR_df =3D (0x0B << 17) | OPC_MSA_2RF, - OPC_FTINT_S_df =3D (0x0C << 17) | OPC_MSA_2RF, - OPC_FTINT_U_df =3D (0x0D << 17) | OPC_MSA_2RF, - OPC_FFINT_S_df =3D (0x0E << 17) | OPC_MSA_2RF, - OPC_FFINT_U_df =3D (0x0F << 17) | OPC_MSA_2RF, - /* 3R instruction df(bits 22..21) =3D _b, _h, _w, d */ OPC_SLL_df =3D (0x0 << 23) | OPC_MSA_3R_0D, OPC_ADDV_df =3D (0x0 << 23) | OPC_MSA_3R_0E, @@ -1930,73 +1916,38 @@ static void gen_msa_2r(DisasContext *ctx) tcg_temp_free_i32(tws); } =20 -static void gen_msa_2rf(DisasContext *ctx) +static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a, + gen_helper_piii *gen_msa_2rf) { -#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ - (op & (0xf << 17))) - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - uint8_t df =3D (ctx->opcode >> 16) & 0x1; - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - /* adjust df value for floating-point instruction */ - TCGv_i32 tdf =3D tcg_constant_i32(DF_WORD + df); - - switch (MASK_MSA_2RF(ctx->opcode)) { - case OPC_FCLASS_df: - gen_helper_msa_fclass_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTRUNC_S_df: - gen_helper_msa_ftrunc_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTRUNC_U_df: - gen_helper_msa_ftrunc_u_df(cpu_env, tdf, twd, tws); - break; - case OPC_FSQRT_df: - gen_helper_msa_fsqrt_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRSQRT_df: - gen_helper_msa_frsqrt_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRCP_df: - gen_helper_msa_frcp_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRINT_df: - gen_helper_msa_frint_df(cpu_env, tdf, twd, tws); - break; - case OPC_FLOG2_df: - gen_helper_msa_flog2_df(cpu_env, tdf, twd, tws); - break; - case OPC_FEXUPL_df: - gen_helper_msa_fexupl_df(cpu_env, tdf, twd, tws); - break; - case OPC_FEXUPR_df: - gen_helper_msa_fexupr_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFQL_df: - gen_helper_msa_ffql_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFQR_df: - gen_helper_msa_ffqr_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTINT_S_df: - gen_helper_msa_ftint_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTINT_U_df: - gen_helper_msa_ftint_u_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFINT_S_df: - gen_helper_msa_ffint_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFINT_U_df: - gen_helper_msa_ffint_u_df(cpu_env, tdf, twd, tws); - break; + if (!check_msa_enabled(ctx)) { + return true; } =20 - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); + gen_msa_2rf(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws)); + + return true; } =20 +TRANS(FCLASS, trans_msa_2rf, gen_helper_msa_fclass_df); +TRANS(FTRUNC_S, trans_msa_2rf, gen_helper_msa_fclass_df); +TRANS(FTRUNC_U, trans_msa_2rf, gen_helper_msa_ftrunc_s_df); +TRANS(FSQRT, trans_msa_2rf, gen_helper_msa_fsqrt_df); +TRANS(FRSQRT, trans_msa_2rf, gen_helper_msa_frsqrt_df); +TRANS(FRCP, trans_msa_2rf, gen_helper_msa_frcp_df); +TRANS(FRINT, trans_msa_2rf, gen_helper_msa_frint_df); +TRANS(FLOG2, trans_msa_2rf, gen_helper_msa_flog2_df); +TRANS(FEXUPL, trans_msa_2rf, gen_helper_msa_fexupl_df); +TRANS(FEXUPR, trans_msa_2rf, gen_helper_msa_fexupr_df); +TRANS(FFQL, trans_msa_2rf, gen_helper_msa_ffql_df); +TRANS(FFQR, trans_msa_2rf, gen_helper_msa_ffqr_df); +TRANS(FTINT_S, trans_msa_2rf, gen_helper_msa_ftint_s_df); +TRANS(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df); +TRANS(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df); +TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df); + static void gen_msa_vec_v(DisasContext *ctx) { #define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21))) @@ -2055,9 +2006,6 @@ static void gen_msa_vec(DisasContext *ctx) case OPC_MSA_2R: gen_msa_2r(ctx); break; - case OPC_MSA_2RF: - gen_msa_2rf(ctx); - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); --=20 2.31.1