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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id q193sm2857011wme.48.2021.11.02.06.42.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:42:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GYjaEEe+Ru5uUdnZddVxZVIqZpROsaQfXPXEBpgAmpU=; b=ejYoKfOlWFOGWZKWCfDrxBO8+FPgENXnKkHhBLgwdhvFWR05z2g+8De6mood5EWsuu 1E8B9fvWJUp8yIMZtHKtUBpWcEe8ZMXyTaNEbxz05Xnzcjf5eoKRFRbEEtHyV51U6QC6 fREcZk9dDj6L7DFH+pDY3N+sHvcc65/v4+O+w85zMwqZoQsK2sFdAFs7jiD6fA7bu74x jTv2xHh2xgKRtvN5ccvm6WchuPmGvKeEv3rmCxDcaGbPhlKs9xSaB97kOx0jAkhS6Tcb aVLam6KTgMHkGwssyKsaswmvaj4oy06CUHvmzvPgKBc9CwPS+LDmJcqvouFeweSk66DE 91Ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=GYjaEEe+Ru5uUdnZddVxZVIqZpROsaQfXPXEBpgAmpU=; b=CDKd7XSxJHglDU9/Pq+ODPeBt56UOF8rj1pg0SLxibYI+9vrP7B6SoRbKct6zD+Pze P04+SwrDnG43Es8BawkREzXIdvd1DWvs/B5vxpSJ10oL/v6peAdeH/eCJvlDMwpJ6C33 Pufm1sopP5afkGrjJZeO4vjat/oBySkJXAx22CWopX4oeR4G+oWteahu6p1hfXAmtYQy p0FakEsRz6QZyJIpYOExr6A11teuga6Bw5fW41sfSspIApfdKqr+6oeZv7VbmaEgNpew FbGF0EASrUSGdK2dLySvsi4BtQvCFsH37P0v6uww6SpEVShz2yeu1zZuFvU78D/l+A+Q SUng== X-Gm-Message-State: AOAM533JUAfZ+S4V3b+zEhaVgTOPz9vpKtFpWIG9ulX3c1ZkfcJScyCf Ui458Ncp6ePu3sz4GfgG91c= X-Google-Smtp-Source: ABdhPJy8eCx1Jms5zop7wnLN7WUFKF/3+d9vOPn6xKBu28TqoG4iEtnCSimopoKlwnqHFMXZLfTi4Q== X-Received: by 2002:adf:e84d:: with SMTP id d13mr27825205wrn.72.1635860567317; Tue, 02 Nov 2021 06:42:47 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 01/41] MAINTAINERS: Add MIPS general architecture support entry Date: Tue, 2 Nov 2021 14:42:00 +0100 Message-Id: <20211102134240.3036524-2-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860570831100001 The architecture is covered in TCG (frontend and backend) and hardware models. Add a generic section matching the 'mips' word in patch subjects. Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211004092515.3819836-2-f4bug@amsat.org> Reviewed-by: Richard Henderson --- MAINTAINERS | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 310a9512ea1..a156c4bffc0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -109,6 +109,12 @@ K: ^Subject:.*(?i)s390x? T: git https://gitlab.com/cohuck/qemu.git s390-next L: qemu-s390x@nongnu.org =20 +MIPS general architecture support +M: Philippe Mathieu-Daud=C3=A9 +R: Jiaxun Yang +S: Odd Fixes +K: ^Subject:.*(?i)mips + Guest CPU cores (TCG) --------------------- Overall TCG CPUs @@ -242,7 +248,6 @@ F: include/hw/mips/ F: include/hw/misc/mips_* F: include/hw/timer/mips_gictimer.h F: tests/tcg/mips/ -K: ^Subject:.*(?i)mips =20 MIPS TCG CPUs (nanoMIPS ISA) S: Orphan --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.53 as permitted sender) client-ip=209.85.128.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860574; cv=none; d=zohomail.com; s=zohoarc; b=KA2oNa/+rNnSP4VbH6XB3AD9ACnTVcpTKkChc9xj7scLl2/sWDZukzrPrEjlpBY6ldlPHCa5UDG0qu9MbupbmFBgXxqHcc+3KyJ5ku8l5oAaYMJFHBHEI6WX5VJ5dk37PsenVOIOiNymIU0JvsJYT5oBnAGyh17a8Q9uqxgPs30= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860574; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=j/xEM6vLjAWjy6ZJIHvYWNvgWXnKjywi5uLYZJGHzmE=; b=h8pqAiaPRDTKJZ+0HIaBTpEKqHUmgblrXmdBVPeuAchnn3Wl+dDSzo4qdYjOHsL45PzZaTvr62uQ4T6t4ISZs8EJAtleeywi5xwk45xHXma2eX7RJW6TUy5ocptcAcTvIspn18Los/82Kz0S9Ze8W3ksJx64Fm10Pe2/iDlift4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) by mx.zohomail.com with SMTPS id 1635860574389284.8643311640594; Tue, 2 Nov 2021 06:42:54 -0700 (PDT) Received: by mail-wm1-f53.google.com with SMTP id 77-20020a1c0450000000b0033123de3425so2007077wme.0 for ; Tue, 02 Nov 2021 06:42:53 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id v185sm2550116wme.35.2021.11.02.06.42.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:42:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=j/xEM6vLjAWjy6ZJIHvYWNvgWXnKjywi5uLYZJGHzmE=; b=cpUPYV48r+4jB0BKZZNCGg8rubkzc34VE5gD1jwdSI4kn0wR7cnSHMSRkVv25XF5Yy xPsBA+W5PDQrmAk2vfdZXmShdLUTZsXXqlhiiy42+6k4Qirj+9Mt98sS8E1YcrqTyZf3 T08XJtgnMilGnHtD7Qs82D15V2c/88WAmKsWUIFziRGdhGiIAuVfhxKeka83vPO8UEHr XP/LzQwiW2jTaCFVpdTtvMY6PladH7SYAPtt2WVMMjWNsv1mCWJWxMOpyBsJ8iTEghN9 JlKELjHtJ5nZaUqTJX3/sSHUhmx12QtDo+cD/961y3RitE/Hy2t5MC1Pq1334fwMnDrS AUQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=j/xEM6vLjAWjy6ZJIHvYWNvgWXnKjywi5uLYZJGHzmE=; b=lXabuS3opkNcXApp+/Ly5XUbVznWKu/LkNM9xLeplnBd8ckWDmzbVPQ1CS3FHbgHgg dNhzP5VaAHPg3ddkPIogExvoPORoi3bghH4h4i1+jYVCF/8w/UHCi78Rbr3TP0BKkFqg RS17u9bgvTrUZOy0KP3Pe9s475m75KPgm0IYCz0XjzZOkvjRQMTQRAK2hTlqcJre24iA bS+LitgKKtX9bxft/6zBFmjTdjMhg+FCWOkL7S4o0goKHNUb9Rc8MNpBnVbPrdClEq2s USBmELvozcoHpI92LJ5sz1b3czfApV/CpfIX3nwlkooT6zmOHqbL0qsPqU6/wWky/FVC q4eA== X-Gm-Message-State: AOAM532MXAU5hC0U6l/5nNjj/uMMSaYRlCdcVyV0P/e7LiyCu+bupJ29 /fCQEclX4M8OdhwLPJ5keWo= X-Google-Smtp-Source: ABdhPJz4oxyGdR/08nX1VxHXHYuwzyeQyGS/2mhveDoCpTNyVWX4rnmOH/VJihHjp8CUCDJrKwSlMA== X-Received: by 2002:a1c:7313:: with SMTP id d19mr6988317wmb.183.1635860572542; Tue, 02 Nov 2021 06:42:52 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton , Richard Henderson Subject: [PULL 02/41] MAINTAINERS: Add entries to cover MIPS CPS / GIC hardware Date: Tue, 2 Nov 2021 14:42:01 +0100 Message-Id: <20211102134240.3036524-3-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860575565100001 MIPS CPS and GIC models are unrelated to the TCG frontend. Move them as new sections under the 'Devices' group. Cc: Paul Burton Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20211027041416.1237433-3-f4bug@amsat.org> --- MAINTAINERS | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index a156c4bffc0..684990b63da 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -239,14 +239,8 @@ F: target/mips/ F: configs/devices/mips*/* F: disas/mips.c F: docs/system/cpu-models-mips.rst.inc -F: hw/intc/mips_gic.c F: hw/mips/ -F: hw/misc/mips_* -F: hw/timer/mips_gictimer.c -F: include/hw/intc/mips_gic.h F: include/hw/mips/ -F: include/hw/misc/mips_* -F: include/hw/timer/mips_gictimer.h F: tests/tcg/mips/ =20 MIPS TCG CPUs (nanoMIPS ISA) @@ -2272,6 +2266,20 @@ S: Odd Fixes F: hw/intc/openpic.c F: include/hw/ppc/openpic.h =20 +MIPS CPS +M: Philippe Mathieu-Daud=C3=A9 +S: Odd Fixes +F: hw/misc/mips_* +F: include/hw/misc/mips_* + +MIPS GIC +M: Philippe Mathieu-Daud=C3=A9 +S: Odd Fixes +F: hw/intc/mips_gic.c +F: hw/timer/mips_gictimer.c +F: include/hw/intc/mips_gic.h +F: include/hw/timer/mips_gictimer.h + Subsystems ---------- Overall Audio backends --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) client-ip=209.85.128.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860579; cv=none; d=zohomail.com; s=zohoarc; b=d4uxq8sCHCWpwnwS6NF9g5QFIEFyktXJ+QA3KWxaozGFjK06arjk/gfNKVf2ap5CfZQihKlmtxCAUNltAOsH3Tp//ZEGVR7DXaRATEpc0AXvrQW84umTgEun1PdU6ttK4GatpMVVFDd30kO6tpCJeHJi6aO7mvGhJxqozubODQ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860579; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+6os92o+OmHs2GzDtEOA7Zk03dLIh2eNcVK+D5fvKF4=; b=Q4ufL5Gu7IZbFuqVbte7O15dj7MtVml1CJI5FUWsgQ/e5V9bLnEcBPnjpyDKStYFJOH5budA/WzBdxE/WBGd0GltOZmB6hvo2cq6Nitd3RQJdnfS9MU8VACgAe0CtpyvO8iaKAAanxDCB0eo2hNXbzS+zOK9CPS4VjYso+LtUI0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.zohomail.com with SMTPS id 1635860579271660.9845148531109; Tue, 2 Nov 2021 06:42:59 -0700 (PDT) Received: by mail-wm1-f43.google.com with SMTP id c71-20020a1c9a4a000000b0032cdcc8cbafso2123596wme.3 for ; Tue, 02 Nov 2021 06:42:58 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id d8sm13778935wrm.76.2021.11.02.06.42.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:42:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+6os92o+OmHs2GzDtEOA7Zk03dLIh2eNcVK+D5fvKF4=; b=M50F7ZedAOyT43Qvas6r98r2sApvd+pUGx2bIem5C++4ohuRVm9dej3ljT385ZySZ9 jE0GLQ5lAFd2zM8XjN3qP+Q2gn3GWC8PSnup5rwFuXkrcIYK79sIi3FIzsrcn3q/RIiE rpogVifDeKrZTrayBIbyGnxoACNJqv+yIO/rBmcFgSIJ4/YqQr729M3SAWkfE199Qm28 aGp36yq89lsOVCbT7UYx3dMKYH2O5BQsQfzK7hzOFe0psHg1UatLC6O7BKgPh0l11sS+ VsjrIfXj0fn6swPixW1vYuh2CFvG/G6v3LJbiDlwamZx/td77TfXQj4pmh3bgKCaZw0Q mhow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=+6os92o+OmHs2GzDtEOA7Zk03dLIh2eNcVK+D5fvKF4=; b=MqVhB22MOqzDdV+d1P/ib58gS9+mp7xFoPicP4wqNRUgXZeQtL9vK2BDJeWReH3uxS 2uVSLFQ2tIyE5mAHu94fxa143AYfnPoODmikAJcVZJIkPaPQ7PWVjc+yP6NqRoc/HILs AhftPhpU2lk2LarzzaF1jpDRI0cmg/QFQ23k1GhqsnI7fem/gYeI0YPyDSPALaOw5+Ix PURtq6Vj+i1UwgSqwzL4rbfjt54F9uD64s0gmxB56SX3p59Fdc/cTHP3sKBsae7hwXAM jtwe9wXJ92rfX3blcLAIk2cJ7JOX3Kec1ttFh2XF4yic4ukkNr5eC2eGxPIHZ6mB3SYP e28g== X-Gm-Message-State: AOAM532YixMwXBB0zAKN6b1P/93wgUZ5fQBZfvNLiNm0EscRNS5VNrsf t6kiytYcc6VcG9w1s4P+ICs= X-Google-Smtp-Source: ABdhPJwKfTSj9Qqa62cVgvMBaJwTaywTMxZ0oj+o1PM2/BqILseVxdAmAmCX7XLFb7xkr8q1mfelkQ== X-Received: by 2002:a1c:f601:: with SMTP id w1mr7069392wmc.112.1635860577525; Tue, 02 Nov 2021 06:42:57 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 03/41] MAINTAINERS: Split MIPS TCG frontend vs MIPS machines/hardware Date: Tue, 2 Nov 2021 14:42:02 +0100 Message-Id: <20211102134240.3036524-4-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860579816100001 Hardware emulated models don't belong to the TCG MAINTAINERS section. Move them to a new 'Overall MIPS Machines' section in the 'MIPS Machines' group. Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211004092515.3819836-4-f4bug@amsat.org> Reviewed-by: Richard Henderson --- MAINTAINERS | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 684990b63da..d58885d9b91 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -236,11 +236,8 @@ R: Jiaxun Yang R: Aleksandar Rikalo S: Odd Fixes F: target/mips/ -F: configs/devices/mips*/* F: disas/mips.c F: docs/system/cpu-models-mips.rst.inc -F: hw/mips/ -F: include/hw/mips/ F: tests/tcg/mips/ =20 MIPS TCG CPUs (nanoMIPS ISA) @@ -1169,6 +1166,13 @@ F: hw/microblaze/petalogix_ml605_mmu.c =20 MIPS Machines ------------- +Overall MIPS Machines +M: Philippe Mathieu-Daud=C3=A9 +S: Odd Fixes +F: configs/devices/mips*/* +F: hw/mips/ +F: include/hw/mips/ + Jazz M: Herv=C3=A9 Poussineau R: Aleksandar Rikalo --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) client-ip=209.85.221.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860584; cv=none; d=zohomail.com; s=zohoarc; b=b9Aef5EBqmBeiCNAgXW69Bfbsgar2D+zIAOOMTPbQ8T0MgOMLc1FBbTXGFF2JjxG6B2YdNmki4iOkWmZbeu6mMKN9CX/zrHZQEwHhyCe73wfrRgWme+0k/K9zZ+JJVfDy8hRs1o5qB6OJD1B6da60OHP3rlObBLR/E0fRixxRV8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860584; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9kD5AmlRz7msVGq9htNUWCOsA1AE3Dw4ZHbCNXBATxA=; b=P8V1PHr6zwbh9eylABp8k3uA34AVqANDZsoGKiICvE+pZn7i84glejk7XUg5gvqYAmo9CUXRgFcp+bMVTUFH9/ppAyejiVhF8ZSh+kLHbXYIzyTsGbOwo4uCzkcisEmYhv7EVHUEjsH2mdK2O22Eeoc8uIymZQWgabKqHV6aQ3o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) by mx.zohomail.com with SMTPS id 1635860584167976.5249268699644; Tue, 2 Nov 2021 06:43:04 -0700 (PDT) Received: by mail-wr1-f43.google.com with SMTP id d24so2814232wra.0 for ; Tue, 02 Nov 2021 06:43:03 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id x1sm2220087wru.40.2021.11.02.06.43.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:43:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9kD5AmlRz7msVGq9htNUWCOsA1AE3Dw4ZHbCNXBATxA=; b=Gem0gLsRrbCrAmqyoA/mxgug2PsrSsOSAQ9msDFD9yT5lilFq1NQFHdsMTIxALAwZq fpCXuiVxspsYKwsvRmyhitdTM/2cXRX68WXuoUJUjClttHlTXNe6wEyFaqUzL/wfYGwv htScOn+J93pjJbvuxTVi0bRL0pA26azJCE9GBEWqlseHaXVvyANAd9i8RJBsEyn3UvgW UgYGA0GYWgHDpANCEEA+2w2iJAv5346uG93uSK0HQZInUUv+HzEVg/cK/szNRQWxD9WI O0v7d2CZp7G51wgnNVYUFbz4Ge80sln9t7xhBirdTH0n/WJGTcGKJDA6Ldh40Ch73331 wgYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=9kD5AmlRz7msVGq9htNUWCOsA1AE3Dw4ZHbCNXBATxA=; b=cabmaUhONQOCzvMS9betiOkaSlzWp1l1E5k6ouRepFhbkyFSG2fe31pxQeLhL0HCIE 9NJV4lU3FSxhoFmBAgRHaNsd7CFQP3hFoHl7XWQr3nIClwjAvCFOatlqhNlhHy27Uxnx IrHZl91zLXSYoLxwu9OUSFF5cQvE4vbNuySUa0Ko0zXq7WjEVDjiO320gdM5Nyda2kLv EYxgfJ29E3Id1yTmDcGf3NTm9/I8wPTx3a039tJEKXWuf3+loP2NAUtR/ObfAYH6XSif fo/64/x7hxlUN5yVXy8YxsShsvniltzNmuCwIw4T1laS9YMz7rU3c4BRR1zU85ql0hZv WVww== X-Gm-Message-State: AOAM532rDNkAN/n2s2699ScpNoI13TjNr4b4sBV8PY4epuu6K3ejYH6l VEcdIDFrveQ4n7RNH93VNiY= X-Google-Smtp-Source: ABdhPJw2cKgieGqnZs0sHlwc8e3ugR3ohEzw6JNxVhM9iI1NI+gzdMmEQapR7eC4VWZHiguMa+r1dg== X-Received: by 2002:a05:6000:18ad:: with SMTP id b13mr12944591wri.195.1635860582353; Tue, 02 Nov 2021 06:43:02 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 04/41] target/mips: Fix MSA MADDV.B opcode Date: Tue, 2 Nov 2021 14:42:03 +0100 Message-Id: <20211102134240.3036524-5-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860586358100001 The result of the 'Vector Multiply and Add' opcode is incorrect with Byte vectors. Probably due to a copy/paste error, commit 7a7a162adde mistakenly used the $wt (target register) instead of $wd (destination register) as first operand. Fix that. Cc: Aleksandar Rikalo Fixes: 7a7a162adde ("target/mips: msa: Split helpers for MADDV.") Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-2-f4bug@amsat.org> --- target/mips/tcg/msa_helper.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index e40c1b70575..d978909527f 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -3231,22 +3231,22 @@ void helper_msa_maddv_b(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 - pwd->b[0] =3D msa_maddv_df(DF_BYTE, pwt->b[0], pws->b[0], pwt->b[0]= ); - pwd->b[1] =3D msa_maddv_df(DF_BYTE, pwt->b[1], pws->b[1], pwt->b[1]= ); - pwd->b[2] =3D msa_maddv_df(DF_BYTE, pwt->b[2], pws->b[2], pwt->b[2]= ); - pwd->b[3] =3D msa_maddv_df(DF_BYTE, pwt->b[3], pws->b[3], pwt->b[3]= ); - pwd->b[4] =3D msa_maddv_df(DF_BYTE, pwt->b[4], pws->b[4], pwt->b[4]= ); - pwd->b[5] =3D msa_maddv_df(DF_BYTE, pwt->b[5], pws->b[5], pwt->b[5]= ); - pwd->b[6] =3D msa_maddv_df(DF_BYTE, pwt->b[6], pws->b[6], pwt->b[6]= ); - pwd->b[7] =3D msa_maddv_df(DF_BYTE, pwt->b[7], pws->b[7], pwt->b[7]= ); - pwd->b[8] =3D msa_maddv_df(DF_BYTE, pwt->b[8], pws->b[8], pwt->b[8]= ); - pwd->b[9] =3D msa_maddv_df(DF_BYTE, pwt->b[9], pws->b[9], pwt->b[9]= ); - pwd->b[10] =3D msa_maddv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10= ]); - pwd->b[11] =3D msa_maddv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11= ]); - pwd->b[12] =3D msa_maddv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12= ]); - pwd->b[13] =3D msa_maddv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13= ]); - pwd->b[14] =3D msa_maddv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14= ]); - pwd->b[15] =3D msa_maddv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15= ]); + pwd->b[0] =3D msa_maddv_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[0]= ); + pwd->b[1] =3D msa_maddv_df(DF_BYTE, pwd->b[1], pws->b[1], pwt->b[1]= ); + pwd->b[2] =3D msa_maddv_df(DF_BYTE, pwd->b[2], pws->b[2], pwt->b[2]= ); + pwd->b[3] =3D msa_maddv_df(DF_BYTE, pwd->b[3], pws->b[3], pwt->b[3]= ); + pwd->b[4] =3D msa_maddv_df(DF_BYTE, pwd->b[4], pws->b[4], pwt->b[4]= ); + pwd->b[5] =3D msa_maddv_df(DF_BYTE, pwd->b[5], pws->b[5], pwt->b[5]= ); + pwd->b[6] =3D msa_maddv_df(DF_BYTE, pwd->b[6], pws->b[6], pwt->b[6]= ); + pwd->b[7] =3D msa_maddv_df(DF_BYTE, pwd->b[7], pws->b[7], pwt->b[7]= ); + pwd->b[8] =3D msa_maddv_df(DF_BYTE, pwd->b[8], pws->b[8], pwt->b[8]= ); + pwd->b[9] =3D msa_maddv_df(DF_BYTE, pwd->b[9], pws->b[9], pwt->b[9]= ); + pwd->b[10] =3D msa_maddv_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10= ]); + pwd->b[11] =3D msa_maddv_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11= ]); + pwd->b[12] =3D msa_maddv_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12= ]); + pwd->b[13] =3D msa_maddv_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13= ]); + pwd->b[14] =3D msa_maddv_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14= ]); + pwd->b[15] =3D msa_maddv_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15= ]); } =20 void helper_msa_maddv_h(CPUMIPSState *env, --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) client-ip=209.85.128.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860588; cv=none; d=zohomail.com; s=zohoarc; b=LHVn9jZz27m+7JEBVC5tTklteG7j3i22B/kci7DQ3x26Vl/i+G5H8eVdcAtks3Gg38jnH/omBDnLnwmeel5IWh3WwLAov2g1cgnNfhCPCZ9D2QCe384jQzEnwDMT30aFuLGEKL4y7xZIaMFDezm/W/OCHVm9pDv/sT0g1fXigvM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860588; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6dXKSNpYGewwfpnXz1YgG+6eErPA0FIbda+5/Dd3C5g=; b=FhboiYT0nEItELtosUF2Bd5YIGgeERhfMWk9MM3sphBeefQiolk796TJ7RKIpj0HO1bFcI7t90C56BAbpnzC8H+IcRmKOwMsAjsT1hBY4MOzjHZ1LovsQoak0W9cXB3iQCzM2nbBwpLBWTeremRsX900VeT6FOOQ0WBdACKKPTs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) by mx.zohomail.com with SMTPS id 1635860588854511.2961509080849; Tue, 2 Nov 2021 06:43:08 -0700 (PDT) Received: by mail-wm1-f48.google.com with SMTP id z11-20020a1c7e0b000000b0030db7b70b6bso1985050wmc.1 for ; Tue, 02 Nov 2021 06:43:08 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id c15sm16766933wrs.19.2021.11.02.06.43.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:43:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6dXKSNpYGewwfpnXz1YgG+6eErPA0FIbda+5/Dd3C5g=; b=b9UAQnQZQab86APzpfpcvO0M/Fa8dIqLEit+0s7t6W0i4EtDJHEozLcK3fvxFizG3Q KrD5IpkAJoPZ4rmWLttM7pJbBwcxo9h3GeHQgvv7pM+WYT0fwW/O3JZlarUX+5JpYt8G YAIqw4s2uTvf5creyTGHhYnlbKmZwkMK3Rvk7A8GOPSTCKyGs2y/JT3/UUr4EMU6DJjJ lEXW+R4CnxWu62SBRMscF36mSbGo+LUW7TTFBUy4CSRT45A6E5agT6vlfz6qlTqZlTyr ineRF4tgvnJOPD4Ij6adlidepPkkVm5sOA42gnJ1X/77xTdAHG3XbL+sfEtZWF3+sLiw VJgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=6dXKSNpYGewwfpnXz1YgG+6eErPA0FIbda+5/Dd3C5g=; b=Im6OEgR88HLaQcfbdbxFlyUmGMD6tyFT56y+vTBbhfNu/94jwurbzp5PvGhez9/Z1c KaBB5YBubTxvWGAz1Yvy0VBc6C9aWlcbE4i0hrsVnbCbfzx4gB42VtQDeMvhiPLZrCjq cq9K5i+fCjxdhHrgWRMW41uWnG6esKF6532rTmzT+iKrI6/w4OSNFDo+vt+R6FGh0bFh kZdKgEkNvli+MrOYfnzSMVPriUN2eAH5Pc95TxeS7fFswxefzCBKsGrYlFSHrzWh7IvZ Z3irgCjhzvorKBl5lc35VTqEKdZrz7gz8rdLodh06yTgQu83HIjpGC/BzwNQ6PIwDaXu jGxA== X-Gm-Message-State: AOAM5324jz8v/VtAPqRgmyWeOb/p3J+2jwB/B715ALzPHsaJyY7NSAeU efxXEh52v/hxHsS2RWyZ00Y= X-Google-Smtp-Source: ABdhPJyxSu+8lrB7QqU/tDSeqOrupljLfiZLrxAG5wCvlWK8AKc9Wax51h+9ei7AazJoCRYJYn186A== X-Received: by 2002:a1c:1fcf:: with SMTP id f198mr7176406wmf.66.1635860587060; Tue, 02 Nov 2021 06:43:07 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 05/41] target/mips: Fix MSA MSUBV.B opcode Date: Tue, 2 Nov 2021 14:42:04 +0100 Message-Id: <20211102134240.3036524-6-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860591214100001 The result of the 'Vector Multiply and Subtract' opcode is incorrect with Byte vectors. Probably due to a copy/paste error, commit 5f148a02327 mistakenly used the $wt (target register) instead of $wd (destination register) as first operand. Fix that. Cc: Aleksandar Rikalo Fixes: 5f148a02327 ("target/mips: msa: Split helpers for MSUBV.") Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-3-f4bug@amsat.org> --- target/mips/tcg/msa_helper.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index d978909527f..5667b1f0a15 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -3303,22 +3303,22 @@ void helper_msa_msubv_b(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 - pwd->b[0] =3D msa_msubv_df(DF_BYTE, pwt->b[0], pws->b[0], pwt->b[0]= ); - pwd->b[1] =3D msa_msubv_df(DF_BYTE, pwt->b[1], pws->b[1], pwt->b[1]= ); - pwd->b[2] =3D msa_msubv_df(DF_BYTE, pwt->b[2], pws->b[2], pwt->b[2]= ); - pwd->b[3] =3D msa_msubv_df(DF_BYTE, pwt->b[3], pws->b[3], pwt->b[3]= ); - pwd->b[4] =3D msa_msubv_df(DF_BYTE, pwt->b[4], pws->b[4], pwt->b[4]= ); - pwd->b[5] =3D msa_msubv_df(DF_BYTE, pwt->b[5], pws->b[5], pwt->b[5]= ); - pwd->b[6] =3D msa_msubv_df(DF_BYTE, pwt->b[6], pws->b[6], pwt->b[6]= ); - pwd->b[7] =3D msa_msubv_df(DF_BYTE, pwt->b[7], pws->b[7], pwt->b[7]= ); - pwd->b[8] =3D msa_msubv_df(DF_BYTE, pwt->b[8], pws->b[8], pwt->b[8]= ); - pwd->b[9] =3D msa_msubv_df(DF_BYTE, pwt->b[9], pws->b[9], pwt->b[9]= ); - pwd->b[10] =3D msa_msubv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10= ]); - pwd->b[11] =3D msa_msubv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11= ]); - pwd->b[12] =3D msa_msubv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12= ]); - pwd->b[13] =3D msa_msubv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13= ]); - pwd->b[14] =3D msa_msubv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14= ]); - pwd->b[15] =3D msa_msubv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15= ]); + pwd->b[0] =3D msa_msubv_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[0]= ); + pwd->b[1] =3D msa_msubv_df(DF_BYTE, pwd->b[1], pws->b[1], pwt->b[1]= ); + pwd->b[2] =3D msa_msubv_df(DF_BYTE, pwd->b[2], pws->b[2], pwt->b[2]= ); + pwd->b[3] =3D msa_msubv_df(DF_BYTE, pwd->b[3], pws->b[3], pwt->b[3]= ); + pwd->b[4] =3D msa_msubv_df(DF_BYTE, pwd->b[4], pws->b[4], pwt->b[4]= ); + pwd->b[5] =3D msa_msubv_df(DF_BYTE, pwd->b[5], pws->b[5], pwt->b[5]= ); + pwd->b[6] =3D msa_msubv_df(DF_BYTE, pwd->b[6], pws->b[6], pwt->b[6]= ); + pwd->b[7] =3D msa_msubv_df(DF_BYTE, pwd->b[7], pws->b[7], pwt->b[7]= ); + pwd->b[8] =3D msa_msubv_df(DF_BYTE, pwd->b[8], pws->b[8], pwt->b[8]= ); + pwd->b[9] =3D msa_msubv_df(DF_BYTE, pwd->b[9], pws->b[9], pwt->b[9]= ); + pwd->b[10] =3D msa_msubv_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10= ]); + pwd->b[11] =3D msa_msubv_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11= ]); + pwd->b[12] =3D msa_msubv_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12= ]); + pwd->b[13] =3D msa_msubv_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13= ]); + pwd->b[14] =3D msa_msubv_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14= ]); + pwd->b[15] =3D msa_msubv_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15= ]); } =20 void helper_msa_msubv_h(CPUMIPSState *env, --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860593; cv=none; d=zohomail.com; s=zohoarc; b=iQYp8cVDzfjWYxWbjzAe6bIYo3VsWjniA6NKgf+339nBBSxkXNT8IlNy9V7yVDuu8vA2YXZvuKPpyogMEN9hfu7LXvfuVhpcHDZ9hnAoPFd1Ht5YtVyS/au5sgW6AUF0/+QtbvdQTNBxBcI7g0rmatvK5DyPgzXohDyKs8qFGvc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860593; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+/Q/nSxAuHlXOdojOuByNBLGz7XClzU1ZplGkXdajAo=; b=LfVyU3F1qXDstRZRuo2UcYNP4rRcBsKNSK8skrYYXZ4VmEzn4boBJHMuub56pM/fQiLTjktM/KU9sSv7c2zYe/61urh8S3AvxKW9ctwC5OhvNuteLE+7Ua8E6cBdHoV8hb9aRBAgv+y1CuCjENqRUNdi0O+HCWUddFzqRJZcDHw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) by mx.zohomail.com with SMTPS id 163586059340333.306227892820175; Tue, 2 Nov 2021 06:43:13 -0700 (PDT) Received: by mail-wr1-f51.google.com with SMTP id u18so33416992wrg.5 for ; Tue, 02 Nov 2021 06:43:12 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id o20sm2493624wmq.47.2021.11.02.06.43.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:43:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+/Q/nSxAuHlXOdojOuByNBLGz7XClzU1ZplGkXdajAo=; b=GZuBFBhQl/iJ2xjJfGP0496QSXIwBGCftp52KiNCfLnNo3vRKhaeDVtkywWcPtW6Kl Ddv+ImPCiKsgxuyQu89+BMfBbhenG3DJzMPWVZ64JBKiaGx7fNAlMUWoYWuaNZh1bAH9 D/bd5XTRTAn38on8aJZtcSwB8UGnh3Ht8WtQtdYyWONCX/g9znAtctLvx7JbNqUBrzHd mopmC5hGYilkQ+ZLGJAflxH1cfN1n8St2XH9IV2bAtQ+akzYchENbnelccAX0LY3p6Ch MuE0H14Dm7m+AR7SaQ0r+Lfesz/oizyK5JpdmjabApVlsVfvXcJe7Nknaa+VJBbiVlYY DxdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=+/Q/nSxAuHlXOdojOuByNBLGz7XClzU1ZplGkXdajAo=; b=PDo/YQw8JUNSUrkIq958ilbSvmd/7Nt9WNuWolqBC8nWg5NWxZHN69fFFILnmbHfkQ 7MiaCc0GNpUemRFOMzM5x3WO26lhcOFzMTSbYYNfyXjfKfuv5ETCLJpxtYykoRtuPahl SzaJ9z207MgqUvVlyO3QM05fR1N6eQ5sp3oCJ8yUPHcYbLdDGN3DDtGHefeEhc8t1SHa cFy+Z/ffEn3scBzBANlW4hjg4RduG+MsOBHrYFk7X+hLvOappgy1jdKHb5XgcYzRHX0c 7joGQg24x/QsC2Kh3H9C9GXRdHVIxwliKY8tQcRYCtSGPNc4Im/yytfwy1AHuAhI+ogW MCOw== X-Gm-Message-State: AOAM530Tw9i5QsOINXshCc4u+tQJwYJTAIGV8J63EhtF6NAZP5N2fRIv L/tWX1HjwD4xbSA4Cy7ZHhM= X-Google-Smtp-Source: ABdhPJwRdJP8UPFKxxTJ3DGMMfslstX2hCU/194kof1zRYCVVWCS7/moVreSKjhdfSXqTVhFqjt0mw== X-Received: by 2002:a5d:4d81:: with SMTP id b1mr4720753wru.366.1635860591632; Tue, 02 Nov 2021 06:43:11 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 06/41] target/mips: Adjust style in msa_translate_init() Date: Tue, 2 Nov 2021 14:42:05 +0100 Message-Id: <20211102134240.3036524-7-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860595533100001 While the first 'off' variable assignment is unused, it helps to better understand the code logic. Move the assignation where it would have been used so it is easier to compare the MSA registers based on FPU ones versus the MSA specific registers. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211023214803.522078-34-f4bug@amsat.org> --- target/mips/tcg/msa_translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 3ef912da6b8..3aa15e147c2 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -280,13 +280,15 @@ void msa_translate_init(void) int i; =20 for (i =3D 0; i < 32; i++) { - int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + int off; =20 /* * The MSA vector registers are mapped on the * scalar floating-point unit (FPU) registers. */ + off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); msa_wr_d[i * 2] =3D fpu_f64[i]; + off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); msa_wr_d[i * 2 + 1] =3D tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860598; cv=none; d=zohomail.com; s=zohoarc; b=WuAtJHa4XnYpWb5jS2s3pWpwTIQrwcDEppMWwZH3PDL3pAYfwwzmigTI9jO+/voNfs1BEQaI6irk17CRsVpV0XKOu1lG4Jy5uLW/t0AYshPqS6dVf/u38RhBCS56mSFal92bZzwqr9E0Ub4NhW28l3wz0qiaDBvMGXVXC9azDxs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860598; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cqMjHHYN10H3op3QY78nRkjwyRaM4nA6KOm3QFWkggo=; b=Nge44OopV+KHCUlqsCDRiCBnR2JWp6IEizO+p3GZzkXDm/Sm57aw/oznM0vt1wiKE5dY11Etir9l2b+ysTQF7KRvFwJibXMNzHp5bZ05PJqoeMe0zZf6zE+gMeOVS35BUi6ehX2FWTsPuKX2s4cptAd9zbbWb++Q23bXsGn3XL0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by mx.zohomail.com with SMTPS id 1635860598366153.5638642812737; Tue, 2 Nov 2021 06:43:18 -0700 (PDT) Received: by mail-wr1-f49.google.com with SMTP id b12so28953782wrh.4 for ; Tue, 02 Nov 2021 06:43:17 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id j38sm2614285wms.29.2021.11.02.06.43.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:43:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cqMjHHYN10H3op3QY78nRkjwyRaM4nA6KOm3QFWkggo=; b=ebPrOGqR+jFCdtjYa8fhw8ZKVIMlJm/11ws1hcFZ/RkzQtPq93/y1+nnxWZM50s39i GTqVfnCmuT0iJ5lV/78aUf1Wb8hpuvzHPeD/MgDIFZGsIPjEsqu0vjowbaAm4d85uYVM vaXJ7yqLtVSOfrMYxNSk7QSaX7AibPht0+goNwJ2IYp3qNB1/4MachooV9aOSyZlYSnn MO1FvBHRbcgs0Ou6I75GoLszLpa1TzVfJDGH0ySQigeBrGxfI5tfESOho3rn7Rd27nuh tNbtUKs+rngOrxyg0vUzBIzjBOB+1/czA6CQAOvH+Wpmg5inGztIfRqduToTeE5F4OD6 tu6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cqMjHHYN10H3op3QY78nRkjwyRaM4nA6KOm3QFWkggo=; b=bgAWOw17+4F+NlGLAPeN0v60mk5NvJMKi9PW3AM9wMeUgMHAFWriJOyqjP6Hkgkl4J GWPfpnTWmsduZUc4SRo61niU/O1XpIV3PqVtXCLxzqfnh2sI+XBeKEB8foQ9pCntcVH0 zPv1RBj5jMOwcgO7WqFRjcOpoZ0SOCXXRGMEn3mxzQvc17gq50mkDumDKe+JmNYyuP8o x9XlK8HN7TgJeurqCa9nRg1mMDQRLWcFC/CIOLJ4mO/ZIMC/LN/urduC27xjKOCIh41T 7UcLLG4r/6aVASgbfk+yIgaCiNJvAjLorzU/ucMU8YMKs2rWl5T29fwRhLZwqhiOwlI2 SvcA== X-Gm-Message-State: AOAM530exZYzBIIRKZItgLRFY4n+eKlvkNWsNbjHYSi6+LD7f/iPqKHi DrWKLzqMO5Mi3NYkV4DdcRk= X-Google-Smtp-Source: ABdhPJzhwyo4vZwVoFFnQrj8JV+RIiOW+tnhV5PN8fc6Qfmi8wi1FwUG4OHZ2AS3v0oaB0xBE7Rz1g== X-Received: by 2002:adf:ded0:: with SMTP id i16mr42517579wrn.335.1635860596651; Tue, 02 Nov 2021 06:43:16 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 07/41] target/mips: Use dup_const() to simplify Date: Tue, 2 Nov 2021 14:42:06 +0100 Message-Id: <20211102134240.3036524-8-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860600238100001 The dup_const() helper makes the code easier to follow, use it. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20211028210843.2120802-5-f4bug@amsat.org> --- target/mips/tcg/msa_translate.c | 23 +++-------------------- 1 file changed, 3 insertions(+), 20 deletions(-) diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 3aa15e147c2..b135c58fd4f 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -315,28 +315,11 @@ static void gen_check_zero_element(TCGv tresult, uint= 8_t df, uint8_t wt, { /* generates tcg ops to check if any element is 0 */ /* Note this function only works with MSA_WRLEN =3D 128 */ - uint64_t eval_zero_or_big =3D 0; - uint64_t eval_big =3D 0; + uint64_t eval_zero_or_big =3D dup_const(df, 1); + uint64_t eval_big =3D eval_zero_or_big << ((8 << df) - 1); TCGv_i64 t0 =3D tcg_temp_new_i64(); TCGv_i64 t1 =3D tcg_temp_new_i64(); - switch (df) { - case DF_BYTE: - eval_zero_or_big =3D 0x0101010101010101ULL; - eval_big =3D 0x8080808080808080ULL; - break; - case DF_HALF: - eval_zero_or_big =3D 0x0001000100010001ULL; - eval_big =3D 0x8000800080008000ULL; - break; - case DF_WORD: - eval_zero_or_big =3D 0x0000000100000001ULL; - eval_big =3D 0x8000000080000000ULL; - break; - case DF_DOUBLE: - eval_zero_or_big =3D 0x0000000000000001ULL; - eval_big =3D 0x8000000000000000ULL; - break; - } + tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big); tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]); tcg_gen_andi_i64(t0, t0, eval_big); --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) client-ip=209.85.128.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860603; cv=none; d=zohomail.com; s=zohoarc; b=UTh0fEeC0ASfNMoCGDStDJEdvjTn4AlkAspADwFWBs1tCrQj8pHioxJUFolUG+9cz4ISjkEdbspbKLNra/eH/2S4welkkbtiE2mxAuCoSHay3Lvk6CE+av5XS4Ze4hI/s7hLFGcda+fUia0cCi/Lxl0VjG2kJW9ydx/SNmdq2mc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860603; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vrlE266b7OXg2/V52v1brIFbPFZKEknGt9V0I3M5muc=; b=nSOe8p4JmzzCcN54v8kaH6wnCQ9o/hc3NX4mqfxh3TWhryve/TAU4V4XoT/f4qrkOCwzCYweuqNLKShzvIqzWbS19hCXBjoK8yOyP6ONOX0xWdTqA+vRp96monRe+XB8orh5yQ1S/Cj018hmAllxGlQX5zF/TeWpREGwLs6NDFg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) by mx.zohomail.com with SMTPS id 1635860603044515.2868327083959; Tue, 2 Nov 2021 06:43:23 -0700 (PDT) Received: by mail-wm1-f50.google.com with SMTP id z200so14804701wmc.1 for ; Tue, 02 Nov 2021 06:43:22 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-6-f4bug@amsat.org> --- target/mips/tcg/msa_translate.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index b135c58fd4f..e0ccd8c1cb8 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -295,19 +295,24 @@ void msa_translate_init(void) } } =20 -static inline int check_msa_access(DisasContext *ctx) +/* + * Check if MSA is enabled. + * This function is always called with MSA available. + * If MSA is disabled, raise an exception. + */ +static inline bool check_msa_enabled(DisasContext *ctx) { if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && !(ctx->hflags & MIPS_HFLAG_F64))) { gen_reserved_instruction(ctx); - return 0; + return false; } =20 if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { generate_exception_end(ctx, EXCP_MSADIS); - return 0; + return false; } - return 1; + return true; } =20 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, @@ -339,7 +344,9 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, in= t s16, TCGCond cond) { TCGv_i64 t0; =20 - check_msa_access(ctx); + if (!check_msa_enabled(ctx)) { + return true; + } =20 if (ctx->hflags & MIPS_HFLAG_BMASK) { gen_reserved_instruction(ctx); @@ -371,7 +378,9 @@ static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *= a) =20 static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool i= f_not) { - check_msa_access(ctx); + if (!check_msa_enabled(ctx)) { + return true; + } =20 if (ctx->hflags & MIPS_HFLAG_BMASK) { gen_reserved_instruction(ctx); @@ -2143,7 +2152,9 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) { uint32_t opcode =3D ctx->opcode; =20 - check_msa_access(ctx); + if (!check_msa_enabled(ctx)) { + return true; + } =20 switch (MASK_MSA_MINOR(opcode)) { case OPC_MSA_I8_00: --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) client-ip=209.85.128.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860607; cv=none; d=zohomail.com; s=zohoarc; b=m5SmvgFt6nlG9FMBDu793FSxEmyqIWK864BvG6y0NuoCftARz3f5lqnRytfWs9/HU0XWx953U3R6LYZCEhk8TJyiyS1T00aLVnPvo0qYO4BtDgpUZms35EpewQJ7FYRrKdZe1cTiNqzQabVJhsOtPUQdP9TCN51fhsTCiFyspSY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860607; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pGmk5nM4J97afcci2ysvn5KSokS31yrMASYWBaOPBcc=; b=BXyiBzkmSo8ceiR00z5Ydhq4piJ44it2sfypwb91hCp64436rbqywpNO1R0GfUK4YUXDyQGl2J+HPf8UOJyD2dd+zpwGUUTMox8l7wO4snVbRE8DNKrv29h6LBMhZgI7IoNRpX8K8fprm2ZGGFgdJdSeAmroMWka8PBK0oZvs44= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.zohomail.com with SMTPS id 1635860607723130.2257508691116; Tue, 2 Nov 2021 06:43:27 -0700 (PDT) Received: by mail-wm1-f49.google.com with SMTP id d72-20020a1c1d4b000000b00331140f3dc8so2128438wmd.1 for ; Tue, 02 Nov 2021 06:43:27 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-7-f4bug@amsat.org> --- target/mips/tcg/msa_translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index e0ccd8c1cb8..56a0148fec2 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -1791,10 +1791,10 @@ static void gen_msa_3rf(DisasContext *ctx) case OPC_MULR_Q_df: case OPC_MADDR_Q_df: case OPC_MSUBR_Q_df: - tdf =3D tcg_constant_i32(df + 1); + tdf =3D tcg_constant_i32(DF_HALF + df); break; default: - tdf =3D tcg_constant_i32(df + 2); + tdf =3D tcg_constant_i32(DF_WORD + df); break; } =20 @@ -2023,7 +2023,7 @@ static void gen_msa_2rf(DisasContext *ctx) TCGv_i32 twd =3D tcg_const_i32(wd); TCGv_i32 tws =3D tcg_const_i32(ws); /* adjust df value for floating-point instruction */ - TCGv_i32 tdf =3D tcg_constant_i32(df + 2); + TCGv_i32 tdf =3D tcg_constant_i32(DF_WORD + df); =20 switch (MASK_MSA_2RF(ctx->opcode)) { case OPC_FCLASS_df: --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) client-ip=209.85.128.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860612; cv=none; d=zohomail.com; s=zohoarc; b=IFNEvqgyR2qLAXKqE1nQzQEXgyOmrsL7/cIlBMG3E1CknXomjGF5Ykf/JkFs2pOslDLjDgwxHXJHwLgViPuRkClElEBQ4Y1BA2fEwJz5pruYAuL+JILVypUQNftKFEKFSYPO1VPUtn4aWaJuWJ/OQvK7FRUESHZ7/GhHJzFz0PM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860612; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1SfrBjy49GnKzoXBRmaEQRcOCSJ40ZiUUIclKR8kQN4=; b=VQ5/BVTpCq1V8u4noCux7t4tzjmAKLzRaHUv7O9QiH3AxemZYGBi+XxHJFu4hFn4KaQ+TYEKOUG/cLJNWl9V+3MoH/bSM/9tYZwhyVhGYojCosy4hsGjHgosUVvNROR5hvoOJY4g3l8nY0CjkQi7/ldlV0cKbQEQFu1PDv4Jm6I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.zohomail.com with SMTPS id 1635860612459841.3192510614466; Tue, 2 Nov 2021 06:43:32 -0700 (PDT) Received: by mail-wm1-f49.google.com with SMTP id g191-20020a1c9dc8000000b0032fbf912885so2127243wme.4 for ; Tue, 02 Nov 2021 06:43:31 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id w15sm8149451wrk.77.2021.11.02.06.43.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:43:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1SfrBjy49GnKzoXBRmaEQRcOCSJ40ZiUUIclKR8kQN4=; b=fHcvO5D1C2RFpXlVe9FRXaVeuLFnjrcBjuFl+9BxuyH4ZK3LLhdZKo+sl/7FFUEUqQ qSMlXsEAmi24KqMNWD6kDs8VICt228DsIpUjkkLEgUsd99oIG8SURzeHv/+e5F9Vd72R b2wlhp7PFW7MouMX4qA/hNPyNarH/q7rFxaMlGtONX79emy9BqCaYhvkzQq5B6qpyo2k MXILgf1BQSq/+SortFXSxYzBlJ6eB+bzr995p74v8U2RMjeZkLlpx8xHEuJ8d5R+fW+j VvZVSZMeqa/6Kqw/oHl6xCpsymZXe1MHFEDYpiK4Fm8XJHdvLj+fKUPvHu2Ysymp0qkY d0iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=1SfrBjy49GnKzoXBRmaEQRcOCSJ40ZiUUIclKR8kQN4=; b=l0HMOvjNpwZ0/GKHx0NgqheW421Kbbe5g8COg3FwXIX53xM4W7W2XIDL77RQDJeUZo 8d1wP6QbNeTVtGH9Wu6VdmYAwo7QX82KunYiaMLI91SqwwQBl5lqinEx8JrdIDDh2Ers Zs1im03ok4eeIYZAesnOyXugLJQqJ73R4j49b3LvV1yr1Vg1WQCQwcdFXgXbrhNQGFtH coUWrIPgaHFFRSG5gJwo+I2Ei+rzZL+cDjn1jKWYxJ0P+WEeFND1CJSTvxLhsiJUwRA2 fB3CeGP6kCaSHmjMP6BZiNHDV/iDBSujLzQMEZkUWmpPA4ug5x74XLr2XQ9Pkdk1vAnM USjQ== X-Gm-Message-State: AOAM530rpIiG1GWa2W96jI0LmjpVfpXJmFCQQXbT0qXRCsoVnfHd0x/3 8hvO+QfOHPbZ40s4zl1P3I8= X-Google-Smtp-Source: ABdhPJz+0Dn+GnEtcRruEBFv6zuE/espbwUJkixfrdvlyVSaFN/sbcfe4w7lJ5naEDX1sK1lRb2ytw== X-Received: by 2002:a05:600c:24d:: with SMTP id 13mr6742727wmj.156.1635860610772; Tue, 02 Nov 2021 06:43:30 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 10/41] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Date: Tue, 2 Nov 2021 14:42:09 +0100 Message-Id: <20211102134240.3036524-11-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860614151100001 This 'shift amount' format is not always 16-bit, so name it generically as 'sa'. This will help to unify the various arg_msa decodetree generated structures. Rename the @bz format -> @bz_v (specific @bz with df=3D3) and @bz_df -> @bz (generic @bz). Since we modify &msa_bz, re-align its arguments, so the other structures added in the following commits stay visually aligned. Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-8-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 15 +++++++-------- target/mips/tcg/msa_translate.c | 20 ++++++++++---------- 2 files changed, 17 insertions(+), 18 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 74d99f6862c..56419a24eb9 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -13,19 +13,18 @@ =20 &r rs rt rd sa =20 -&msa_bz df wt s16 +&msa_bz df wt sa =20 @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r -@bz ...... ... .. wt:5 s16:16 &msa_bz df=3D3 -@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz +@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3D3 +@bz ...... ... df:2 wt:5 sa:16 &msa_bz =20 LSA 000000 ..... ..... ..... 000 .. 000101 @lsa DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa =20 -BZ_V 010001 01011 ..... ................ @bz -BNZ_V 010001 01111 ..... ................ @bz - -BZ_x 010001 110 .. ..... ................ @bz_df -BNZ_x 010001 111 .. ..... ................ @bz_df +BZ_V 010001 01011 ..... ................ @bz_v +BNZ_V 010001 01111 ..... ................ @bz_v +BZ 010001 110 .. ..... ................ @bz +BNZ 010001 111 .. ..... ................ @bz =20 MSA 011110 -------------------------- diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 56a0148fec2..8311730f0a5 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -340,7 +340,7 @@ static void gen_check_zero_element(TCGv tresult, uint8_= t df, uint8_t wt, tcg_temp_free_i64(t1); } =20 -static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond) +static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond) { TCGv_i64 t0; =20 @@ -358,7 +358,7 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, in= t s16, TCGCond cond) tcg_gen_trunc_i64_tl(bcond, t0); tcg_temp_free_i64(t0); =20 - ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; + ctx->btarget =3D ctx->base.pc_next + (sa << 2) + 4; =20 ctx->hflags |=3D MIPS_HFLAG_BC; ctx->hflags |=3D MIPS_HFLAG_BDS32; @@ -368,15 +368,15 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, = int s16, TCGCond cond) =20 static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a) { - return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_EQ); + return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_EQ); } =20 static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a) { - return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_NE); + return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_NE); } =20 -static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool i= f_not) +static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int sa, bool if= _not) { if (!check_msa_enabled(ctx)) { return true; @@ -389,21 +389,21 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, in= t wt, int s16, bool if_not) =20 gen_check_zero_element(bcond, df, wt, if_not ? TCG_COND_EQ : TCG_COND_= NE); =20 - ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; + ctx->btarget =3D ctx->base.pc_next + (sa << 2) + 4; ctx->hflags |=3D MIPS_HFLAG_BC; ctx->hflags |=3D MIPS_HFLAG_BDS32; =20 return true; } =20 -static bool trans_BZ_x(DisasContext *ctx, arg_msa_bz *a) +static bool trans_BZ(DisasContext *ctx, arg_msa_bz *a) { - return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, false); + return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, false); } =20 -static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a) +static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *a) { - return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true); + return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true); } =20 static void gen_msa_i8(DisasContext *ctx) --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) client-ip=209.85.128.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860617; cv=none; d=zohomail.com; s=zohoarc; b=BgDaGqBwmtRLtny8aQd99COFb1ULsASzeOS0sQBrLH+Np43qy/nbVCQbucyrtBgu+uBpmJKDu6sNBjiTFHjZa/Fv0rw/8l1ZHc+DrboVy1gg8gS5LzB+sMlLAgdXann3MfuJlbEBch8Jc63zHIu8WKi8YeTgMsOHjKltdpMr8U8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860617; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yq0hPXTClhBJmAxr5iw2vWW8JkXa0mJtI91u85gGNks=; b=RtcCdANvfNopCBXWF1c2V5KgMYJ42MX4P2p9DhLPswPr3wl+EAWccJOqJCKtUAgXmu5qPI2D2Q2GUv+lz8iZjSIfX/Zh0fhNMj3tprzL/eElZwmrTGIZ4953PR1pD0GxCuMYwDYrV1HEhE/RAgjgeGmjjkbHK3udZBg4yCcRayM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) by mx.zohomail.com with SMTPS id 1635860617165223.34080129269273; Tue, 2 Nov 2021 06:43:37 -0700 (PDT) Received: by mail-wm1-f42.google.com with SMTP id d72-20020a1c1d4b000000b00331140f3dc8so2128803wmd.1 for ; Tue, 02 Nov 2021 06:43:36 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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Since it overlaps with the generic MSA handler, use a decodetree overlap group. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-9-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 8 +++++++- target/mips/tcg/msa_translate.c | 22 ++++++++++++++-------- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 56419a24eb9..bdfe5a24cb3 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -14,10 +14,12 @@ &r rs rt rd sa =20 &msa_bz df wt sa +&msa_ldi df wd sa =20 @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3D3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi =20 LSA 000000 ..... ..... ..... 000 .. 000101 @lsa DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa @@ -27,4 +29,8 @@ BNZ_V 010001 01111 ..... ................ = @bz_v BZ 010001 110 .. ..... ................ @bz BNZ 010001 111 .. ..... ................ @bz =20 -MSA 011110 -------------------------- +{ + LDI 011110 110 .. .......... ..... 000111 @ldi + + MSA 011110 -------------------------- +} diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 8311730f0a5..94c69a668da 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -70,7 +70,6 @@ enum { OPC_CLEI_S_df =3D (0x4 << 23) | OPC_MSA_I5_07, OPC_MINI_U_df =3D (0x5 << 23) | OPC_MSA_I5_06, OPC_CLEI_U_df =3D (0x5 << 23) | OPC_MSA_I5_07, - OPC_LDI_df =3D (0x6 << 23) | OPC_MSA_I5_07, =20 /* I8 instruction */ OPC_ANDI_B =3D (0x0 << 24) | OPC_MSA_I8_00, @@ -515,13 +514,6 @@ static void gen_msa_i5(DisasContext *ctx) case OPC_CLEI_U_df: gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm); break; - case OPC_LDI_df: - { - int32_t s10 =3D sextract32(ctx->opcode, 11, 10); - tcg_gen_movi_i32(timm, s10); - gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm); - } - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); @@ -534,6 +526,20 @@ static void gen_msa_i5(DisasContext *ctx) tcg_temp_free_i32(timm); } =20 +static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a) +{ + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_helper_msa_ldi_df(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->sa)); + + return true; +} + static void gen_msa_bit(DisasContext *ctx) { #define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) client-ip=209.85.221.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860621; cv=none; d=zohomail.com; s=zohoarc; b=Q0KjRUgiw6bit55pSnUGsdS6TzBkSwXNa0JBC6bNyMz5n4sJiEm9gwKm3mYVCbM0XbtUR0D0ClECMYmErgvpVNUyz4rLyOuokAMLtUrNHFhOYITQf+YnMbMww9QDrsL67S/BUBc/34luig3CZZHe8871S6lfI/Uv9vJPwevG4rE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860621; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+f44HY6xVp3slFuAvynWqLcpuyEsThV2J9eWl3iDpy4=; b=kcyn55ljlb9wlgv2ewYDPeayJxzMoxJZfczFUuCnC/WCIvLeA6t9cgzacDXe6rxEro/OuJZp9FsxUJcmiKkEKSkwlFfKIQjOKQ31Jw3l0Hlx1TkIeDA+c7HYm8KcMFeFl8ZXYIetiVPoEXMk6NY7yYvR9W6hZ0KdnSRFPP0jthg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) by mx.zohomail.com with SMTPS id 1635860621804513.9326002220911; Tue, 2 Nov 2021 06:43:41 -0700 (PDT) Received: by mail-wr1-f41.google.com with SMTP id i5so25754114wrb.2 for ; Tue, 02 Nov 2021 06:43:41 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id y7sm8738167wrw.55.2021.11.02.06.43.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:43:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+f44HY6xVp3slFuAvynWqLcpuyEsThV2J9eWl3iDpy4=; b=T4vQT5EwtnsBDlu8n9tfQOWn9nCXRsonnJhdwK9mh0Cgkg4DkCmqhkAgBXzJlygzbY +YiOlx84wwo9pHhqQsbix3LOpwfg4v2H0tYpYTWtpT5ez4Y9HshkViFGmdLOX4Abz+3M EGIiWLz7/g+k4wm2I+xAEcxT4nX7TbpasgalL/A5+bbWXiXrQbFOQ4t0todo7SVUF0XA LxyJStnovodtT5rT70jW2lkGml/2O1eCcmjglvEROYv27qbw4OKFxoqX0WEVRPwSpSbW pyOQe19WjbMaoIsEMO+hCHIhf0X/I9kpunbm6faiGjxcSsuhyY0OQl06acVp4A1SUOlI QW0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=+f44HY6xVp3slFuAvynWqLcpuyEsThV2J9eWl3iDpy4=; b=KsNlxiQzaL9SBAnL0gj5qGvGJxVBrEhNVBKwZR8tuM0bJKxpqvrSDiODNYC/yC9NbQ 3i1P024WEWwH46z3bEeI7pmOZjfUrojno+cc3/FH5n8i3WFL9xdlGyxkFGm+ye1WlQFX Y2MDZzCcjkoD13+Q4uZmS2LbhZguvRXypokJOF9fdLhuJRTXb3yacgFK2lG5EMXqygBb 8L3cuTqxzO0VGbL+b/VJfMOG5E1imZPy/G7Ny33HETPztD7uvyRXtHZWDSAFzR3TLPJt UVvsnjNMVALmoCrD3Ze4wPoxPqXy3ssrKLhFaMOW9n4a323mO3pax+If2CrbrVcZ/TDJ HP0Q== X-Gm-Message-State: AOAM530pXIANPJvbT39wNdcwHG8gotrGfdI3dyW5aBPAL5mEv98rX+np VQhlHgvz1xKQPLrrow4M+xM= X-Google-Smtp-Source: ABdhPJymxk7eaGpecdpntGb5KBRXiIB8cKmQ1ZWKTbTYWaHrJmQTTmuVtcIRfnJSU5fdT6w3wbDWiQ== X-Received: by 2002:a5d:64c3:: with SMTP id f3mr2902248wri.377.1635860620091; Tue, 02 Nov 2021 06:43:40 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 12/41] target/mips: Convert MSA I5 instruction format to decodetree Date: Tue, 2 Nov 2021 14:42:11 +0100 Message-Id: <20211102134240.3036524-13-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860623487100001 Convert instructions with a 5-bit immediate value to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-10-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 16 +++++ target/mips/tcg/msa_translate.c | 102 ++++++++------------------------ 2 files changed, 41 insertions(+), 77 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index bdfe5a24cb3..cd2b618684a 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -15,10 +15,13 @@ =20 &msa_bz df wt sa &msa_ldi df wd sa +&msa_i df wd ws sa =20 @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3D3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i +@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i @ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi =20 LSA 000000 ..... ..... ..... 000 .. 000101 @lsa @@ -30,6 +33,19 @@ BZ 010001 110 .. ..... ................= @bz BNZ 010001 111 .. ..... ................ @bz =20 { + ADDVI 011110 000 .. ..... ..... ..... 000110 @u5 + SUBVI 011110 001 .. ..... ..... ..... 000110 @u5 + MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5 + MAXI_U 011110 011 .. ..... ..... ..... 000110 @u5 + MINI_S 011110 100 .. ..... ..... ..... 000110 @s5 + MINI_U 011110 101 .. ..... ..... ..... 000110 @u5 + + CEQI 011110 000 .. ..... ..... ..... 000111 @s5 + CLTI_S 011110 010 .. ..... ..... ..... 000111 @s5 + CLTI_U 011110 011 .. ..... ..... ..... 000111 @u5 + CLEI_S 011110 100 .. ..... ..... ..... 000111 @s5 + CLEI_U 011110 101 .. ..... ..... ..... 000111 @u5 + LDI 011110 110 .. .......... ..... 000111 @ldi =20 MSA 011110 -------------------------- diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 94c69a668da..c5211c4e057 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -27,8 +27,6 @@ enum { OPC_MSA_I8_00 =3D 0x00 | OPC_MSA, OPC_MSA_I8_01 =3D 0x01 | OPC_MSA, OPC_MSA_I8_02 =3D 0x02 | OPC_MSA, - OPC_MSA_I5_06 =3D 0x06 | OPC_MSA, - OPC_MSA_I5_07 =3D 0x07 | OPC_MSA, OPC_MSA_BIT_09 =3D 0x09 | OPC_MSA, OPC_MSA_BIT_0A =3D 0x0A | OPC_MSA, OPC_MSA_3R_0D =3D 0x0D | OPC_MSA, @@ -58,19 +56,6 @@ enum { }; =20 enum { - /* I5 instruction df(bits 22..21) =3D _b, _h, _w, _d */ - OPC_ADDVI_df =3D (0x0 << 23) | OPC_MSA_I5_06, - OPC_CEQI_df =3D (0x0 << 23) | OPC_MSA_I5_07, - OPC_SUBVI_df =3D (0x1 << 23) | OPC_MSA_I5_06, - OPC_MAXI_S_df =3D (0x2 << 23) | OPC_MSA_I5_06, - OPC_CLTI_S_df =3D (0x2 << 23) | OPC_MSA_I5_07, - OPC_MAXI_U_df =3D (0x3 << 23) | OPC_MSA_I5_06, - OPC_CLTI_U_df =3D (0x3 << 23) | OPC_MSA_I5_07, - OPC_MINI_S_df =3D (0x4 << 23) | OPC_MSA_I5_06, - OPC_CLEI_S_df =3D (0x4 << 23) | OPC_MSA_I5_07, - OPC_MINI_U_df =3D (0x5 << 23) | OPC_MSA_I5_06, - OPC_CLEI_U_df =3D (0x5 << 23) | OPC_MSA_I5_07, - /* I8 instruction */ OPC_ANDI_B =3D (0x0 << 24) | OPC_MSA_I8_00, OPC_BMNZI_B =3D (0x0 << 24) | OPC_MSA_I8_01, @@ -314,6 +299,8 @@ static inline bool check_msa_enabled(DisasContext *ctx) return true; } =20 +typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv= _i32); + static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, TCGCond cond) { @@ -463,69 +450,34 @@ static void gen_msa_i8(DisasContext *ctx) tcg_temp_free_i32(ti8); } =20 -static void gen_msa_i5(DisasContext *ctx) +static bool trans_msa_i5(DisasContext *ctx, arg_msa_i *a, + gen_helper_piiii *gen_msa_i5) { -#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) - int8_t s5 =3D (int8_t) sextract32(ctx->opcode, 16, 5); - uint8_t u5 =3D extract32(ctx->opcode, 16, 5); - - TCGv_i32 tdf =3D tcg_const_i32(extract32(ctx->opcode, 21, 2)); - TCGv_i32 twd =3D tcg_const_i32(extract32(ctx->opcode, 11, 5)); - TCGv_i32 tws =3D tcg_const_i32(extract32(ctx->opcode, 6, 5)); - TCGv_i32 timm =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(timm, u5); - - switch (MASK_MSA_I5(ctx->opcode)) { - case OPC_ADDVI_df: - gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_SUBVI_df: - gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MAXI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MAXI_U_df: - gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MINI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MINI_U_df: - gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CEQI_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLTI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLTI_U_df: - gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLEI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLEI_U_df: - gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; + if (!check_msa_enabled(ctx)) { + return true; } =20 - tcg_temp_free_i32(tdf); - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(timm); + gen_msa_i5(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->sa)); + + return true; } =20 +TRANS(ADDVI, trans_msa_i5, gen_helper_msa_addvi_df); +TRANS(SUBVI, trans_msa_i5, gen_helper_msa_subvi_df); +TRANS(MAXI_S, trans_msa_i5, gen_helper_msa_maxi_s_df); +TRANS(MAXI_U, trans_msa_i5, gen_helper_msa_maxi_u_df); +TRANS(MINI_S, trans_msa_i5, gen_helper_msa_mini_s_df); +TRANS(MINI_U, trans_msa_i5, gen_helper_msa_mini_u_df); +TRANS(CLTI_S, trans_msa_i5, gen_helper_msa_clti_s_df); +TRANS(CLTI_U, trans_msa_i5, gen_helper_msa_clti_u_df); +TRANS(CLEI_S, trans_msa_i5, gen_helper_msa_clei_s_df); +TRANS(CLEI_U, trans_msa_i5, gen_helper_msa_clei_u_df); +TRANS(CEQI, trans_msa_i5, gen_helper_msa_ceqi_df); + static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a) { if (!check_msa_enabled(ctx)) { @@ -2168,10 +2120,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) case OPC_MSA_I8_02: gen_msa_i8(ctx); break; - case OPC_MSA_I5_06: - case OPC_MSA_I5_07: - gen_msa_i5(ctx); - break; case OPC_MSA_BIT_09: case OPC_MSA_BIT_0A: gen_msa_bit(ctx); --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id 6sm2606645wma.48.2021.11.02.06.43.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:43:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z+9Ove7K4hCPh9n5E0O/3HHiI+k3CmL9176x3r0RXoU=; b=GXlxGaFYrbGGH2+zMwF1Taomc0zBWkE2cD0WkCqPDNpGklwyssqk6SBnK9fw3sryZj BRcLc6s8cy95aXbOPsmonk5RIHHOKUW8c+SmvMvqTRMXzcEkBpKXSTz+2ZoeOXsYxgM9 iTJILX+OYz+XyNNg5qj6mVB5ueT2eDpfDGZ+LVtLpT/vdgZ5Z3LFWM0cyVkTqCuT3S/a q5tyX37JUL7treunzJgRAhDsBhYuqNtT4tji5IaIiayoPogO++hhTnjLuePMfObH/5ej QkS7rf/tamh0mgXemru/pnwpjsLGkmX++0LBScr9pPnRBmIBuYZbbydmooN92oiRq6FO 8zgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=z+9Ove7K4hCPh9n5E0O/3HHiI+k3CmL9176x3r0RXoU=; b=AdaxdJPI1ZQzDch8X3I5G0lrKQCgNv+1szzsqiYLnSYFvEEe3mJsRfCw9KOCf1bJvN 3mLXX1++kFD23CYYR6KqVh+CaT7VbCW6IVNxbOOwUL2BkOKGi6MfkTXnLRMS3pbq8qnX 33OwaPc3eSOrt02RCrbJhj56SOLL3zj7gZ9Ucq3BWcbRJNM0nUulrJ9VOPKSGAW345Ju p3BYOWVGLUU55NQ3h6D4LuBt9TNqDfvCMGCRObkNkwWkxQIsOM3KjsHDaN4nKEehowD2 E0Gk7rrsHvYcjW1cXA1zGuqpcdfKUyxyzYYTeJxALJ1fjBSbsFKn9yvtcnM0dKEnn6YU M09Q== X-Gm-Message-State: AOAM532xey5ggfJJA+Us/ayK6dlVD1zgNKhPFf+O3JzBZMPMFmpPr/4z hdQA1+ociwIf3Cg3hSvfomAfifpm3i0= X-Google-Smtp-Source: ABdhPJxaNzXCkN2kRdY3hOJdU4kxb30VLXBtzuUNTIlXyeO2pCe6AnVAPpOzSQAI/0C124edtPp3HQ== X-Received: by 2002:adf:d20e:: with SMTP id j14mr39069065wrh.220.1635860624763; Tue, 02 Nov 2021 06:43:44 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 13/41] target/mips: Convert MSA BIT instruction format to decodetree Date: Tue, 2 Nov 2021 14:42:12 +0100 Message-Id: <20211102134240.3036524-14-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860628057100001 Convert instructions with an immediate bit index and data format df/m to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20211028210843.2120802-11-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 19 ++++ target/mips/tcg/msa_translate.c | 179 +++++++++++++++----------------- 2 files changed, 101 insertions(+), 97 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index cd2b618684a..3d6c6faf688 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -16,6 +16,10 @@ &msa_bz df wt sa &msa_ldi df wd sa &msa_i df wd ws sa +&msa_bit df wd ws m + +%bit_df 16:7 !function=3Dbit_df +%bit_m 16:7 !function=3Dbit_m =20 @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3D3 @@ -23,6 +27,7 @@ @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i @ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi +@bit ...... ... ....... ws:5 wd:5 ...... &msa_bit df=3D= %bit_df m=3D%bit_m =20 LSA 000000 ..... ..... ..... 000 .. 000101 @lsa DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa @@ -48,5 +53,19 @@ BNZ 010001 111 .. ..... ................= @bz =20 LDI 011110 110 .. .......... ..... 000111 @ldi =20 + SLLI 011110 000 ....... ..... ..... 001001 @bit + SRAI 011110 001 ....... ..... ..... 001001 @bit + SRLI 011110 010 ....... ..... ..... 001001 @bit + BCLRI 011110 011 ....... ..... ..... 001001 @bit + BSETI 011110 100 ....... ..... ..... 001001 @bit + BNEGI 011110 101 ....... ..... ..... 001001 @bit + BINSLI 011110 110 ....... ..... ..... 001001 @bit + BINSRI 011110 111 ....... ..... ..... 001001 @bit + + SAT_S 011110 000 ....... ..... ..... 001010 @bit + SAT_U 011110 001 ....... ..... ..... 001010 @bit + SRARI 011110 010 ....... ..... ..... 001010 @bit + SRLRI 011110 011 ....... ..... ..... 001010 @bit + MSA 011110 -------------------------- } diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index c5211c4e057..9c1a24eb251 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -17,6 +17,9 @@ #include "fpu_helper.h" #include "internal.h" =20 +static int bit_m(DisasContext *ctx, int x); +static int bit_df(DisasContext *ctx, int x); + /* Include the auto-generated decoder. */ #include "decode-msa.c.inc" =20 @@ -27,8 +30,6 @@ enum { OPC_MSA_I8_00 =3D 0x00 | OPC_MSA, OPC_MSA_I8_01 =3D 0x01 | OPC_MSA, OPC_MSA_I8_02 =3D 0x02 | OPC_MSA, - OPC_MSA_BIT_09 =3D 0x09 | OPC_MSA, - OPC_MSA_BIT_0A =3D 0x0A | OPC_MSA, OPC_MSA_3R_0D =3D 0x0D | OPC_MSA, OPC_MSA_3R_0E =3D 0x0E | OPC_MSA, OPC_MSA_3R_0F =3D 0x0F | OPC_MSA, @@ -222,20 +223,6 @@ enum { OPC_MSUBR_Q_df =3D (0xE << 22) | OPC_MSA_3RF_1C, OPC_FSULE_df =3D (0xF << 22) | OPC_MSA_3RF_1A, OPC_FMAX_A_df =3D (0xF << 22) | OPC_MSA_3RF_1B, - - /* BIT instruction df(bits 22..16) =3D _B _H _W _D */ - OPC_SLLI_df =3D (0x0 << 23) | OPC_MSA_BIT_09, - OPC_SAT_S_df =3D (0x0 << 23) | OPC_MSA_BIT_0A, - OPC_SRAI_df =3D (0x1 << 23) | OPC_MSA_BIT_09, - OPC_SAT_U_df =3D (0x1 << 23) | OPC_MSA_BIT_0A, - OPC_SRLI_df =3D (0x2 << 23) | OPC_MSA_BIT_09, - OPC_SRARI_df =3D (0x2 << 23) | OPC_MSA_BIT_0A, - OPC_BCLRI_df =3D (0x3 << 23) | OPC_MSA_BIT_09, - OPC_SRLRI_df =3D (0x3 << 23) | OPC_MSA_BIT_0A, - OPC_BSETI_df =3D (0x4 << 23) | OPC_MSA_BIT_09, - OPC_BNEGI_df =3D (0x5 << 23) | OPC_MSA_BIT_09, - OPC_BINSLI_df =3D (0x6 << 23) | OPC_MSA_BIT_09, - OPC_BINSRI_df =3D (0x7 << 23) | OPC_MSA_BIT_09, }; =20 static const char msaregnames[][6] =3D { @@ -257,6 +244,59 @@ static const char msaregnames[][6] =3D { "w30.d0", "w30.d1", "w31.d0", "w31.d1", }; =20 +/* Encoding of Operation Field (must be indexed by CPUMIPSMSADataFormat) */ +struct dfe { + int start; + int length; + uint32_t mask; +}; + +/* + * Extract immediate from df/{m,n} format (used by ELM & BIT instructions). + * Returns the immediate value, or -1 if the format does not match. + */ +static int df_extract_val(DisasContext *ctx, int x, const struct dfe *s) +{ + for (unsigned i =3D 0; i < 4; i++) { + if (extract32(x, s->start, s->length) =3D=3D s->mask) { + return extract32(x, 0, s->start); + } + } + return -1; +} + +/* + * Extract DataField from df/{m,n} format (used by ELM & BIT instructions). + * Returns the DataField, or -1 if the format does not match. + */ +static int df_extract_df(DisasContext *ctx, int x, const struct dfe *s) +{ + for (unsigned i =3D 0; i < 4; i++) { + if (extract32(x, s->start, s->length) =3D=3D s->mask) { + return i; + } + } + return -1; +} + +static const struct dfe df_bit[] =3D { + /* Table 3.28 BIT Instruction Format */ + [DF_BYTE] =3D {3, 4, 0b1110}, + [DF_HALF] =3D {4, 3, 0b110}, + [DF_WORD] =3D {5, 2, 0b10}, + [DF_DOUBLE] =3D {6, 1, 0b0} +}; + +static int bit_m(DisasContext *ctx, int x) +{ + return df_extract_val(ctx, x, df_bit); +} + +static int bit_df(DisasContext *ctx, int x) +{ + return df_extract_df(ctx, x, df_bit); +} + static TCGv_i64 msa_wr_d[64]; =20 void msa_translate_init(void) @@ -492,90 +532,39 @@ static bool trans_LDI(DisasContext *ctx, arg_msa_ldi = *a) return true; } =20 -static void gen_msa_bit(DisasContext *ctx) +static bool trans_msa_bit(DisasContext *ctx, arg_msa_bit *a, + gen_helper_piiii *gen_msa_bit) { -#define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) - uint8_t dfm =3D (ctx->opcode >> 16) & 0x7f; - uint32_t df =3D 0, m =3D 0; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 tdf; - TCGv_i32 tm; - TCGv_i32 twd; - TCGv_i32 tws; - - if ((dfm & 0x40) =3D=3D 0x00) { - m =3D dfm & 0x3f; - df =3D DF_DOUBLE; - } else if ((dfm & 0x60) =3D=3D 0x40) { - m =3D dfm & 0x1f; - df =3D DF_WORD; - } else if ((dfm & 0x70) =3D=3D 0x60) { - m =3D dfm & 0x0f; - df =3D DF_HALF; - } else if ((dfm & 0x78) =3D=3D 0x70) { - m =3D dfm & 0x7; - df =3D DF_BYTE; - } else { - gen_reserved_instruction(ctx); - return; + if (a->df < 0) { + return false; } =20 - tdf =3D tcg_const_i32(df); - tm =3D tcg_const_i32(m); - twd =3D tcg_const_i32(wd); - tws =3D tcg_const_i32(ws); - - switch (MASK_MSA_BIT(ctx->opcode)) { - case OPC_SLLI_df: - gen_helper_msa_slli_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRAI_df: - gen_helper_msa_srai_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRLI_df: - gen_helper_msa_srli_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BCLRI_df: - gen_helper_msa_bclri_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BSETI_df: - gen_helper_msa_bseti_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BNEGI_df: - gen_helper_msa_bnegi_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BINSLI_df: - gen_helper_msa_binsli_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BINSRI_df: - gen_helper_msa_binsri_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SAT_S_df: - gen_helper_msa_sat_s_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SAT_U_df: - gen_helper_msa_sat_u_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRARI_df: - gen_helper_msa_srari_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRLRI_df: - gen_helper_msa_srlri_df(cpu_env, tdf, twd, tws, tm); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; + if (!check_msa_enabled(ctx)) { + return true; } =20 - tcg_temp_free_i32(tdf); - tcg_temp_free_i32(tm); - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); + gen_msa_bit(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->m)); + + return true; } =20 +TRANS(SLLI, trans_msa_bit, gen_helper_msa_slli_df); +TRANS(SRAI, trans_msa_bit, gen_helper_msa_srai_df); +TRANS(SRLI, trans_msa_bit, gen_helper_msa_srli_df); +TRANS(BCLRI, trans_msa_bit, gen_helper_msa_bclri_df); +TRANS(BSETI, trans_msa_bit, gen_helper_msa_bseti_df); +TRANS(BNEGI, trans_msa_bit, gen_helper_msa_bnegi_df); +TRANS(BINSLI, trans_msa_bit, gen_helper_msa_binsli_df); +TRANS(BINSRI, trans_msa_bit, gen_helper_msa_binsri_df); +TRANS(SAT_S, trans_msa_bit, gen_helper_msa_sat_u_df); +TRANS(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df); +TRANS(SRARI, trans_msa_bit, gen_helper_msa_srari_df); +TRANS(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df); + static void gen_msa_3r(DisasContext *ctx) { #define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) @@ -2120,10 +2109,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) case OPC_MSA_I8_02: gen_msa_i8(ctx); break; - case OPC_MSA_BIT_09: - case OPC_MSA_BIT_0A: - gen_msa_bit(ctx); - break; case OPC_MSA_3R_0D: case OPC_MSA_3R_0E: case OPC_MSA_3R_0F: --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) client-ip=209.85.221.54; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id e12sm1803969wrq.20.2021.11.02.06.43.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:43:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ipjpFsMVBwISznamvW72G3eAUzuzbTQFyEPgUOroDE0=; b=fvIOkjENbuBv/6tUBDs2Q7772a4ImEcSzaJU5xI4w5hNGyyRqhMs9tY4MP9QGWSYlu rLxt6jtd0VsDngiPMe63JUs0ulHRVtxwB+Nj0IshvdF41geFZ32XTprrfL+6rFnbxGas AAhBdtjKfaJoi2rKAYSu9Ze3in95JD7+8SuakSjC0U+5EPi50vn5uiPuGBcgqzShw+Fd XbuURIfgIcu/6jWwUdpQO7Gu1uFFmKWxBc2LU4a6rCn1p84wDJDlaz7hEnkqcswFigOy T4K1HRcnVaJNLxAmb/vyYdtwwakgFG95GYc+Kh8j681Eez57HIgY3QOJZCtpZMcNwsFR W6cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ipjpFsMVBwISznamvW72G3eAUzuzbTQFyEPgUOroDE0=; b=1mDHXy9JPwSZwaY4M6ii03IMQG3lU8Rk3Nh0PiwcrJiLsL7W4JPXePv7V/UsOs0e0k QBQ5vbelqLwcZ5Em635a+gpGk9u0aWXyq/SNNo+SutMM/5QkbpD9wFeUWy1rTS6RQ7Gs 9VPFEdmPIOmYEOvcM7A+eNHSzrEwFWQj1tFjHTxtoFUCeNAGkOSRqwTJFrKiqrzZrVf2 HC+ibhSrMRgLnMQZukVy7emCFwLzREyAAs6NnVvTXEDpdJwkQLNVu69Gh4MiMObTuWGG URBKwD4FDI3Dc++QgVnhk2Ip5BKxHv3ZSfPvH54SAxVhxyLcGD8JXiJNDdTOXy0QbdDN fkPg== X-Gm-Message-State: AOAM533ocJv9QM98r7wtKo1FLbA43vu97skmuQB03WRZcVe1J0yF5wh9 nCKCXCNM2dTdct1UtQeqymvWQSG7es0= X-Google-Smtp-Source: ABdhPJwkI7pIEaAYsv6ZHWGjOmUNNgRhBeNYQTz2K3ExM6yXphxQ0MCRXpmpx41NQcRaqSEzia7oBQ== X-Received: by 2002:a05:6000:1449:: with SMTP id v9mr48068418wrx.137.1635860629616; Tue, 02 Nov 2021 06:43:49 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 14/41] target/mips: Convert MSA SHF opcode to decodetree Date: Tue, 2 Nov 2021 14:42:13 +0100 Message-Id: <20211102134240.3036524-15-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860632459100001 Convert the SHF opcode (Immediate Set Shuffle Elements) to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-12-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 3 +++ target/mips/tcg/msa_translate.c | 36 +++++++++++++++++---------------- 2 files changed, 22 insertions(+), 17 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 3d6c6faf688..8e887f54ad5 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -26,6 +26,7 @@ @bz ...... ... df:2 wt:5 sa:16 &msa_bz @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i +@i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i @ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi @bit ...... ... ....... ws:5 wd:5 ...... &msa_bit df=3D= %bit_df m=3D%bit_m =20 @@ -38,6 +39,8 @@ BZ 010001 110 .. ..... ................ = @bz BNZ 010001 111 .. ..... ................ @bz =20 { + SHF 011110 .. ........ ..... ..... 000010 @i8_df + ADDVI 011110 000 .. ..... ..... ..... 000110 @u5 SUBVI 011110 001 .. ..... ..... ..... 000110 @u5 MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5 diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 9c1a24eb251..1b1d88ac646 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -60,13 +60,10 @@ enum { /* I8 instruction */ OPC_ANDI_B =3D (0x0 << 24) | OPC_MSA_I8_00, OPC_BMNZI_B =3D (0x0 << 24) | OPC_MSA_I8_01, - OPC_SHF_B =3D (0x0 << 24) | OPC_MSA_I8_02, OPC_ORI_B =3D (0x1 << 24) | OPC_MSA_I8_00, OPC_BMZI_B =3D (0x1 << 24) | OPC_MSA_I8_01, - OPC_SHF_H =3D (0x1 << 24) | OPC_MSA_I8_02, OPC_NORI_B =3D (0x2 << 24) | OPC_MSA_I8_00, OPC_BSELI_B =3D (0x2 << 24) | OPC_MSA_I8_01, - OPC_SHF_W =3D (0x2 << 24) | OPC_MSA_I8_02, OPC_XORI_B =3D (0x3 << 24) | OPC_MSA_I8_00, =20 /* VEC/2R/2RF instruction */ @@ -465,20 +462,6 @@ static void gen_msa_i8(DisasContext *ctx) case OPC_BSELI_B: gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8); break; - case OPC_SHF_B: - case OPC_SHF_H: - case OPC_SHF_W: - { - uint8_t df =3D (ctx->opcode >> 24) & 0x3; - if (df =3D=3D DF_DOUBLE) { - gen_reserved_instruction(ctx); - } else { - TCGv_i32 tdf =3D tcg_const_i32(df); - gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8); - tcg_temp_free_i32(tdf); - } - } - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); @@ -490,6 +473,25 @@ static void gen_msa_i8(DisasContext *ctx) tcg_temp_free_i32(ti8); } =20 +static bool trans_SHF(DisasContext *ctx, arg_msa_i *a) +{ + if (a->df =3D=3D DF_DOUBLE) { + return false; + } + + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_helper_msa_shf_df(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->sa)); + + return true; +} + static bool trans_msa_i5(DisasContext *ctx, arg_msa_i *a, gen_helper_piiii *gen_msa_i5) { --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860636; cv=none; d=zohomail.com; s=zohoarc; b=OPskK2ByqReNApdaDYN3/y7oJHDutixh628RQVZwYkZNYhqaqkDDW3KdoPuyivDzO4/0m2hSuqMUjNqBju397bA68lewBVTySLPoH1bZNjcfaloqtgyf3x2jNUjx9YKL64HbM5zQRYYZ0bA03JU7B2DwdVnWTGLS5Q/34N3m0VQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860636; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/blkpftsPcSQ6nROrJWlw52a9nymMffz2N9GqEnnow0=; b=RJVCtt0qnIYN7E2Fe+0HfA4khi46Fr6SSrCYs2CYNWlzApaA+cRnKy7bGXjX+HtQxHmvj9SzT2DwzqdgFEewfvx3183zo/unwmBR5jVGsyoXTcbtuu5tK5uqrf3zt6IEnh6eeWF76IEkd07j9jxBjD6pfpUZB/81dEMiQotXIis= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) by mx.zohomail.com with SMTPS id 1635860636073821.7352729111294; Tue, 2 Nov 2021 06:43:56 -0700 (PDT) Received: by mail-wr1-f51.google.com with SMTP id d5so18097361wrc.1 for ; Tue, 02 Nov 2021 06:43:55 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id b197sm2661221wmb.24.2021.11.02.06.43.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:43:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/blkpftsPcSQ6nROrJWlw52a9nymMffz2N9GqEnnow0=; b=U/k1TN3YUNhft1KkvSOh4j2XWvYABiU2oT1ZJL+wTKrpYg+WXqkOT69MV4ZubCvIhX yqEpnf2B5DydaExtNro1cy3ColkCErCqWeludEvYweeOXAA0wFPwJk59Q96R6G8O11Kl LUEk+0dpCluB6z+5SjxVOx3kxBXCA4M0ERngHKAcLTqGfe741MtZMxXOWA3nWtC7DT55 HSlAUGiqvk2SmtBy2EcSum+xro5+pRB7hS9jeSW0zenD/9NSpk3Zg26xq0M4fHumAkwg 0PWMEtdHbBFfin+fMiAH1PZ/fYayFS9t8esRCls1BOxJ/fI4vlUAyO/8JoPWKmJ3HhGE H42Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=/blkpftsPcSQ6nROrJWlw52a9nymMffz2N9GqEnnow0=; b=e1Zr/AHoLjQHsR5P/TWX42ZiAe4/bHyXA6ZkFZctLNRmXJQ+UzYA1ECEk7AHHONuZO jkTcy/QjOQhZM+6VIVu5KmDDaaZlGkklYGEnsU4mEczw3CHHKvtLpDpM/22i1YzbemsK Va+N8AwWZ5eHZ1H7q1xTnKjGjVmmVwif+9SANotsn9S59nWc3klnUQrLUtuG2sIxG3TA DY3KIWpLiqFPe4ThtEihNOEoCabvFdkzrEzGPNertGNPW7aVbgKbXnIw5SzOgLWQXddZ bFttwctD/71fYSa55nhw9UxroZfbuKpVkufmsDCd/nNJ6HVCZjMfcGfHAZVMgNB04X24 XqDg== X-Gm-Message-State: AOAM532ZdNfMY2DCUQ4jg+mun7YY4pLiaHhQXimf2MuYuv0ffxhQSj/E OJKjvkYuSXFP+g6fG17SXMA= X-Google-Smtp-Source: ABdhPJxIDb5soZpZeSzMsUGkHiDOk1EFCHdjFRPIkErIrvFVC4rtWNdEuC6fO26lymXQyST82uDGnA== X-Received: by 2002:adf:c604:: with SMTP id n4mr46108604wrg.202.1635860634369; Tue, 02 Nov 2021 06:43:54 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 15/41] target/mips: Convert MSA I8 instruction format to decodetree Date: Tue, 2 Nov 2021 14:42:14 +0100 Message-Id: <20211102134240.3036524-16-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860637034100003 Convert instructions with an 8-bit immediate value and either implicit data format or data format df to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-13-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 8 ++++ target/mips/tcg/msa_translate.c | 75 +++++++++------------------------ 2 files changed, 27 insertions(+), 56 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 8e887f54ad5..24847599a05 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -27,6 +27,7 @@ @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i @i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i +@i8 ...... .. sa:s8 ws:5 wd:5 ...... &msa_i df=3D0 @ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi @bit ...... ... ....... ws:5 wd:5 ...... &msa_bit df=3D= %bit_df m=3D%bit_m =20 @@ -39,6 +40,13 @@ BZ 010001 110 .. ..... ................= @bz BNZ 010001 111 .. ..... ................ @bz =20 { + ANDI 011110 00 ........ ..... ..... 000000 @i8 + ORI 011110 01 ........ ..... ..... 000000 @i8 + NORI 011110 10 ........ ..... ..... 000000 @i8 + XORI 011110 11 ........ ..... ..... 000000 @i8 + BMNZI 011110 00 ........ ..... ..... 000001 @i8 + BMZI 011110 01 ........ ..... ..... 000001 @i8 + BSELI 011110 10 ........ ..... ..... 000001 @i8 SHF 011110 .. ........ ..... ..... 000010 @i8_df =20 ADDVI 011110 000 .. ..... ..... ..... 000110 @u5 diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 1b1d88ac646..7e5bd783df0 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -27,9 +27,6 @@ static int bit_df(DisasContext *ctx, int x); =20 #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) enum { - OPC_MSA_I8_00 =3D 0x00 | OPC_MSA, - OPC_MSA_I8_01 =3D 0x01 | OPC_MSA, - OPC_MSA_I8_02 =3D 0x02 | OPC_MSA, OPC_MSA_3R_0D =3D 0x0D | OPC_MSA, OPC_MSA_3R_0E =3D 0x0E | OPC_MSA, OPC_MSA_3R_0F =3D 0x0F | OPC_MSA, @@ -57,15 +54,6 @@ enum { }; =20 enum { - /* I8 instruction */ - OPC_ANDI_B =3D (0x0 << 24) | OPC_MSA_I8_00, - OPC_BMNZI_B =3D (0x0 << 24) | OPC_MSA_I8_01, - OPC_ORI_B =3D (0x1 << 24) | OPC_MSA_I8_00, - OPC_BMZI_B =3D (0x1 << 24) | OPC_MSA_I8_01, - OPC_NORI_B =3D (0x2 << 24) | OPC_MSA_I8_00, - OPC_BSELI_B =3D (0x2 << 24) | OPC_MSA_I8_01, - OPC_XORI_B =3D (0x3 << 24) | OPC_MSA_I8_00, - /* VEC/2R/2RF instruction */ OPC_AND_V =3D (0x00 << 21) | OPC_MSA_VEC, OPC_OR_V =3D (0x01 << 21) | OPC_MSA_VEC, @@ -336,6 +324,7 @@ static inline bool check_msa_enabled(DisasContext *ctx) return true; } =20 +typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv= _i32); =20 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, @@ -429,50 +418,29 @@ static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *= a) return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true); } =20 -static void gen_msa_i8(DisasContext *ctx) +static bool trans_msa_i8(DisasContext *ctx, arg_msa_i *a, + gen_helper_piii *gen_msa_i8) { -#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24))) - uint8_t i8 =3D (ctx->opcode >> 16) & 0xff; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 ti8 =3D tcg_const_i32(i8); - - switch (MASK_MSA_I8(ctx->opcode)) { - case OPC_ANDI_B: - gen_helper_msa_andi_b(cpu_env, twd, tws, ti8); - break; - case OPC_ORI_B: - gen_helper_msa_ori_b(cpu_env, twd, tws, ti8); - break; - case OPC_NORI_B: - gen_helper_msa_nori_b(cpu_env, twd, tws, ti8); - break; - case OPC_XORI_B: - gen_helper_msa_xori_b(cpu_env, twd, tws, ti8); - break; - case OPC_BMNZI_B: - gen_helper_msa_bmnzi_b(cpu_env, twd, tws, ti8); - break; - case OPC_BMZI_B: - gen_helper_msa_bmzi_b(cpu_env, twd, tws, ti8); - break; - case OPC_BSELI_B: - gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; + if (!check_msa_enabled(ctx)) { + return true; } =20 - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(ti8); + gen_msa_i8(cpu_env, + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->sa)); + + return true; } =20 +TRANS(ANDI, trans_msa_i8, gen_helper_msa_andi_b); +TRANS(ORI, trans_msa_i8, gen_helper_msa_ori_b); +TRANS(NORI, trans_msa_i8, gen_helper_msa_nori_b); +TRANS(XORI, trans_msa_i8, gen_helper_msa_xori_b); +TRANS(BMNZI, trans_msa_i8, gen_helper_msa_bmnzi_b); +TRANS(BMZI, trans_msa_i8, gen_helper_msa_bmzi_b); +TRANS(BSELI, trans_msa_i8, gen_helper_msa_bseli_b); + static bool trans_SHF(DisasContext *ctx, arg_msa_i *a) { if (a->df =3D=3D DF_DOUBLE) { @@ -2106,11 +2074,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) } =20 switch (MASK_MSA_MINOR(opcode)) { - case OPC_MSA_I8_00: - case OPC_MSA_I8_01: - case OPC_MSA_I8_02: - gen_msa_i8(ctx); - break; case OPC_MSA_3R_0D: case OPC_MSA_3R_0E: case OPC_MSA_3R_0F: --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860640; cv=none; d=zohomail.com; s=zohoarc; b=G0FkDrhTSm92AXw4KYaCdXiSdzcbYGPFj97i3SRIstjDsFO6MTd3T726NdUixWsQzWZbjSByg6HfyPh5q6l83i5RFXPXBVcBGqHZq2mGtuoyUtlborDbPpg7dNkkCw8Q+PYFg0J1Qk3omyk9IAS/COK5RC9BKnsN0WuvZFFV09Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860640; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; 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Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-14-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 4 ++ target/mips/tcg/msa_translate.c | 91 ++++++++++++--------------------- 2 files changed, 36 insertions(+), 59 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 24847599a05..0aeb83d5c5b 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -22,6 +22,7 @@ %bit_m 16:7 !function=3Dbit_m =20 @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r +@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3D3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @@ -78,5 +79,8 @@ BNZ 010001 111 .. ..... ................ = @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit =20 + LD 011110 .......... ..... ..... 1000 .. @ldst + ST 011110 .......... ..... ..... 1001 .. @ldst + MSA 011110 -------------------------- } diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 7e5bd783df0..2a7fb925b07 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -41,16 +41,6 @@ enum { OPC_MSA_3RF_1B =3D 0x1B | OPC_MSA, OPC_MSA_3RF_1C =3D 0x1C | OPC_MSA, OPC_MSA_VEC =3D 0x1E | OPC_MSA, - - /* MI10 instruction */ - OPC_LD_B =3D (0x20) | OPC_MSA, - OPC_LD_H =3D (0x21) | OPC_MSA, - OPC_LD_W =3D (0x22) | OPC_MSA, - OPC_LD_D =3D (0x23) | OPC_MSA, - OPC_ST_B =3D (0x24) | OPC_MSA, - OPC_ST_H =3D (0x25) | OPC_MSA, - OPC_ST_W =3D (0x26) | OPC_MSA, - OPC_ST_D =3D (0x27) | OPC_MSA, }; =20 enum { @@ -324,9 +314,19 @@ static inline bool check_msa_enabled(DisasContext *ctx) return true; } =20 +typedef void gen_helper_piv(TCGv_ptr, TCGv_i32, TCGv); typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv= _i32); =20 +#define TRANS_DF_x(TYPE, NAME, trans_func, gen_func) \ + static gen_helper_p##TYPE * const NAME##_tab[4] =3D { \ + gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d \ + }; \ + TRANS(NAME, trans_func, NAME##_tab[a->df]) + +#define TRANS_DF_iv(NAME, trans_func, gen_func) \ + TRANS_DF_x(iv, NAME, trans_func, gen_func) + static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, TCGCond cond) { @@ -2096,55 +2096,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) case OPC_MSA_VEC: gen_msa_vec(ctx); break; - case OPC_LD_B: - case OPC_LD_H: - case OPC_LD_W: - case OPC_LD_D: - case OPC_ST_B: - case OPC_ST_H: - case OPC_ST_W: - case OPC_ST_D: - { - int32_t s10 =3D sextract32(ctx->opcode, 16, 10); - uint8_t rs =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - uint8_t df =3D (ctx->opcode >> 0) & 0x3; - - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv taddr =3D tcg_temp_new(); - gen_base_offset_addr(ctx, taddr, rs, s10 << df); - - switch (MASK_MSA_MINOR(opcode)) { - case OPC_LD_B: - gen_helper_msa_ld_b(cpu_env, twd, taddr); - break; - case OPC_LD_H: - gen_helper_msa_ld_h(cpu_env, twd, taddr); - break; - case OPC_LD_W: - gen_helper_msa_ld_w(cpu_env, twd, taddr); - break; - case OPC_LD_D: - gen_helper_msa_ld_d(cpu_env, twd, taddr); - break; - case OPC_ST_B: - gen_helper_msa_st_b(cpu_env, twd, taddr); - break; - case OPC_ST_H: - gen_helper_msa_st_h(cpu_env, twd, taddr); - break; - case OPC_ST_W: - gen_helper_msa_st_w(cpu_env, twd, taddr); - break; - case OPC_ST_D: - gen_helper_msa_st_d(cpu_env, twd, taddr); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free(taddr); - } - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); @@ -2154,6 +2105,28 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) return true; } =20 +static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, + gen_helper_piv *gen_msa_ldst) +{ + TCGv taddr; + + if (!check_msa_enabled(ctx)) { + return true; + } + + taddr =3D tcg_temp_new(); + + gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df); + gen_msa_ldst(cpu_env, tcg_constant_i32(a->wd), taddr); + + tcg_temp_free(taddr); + + return true; +} + +TRANS_DF_iv(LD, trans_msa_ldst, gen_helper_msa_ld); +TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st); + static bool trans_LSA(DisasContext *ctx, arg_r *a) { return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id m125sm2584374wmm.39.2021.11.02.06.44.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:44:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=37CQJH1M7mLS2C9WYzcFC/BbmOyawPZjqzGXIWjjpAA=; b=EYM1M6wqAgpwSwapnkFnwh6zA6aUlaJk2LrffekmNTAjSAiTRs3sGR4ajyHEHwZXpl CKSJhjuqKQVAsKNJafHeIYA0NaICAHPnp4nZ53OvOW3RLoSXCbcGSs8HNee/Fi6yPmhQ JThdK7NF1/LW3EGIpS3rcV7kDtE4T57q59gZ7rjCzsqo/eeHI+2FKMoT8f2nSBE0W91G Ep5H+yswk/cgv7+IAOffLm3AcvSSIdIQS6GCZ5AkzNohRSj2mIqRAASgfftvwEHHtbM/ HQ4U982DAuSIZIWiiV8fB12DWawyi8iKXrXkE4zEomelxOWXO9Kmjt98msau/VSsd5+4 fTCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=37CQJH1M7mLS2C9WYzcFC/BbmOyawPZjqzGXIWjjpAA=; b=QeAWDAmN1j5O7X8tHpI/9wCsB7ZmKertI2P3/97avwXJBso29OpiBD7q45s0Sr3Y+m ZoMjiL+L5PBm2Pws/bCoCzK6nrjPk0zzJ0PHVyPg5wAZk99V5dBYSTS/JdjGW4r8nJ6Y FQjmvgnnXROGk/iq5g36ahVxebduHL1C16tixPJFrWuoylJDSsuvadmuIsov8cZjFPkr /3Wq53E5pYSjTPw8ULPOvs2/8diHxjcQ10yQbb6J8Jv5fWQTZkckqd4BbaHLXQtk8UoW mmlrUMtseU3byuId+uwDi0iiVEF8trnUxaPpOV+vy/+ChMu1noT1yio7zm26m/b2ZEd5 wxaw== X-Gm-Message-State: AOAM533Xl7XoanRo1gEmatflSWoSKAC//F38D/ZptJfBv5e4+x1j3Ctt KBTb0QXXFNla+GqrDnuU49o= X-Google-Smtp-Source: ABdhPJwTyZQdWvITQGfuQNlOWHWupw3kcjLRKH4piHjRvXI4eBSSyC6JfWxagt70uuIEZko/SxmvqQ== X-Received: by 2002:a05:6000:181:: with SMTP id p1mr25116662wrx.292.1635860643952; Tue, 02 Nov 2021 06:44:03 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 17/41] target/mips: Convert MSA 2RF instruction format to decodetree Date: Tue, 2 Nov 2021 14:42:16 +0100 Message-Id: <20211102134240.3036524-18-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860646169100001 Convert 2-register floating-point operations to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-15-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 20 ++++++ target/mips/tcg/msa_translate.c | 118 +++++++++----------------------- 2 files changed, 53 insertions(+), 85 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 0aeb83d5c5b..33288b50355 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -13,6 +13,7 @@ =20 &r rs rt rd sa =20 +&msa_r df wd ws wt &msa_bz df wt sa &msa_ldi df wd sa &msa_i df wd ws sa @@ -20,11 +21,13 @@ =20 %bit_df 16:7 !function=3Dbit_df %bit_m 16:7 !function=3Dbit_m +%2r_df_w 16:1 !function=3Dplus_2 =20 @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3D3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=3D0 = df=3D%2r_df_w @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i @i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i @@ -79,6 +82,23 @@ BNZ 010001 111 .. ..... ................= @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit =20 + FCLASS 011110 110010000 . ..... ..... 011110 @2rf + FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf + FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf + FSQRT 011110 110010011 . ..... ..... 011110 @2rf + FRSQRT 011110 110010100 . ..... ..... 011110 @2rf + FRCP 011110 110010101 . ..... ..... 011110 @2rf + FRINT 011110 110010110 . ..... ..... 011110 @2rf + FLOG2 011110 110010111 . ..... ..... 011110 @2rf + FEXUPL 011110 110011000 . ..... ..... 011110 @2rf + FEXUPR 011110 110011001 . ..... ..... 011110 @2rf + FFQL 011110 110011010 . ..... ..... 011110 @2rf + FFQR 011110 110011011 . ..... ..... 011110 @2rf + FTINT_S 011110 110011100 . ..... ..... 011110 @2rf + FTINT_U 011110 110011101 . ..... ..... 011110 @2rf + FFINT_S 011110 110011110 . ..... ..... 011110 @2rf + FFINT_U 011110 110011111 . ..... ..... 011110 @2rf + LD 011110 .......... ..... ..... 1000 .. @ldst ST 011110 .......... ..... ..... 1001 .. @ldst =20 diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 2a7fb925b07..704273dfd2f 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -20,6 +20,11 @@ static int bit_m(DisasContext *ctx, int x); static int bit_df(DisasContext *ctx, int x); =20 +static inline int plus_2(DisasContext *s, int x) +{ + return x + 2; +} + /* Include the auto-generated decoder. */ #include "decode-msa.c.inc" =20 @@ -44,7 +49,7 @@ enum { }; =20 enum { - /* VEC/2R/2RF instruction */ + /* VEC/2R instruction */ OPC_AND_V =3D (0x00 << 21) | OPC_MSA_VEC, OPC_OR_V =3D (0x01 << 21) | OPC_MSA_VEC, OPC_NOR_V =3D (0x02 << 21) | OPC_MSA_VEC, @@ -54,7 +59,6 @@ enum { OPC_BSEL_V =3D (0x06 << 21) | OPC_MSA_VEC, =20 OPC_MSA_2R =3D (0x18 << 21) | OPC_MSA_VEC, - OPC_MSA_2RF =3D (0x19 << 21) | OPC_MSA_VEC, =20 /* 2R instruction df(bits 17..16) =3D _b, _h, _w, _d */ OPC_FILL_df =3D (0x00 << 18) | OPC_MSA_2R, @@ -62,24 +66,6 @@ enum { OPC_NLOC_df =3D (0x02 << 18) | OPC_MSA_2R, OPC_NLZC_df =3D (0x03 << 18) | OPC_MSA_2R, =20 - /* 2RF instruction df(bit 16) =3D _w, _d */ - OPC_FCLASS_df =3D (0x00 << 17) | OPC_MSA_2RF, - OPC_FTRUNC_S_df =3D (0x01 << 17) | OPC_MSA_2RF, - OPC_FTRUNC_U_df =3D (0x02 << 17) | OPC_MSA_2RF, - OPC_FSQRT_df =3D (0x03 << 17) | OPC_MSA_2RF, - OPC_FRSQRT_df =3D (0x04 << 17) | OPC_MSA_2RF, - OPC_FRCP_df =3D (0x05 << 17) | OPC_MSA_2RF, - OPC_FRINT_df =3D (0x06 << 17) | OPC_MSA_2RF, - OPC_FLOG2_df =3D (0x07 << 17) | OPC_MSA_2RF, - OPC_FEXUPL_df =3D (0x08 << 17) | OPC_MSA_2RF, - OPC_FEXUPR_df =3D (0x09 << 17) | OPC_MSA_2RF, - OPC_FFQL_df =3D (0x0A << 17) | OPC_MSA_2RF, - OPC_FFQR_df =3D (0x0B << 17) | OPC_MSA_2RF, - OPC_FTINT_S_df =3D (0x0C << 17) | OPC_MSA_2RF, - OPC_FTINT_U_df =3D (0x0D << 17) | OPC_MSA_2RF, - OPC_FFINT_S_df =3D (0x0E << 17) | OPC_MSA_2RF, - OPC_FFINT_U_df =3D (0x0F << 17) | OPC_MSA_2RF, - /* 3R instruction df(bits 22..21) =3D _b, _h, _w, d */ OPC_SLL_df =3D (0x0 << 23) | OPC_MSA_3R_0D, OPC_ADDV_df =3D (0x0 << 23) | OPC_MSA_3R_0E, @@ -1930,73 +1916,38 @@ static void gen_msa_2r(DisasContext *ctx) tcg_temp_free_i32(tws); } =20 -static void gen_msa_2rf(DisasContext *ctx) +static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a, + gen_helper_piii *gen_msa_2rf) { -#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ - (op & (0xf << 17))) - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - uint8_t df =3D (ctx->opcode >> 16) & 0x1; - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - /* adjust df value for floating-point instruction */ - TCGv_i32 tdf =3D tcg_constant_i32(DF_WORD + df); - - switch (MASK_MSA_2RF(ctx->opcode)) { - case OPC_FCLASS_df: - gen_helper_msa_fclass_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTRUNC_S_df: - gen_helper_msa_ftrunc_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTRUNC_U_df: - gen_helper_msa_ftrunc_u_df(cpu_env, tdf, twd, tws); - break; - case OPC_FSQRT_df: - gen_helper_msa_fsqrt_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRSQRT_df: - gen_helper_msa_frsqrt_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRCP_df: - gen_helper_msa_frcp_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRINT_df: - gen_helper_msa_frint_df(cpu_env, tdf, twd, tws); - break; - case OPC_FLOG2_df: - gen_helper_msa_flog2_df(cpu_env, tdf, twd, tws); - break; - case OPC_FEXUPL_df: - gen_helper_msa_fexupl_df(cpu_env, tdf, twd, tws); - break; - case OPC_FEXUPR_df: - gen_helper_msa_fexupr_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFQL_df: - gen_helper_msa_ffql_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFQR_df: - gen_helper_msa_ffqr_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTINT_S_df: - gen_helper_msa_ftint_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTINT_U_df: - gen_helper_msa_ftint_u_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFINT_S_df: - gen_helper_msa_ffint_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFINT_U_df: - gen_helper_msa_ffint_u_df(cpu_env, tdf, twd, tws); - break; + if (!check_msa_enabled(ctx)) { + return true; } =20 - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); + gen_msa_2rf(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws)); + + return true; } =20 +TRANS(FCLASS, trans_msa_2rf, gen_helper_msa_fclass_df); +TRANS(FTRUNC_S, trans_msa_2rf, gen_helper_msa_fclass_df); +TRANS(FTRUNC_U, trans_msa_2rf, gen_helper_msa_ftrunc_s_df); +TRANS(FSQRT, trans_msa_2rf, gen_helper_msa_fsqrt_df); +TRANS(FRSQRT, trans_msa_2rf, gen_helper_msa_frsqrt_df); +TRANS(FRCP, trans_msa_2rf, gen_helper_msa_frcp_df); +TRANS(FRINT, trans_msa_2rf, gen_helper_msa_frint_df); +TRANS(FLOG2, trans_msa_2rf, gen_helper_msa_flog2_df); +TRANS(FEXUPL, trans_msa_2rf, gen_helper_msa_fexupl_df); +TRANS(FEXUPR, trans_msa_2rf, gen_helper_msa_fexupr_df); +TRANS(FFQL, trans_msa_2rf, gen_helper_msa_ffql_df); +TRANS(FFQR, trans_msa_2rf, gen_helper_msa_ffqr_df); +TRANS(FTINT_S, trans_msa_2rf, gen_helper_msa_ftint_s_df); +TRANS(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df); +TRANS(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df); +TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df); + static void gen_msa_vec_v(DisasContext *ctx) { #define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21))) @@ -2055,9 +2006,6 @@ static void gen_msa_vec(DisasContext *ctx) case OPC_MSA_2R: gen_msa_2r(ctx); break; - case OPC_MSA_2RF: - gen_msa_2rf(ctx); - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) client-ip=209.85.128.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860650; cv=none; d=zohomail.com; s=zohoarc; b=ZGifSwIiKYSNAlWlfp85KZKiWdH1ntMz2CrWHs0XuNNv3BNEJYByUMj9gHsHSgSQtoEhGP9/8asanAgOXh77bLbINHVw2RDoM1twlGvkgRloOgF5ptccm6HvDvHXtu8xjPILI/Y/q9s4t+BxShCmlwrK0aXRd+I0+ma5dl7m3Fk= ARC-Message-Signature: i=1; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id n9sm2963874wmq.6.2021.11.02.06.44.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:44:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/oAKn93/BmwUt+yc3dYyDptN24rOWDdTSRD3Nh266Ks=; b=EwvVN5nKv8imnjN8ar47AO9wxE/LFaVDzVjlWpXg1L7xyiVSCl0MYdTGWWA3f+j39r r1aHn5HcYMInKiYqAC7VS8UmeDKq3HzOF8KAI4VQmR+QGySnMzgah9UQgLbOGi4QmE70 TpaGL7NvcltJi72RwDg3FBSOa3h10NGnF2ULShAZZhVftPXuUN29uCxIo8NnkdUpFHGT O/lXBacLBo9XBhXaTp1QZxcMQdL5lgmm8v/pMQk3fQsda3v1iKCmQP56OwHE6vh3q/Jb 7fv/PnVB9IXv2H0d+IoQGrsSPd5Vk9ro/3/nACRIdSB+iRDvJy0lymoHJGgWYYJFCl77 GnrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=/oAKn93/BmwUt+yc3dYyDptN24rOWDdTSRD3Nh266Ks=; b=hqt/Y0xywsgReaRXTyc1vwBt25Ym4YGJxXn3p8KIJksLAD9gWgyNwLq/VX9ZSFSe7F pwJKYq3sBlajVzFwg6TX6XpkKe6eK5NP1ySxX/soDvz05o6JgjSRPv9P1hb9Jv9cWiMr UlyJ+UWm7NyIRmPfYkCUzwj2B1M5h8mt/WWTBFlAY7WObEF6E4GAy9Jl6WcNZtUe0ogq Xej0grd1d3QHDDta8FwJLXjB48U4Fo/4h0lrwpy3yGVuCkPG9Xu5OfzP2fFoKsSJzgnF k5DLk3m+7aYsctL/g9vwVNN/SdtdZp5oKdeQG3foxB8F/D6XcWTSo7nsH39+xaZNQK4m VGpA== X-Gm-Message-State: AOAM5305HF3gJ4P2ky6/kIY6y19nhIL28qqcWuDT6ozmEn5Q8kWbz2+o 1kqAp3PF935rwhwk4trNx8o= X-Google-Smtp-Source: ABdhPJyzv5s19f3FlVdpJSJ2DLWcp6vvuTYaPCaRLFEf+wWfdLbj5ec9lQ+poPPZkSBtS0i+wjf0Vg== X-Received: by 2002:a1c:7c02:: with SMTP id x2mr7068071wmc.165.1635860648833; Tue, 02 Nov 2021 06:44:08 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 18/41] target/mips: Convert MSA FILL opcode to decodetree Date: Tue, 2 Nov 2021 14:42:17 +0100 Message-Id: <20211102134240.3036524-19-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860652816100001 Convert the FILL opcode (Vector Fill from GPR) to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-16-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 2 ++ target/mips/tcg/msa_translate.c | 31 +++++++++++++++++++------------ 2 files changed, 21 insertions(+), 12 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 33288b50355..bcbc573deec 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -27,6 +27,7 @@ @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3D3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=3D0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=3D0 = df=3D%2r_df_w @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i @@ -82,6 +83,7 @@ BNZ 010001 111 .. ..... ................ = @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit =20 + FILL 011110 11000000 .. ..... ..... 011110 @2r FCLASS 011110 110010000 . ..... ..... 011110 @2rf FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 704273dfd2f..c7509088987 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -61,7 +61,6 @@ enum { OPC_MSA_2R =3D (0x18 << 21) | OPC_MSA_VEC, =20 /* 2R instruction df(bits 17..16) =3D _b, _h, _w, _d */ - OPC_FILL_df =3D (0x00 << 18) | OPC_MSA_2R, OPC_PCNT_df =3D (0x01 << 18) | OPC_MSA_2R, OPC_NLOC_df =3D (0x02 << 18) | OPC_MSA_2R, OPC_NLZC_df =3D (0x03 << 18) | OPC_MSA_2R, @@ -1847,17 +1846,6 @@ static void gen_msa_2r(DisasContext *ctx) TCGv_i32 tws =3D tcg_const_i32(ws); =20 switch (MASK_MSA_2R(ctx->opcode)) { - case OPC_FILL_df: -#if !defined(TARGET_MIPS64) - /* Double format valid only for MIPS64 */ - if (df =3D=3D DF_DOUBLE) { - gen_reserved_instruction(ctx); - break; - } -#endif - gen_helper_msa_fill_df(cpu_env, tcg_constant_i32(df), - twd, tws); /* trs */ - break; case OPC_NLOC_df: switch (df) { case DF_BYTE: @@ -1916,6 +1904,25 @@ static void gen_msa_2r(DisasContext *ctx) tcg_temp_free_i32(tws); } =20 +static bool trans_FILL(DisasContext *ctx, arg_msa_r *a) +{ + if (TARGET_LONG_BITS !=3D 64 && a->df =3D=3D DF_DOUBLE) { + /* Double format valid only for MIPS64 */ + return false; + } + + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_helper_msa_fill_df(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws)); + + return true; +} + static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a, gen_helper_piii *gen_msa_2rf) { --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) client-ip=209.85.128.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860655; cv=none; d=zohomail.com; s=zohoarc; b=U2zzTIKm5DeTxQLJQa5yEmNPpHye0pDpS+gJiIn+B6SihUISlsYPcOILF5TIWYqwqsAm0f+0FpxrVS5CAWJY2a1o8pqhgiOCeCdDVrFkNAMG7Z7NfLCglwj9bwsMXWqI9dKnWklgpKyDksUIWD0508rgluPxaJf5BguGogngG08= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860655; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/h4wAQ4D6fSVZ1JTKnWt4aHzK/yFuFidxCKOCYN9BJo=; b=jLhnmVRMxPJBG+/ejTo/NtuNNepGZKC1LkKUCzgURqVilScBC0+DQZ8OLKYA7QJVGp6T3NzXtvlbcIo25QDG+fqG9nFRyAINU4+f2zPNTmRRxXXQBSEgYncxqaCEEJ90LkaZ5pfxQTjWqbH0nOaiGKS0zkn6ktzLmKz+8WRPZcc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) by mx.zohomail.com with SMTPS id 1635860655162663.0433908981029; Tue, 2 Nov 2021 06:44:15 -0700 (PDT) Received: by mail-wm1-f54.google.com with SMTP id y84-20020a1c7d57000000b00330cb84834fso1989881wmc.2 for ; Tue, 02 Nov 2021 06:44:14 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id z5sm3321784wmp.26.2021.11.02.06.44.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:44:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/h4wAQ4D6fSVZ1JTKnWt4aHzK/yFuFidxCKOCYN9BJo=; b=ET44fzymxp7c6NmOwIxtBaRk7T/HfSQqA9DEqvZeoVTqqx/WhqNs+EVWCKMCVv2GwN NZu4AZ6xMA5rBmNK7lrzYqY186fQqdooQI0/ab8HZC3a7usHW5rwPCx4ypaYGR8KEEls //dju3spp3f/Hla8tZrVg7mBF6S478jX0coiMbORDigiPFMVaQS1PcfOCzG5+KqbhQVX D240gwaGwnZ2CU4MDdcnhZcDeY2ozrc/wVNlScSvHIT9N/iQhzCuBjnVep5sckHCWQtF CEL6+TRQMoKEqu/YO9nbX+J6mlvERW3dkvBy16UcZvottjw5bTWKMtl3dPU89BgffCL3 S/hA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=/h4wAQ4D6fSVZ1JTKnWt4aHzK/yFuFidxCKOCYN9BJo=; b=AZbmIDiv6PJvGpHC0pVc3ZVyo/0sRX4CfiHpf62MwIKkLXKLIr/GlpOnlvFvZJA8ci KrKWKBUx005IlpinfH+htVBt+3SY+MbRiWeEerV//rb4EcHs6P0Z5bA5erTC0f1CCT7h dZsHZCU2tPFmiX+jVzix0WCtMSbD6+lcNIjjEiAAi1knQdvRZhhHINi6i4cjl5jyfRPr z1UWLADodndZbsRun3j8cPq4DpM8eKvo6ZQX17Otn3dBlAfk1QJXLxvOlVKtKT07X4EN VuGN06jWmnaqpVTf1iDuN8HyfOiUrWyAwDLtQf5Mp0QKdXWry4frrFeze3aaJ5R7P6V1 jXiQ== X-Gm-Message-State: AOAM5338LScGkpzdHB6v2B14+7b23cI+FCVH2ZbWVcnBK+enKzF2C3Cg VvS0yfzTFsVvemXvUDwsCfYYbdQwLvc= X-Google-Smtp-Source: ABdhPJz4s+H/vs/AwqIEYkvwg2D6C27pzhWRsezz0tnbqWdJCwMSUDEMMaI5mYGNcoL8oDWwrneEvg== X-Received: by 2002:a1c:2047:: with SMTP id g68mr7471210wmg.181.1635860653425; Tue, 02 Nov 2021 06:44:13 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 19/41] target/mips: Convert MSA 2R instruction format to decodetree Date: Tue, 2 Nov 2021 14:42:18 +0100 Message-Id: <20211102134240.3036524-20-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860657146100001 Convert 2-register operations to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-17-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 3 ++ target/mips/tcg/msa_translate.c | 91 ++++++--------------------------- 2 files changed, 19 insertions(+), 75 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index bcbc573deec..b6ac80560f6 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -84,6 +84,9 @@ BNZ 010001 111 .. ..... ................ = @bz SRLRI 011110 011 ....... ..... ..... 001010 @bit =20 FILL 011110 11000000 .. ..... ..... 011110 @2r + PCNT 011110 11000001 .. ..... ..... 011110 @2r + NLOC 011110 11000010 .. ..... ..... 011110 @2r + NLZC 011110 11000011 .. ..... ..... 011110 @2r FCLASS 011110 110010000 . ..... ..... 011110 @2rf FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index c7509088987..c6e38281a64 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -49,7 +49,7 @@ enum { }; =20 enum { - /* VEC/2R instruction */ + /* VEC instruction */ OPC_AND_V =3D (0x00 << 21) | OPC_MSA_VEC, OPC_OR_V =3D (0x01 << 21) | OPC_MSA_VEC, OPC_NOR_V =3D (0x02 << 21) | OPC_MSA_VEC, @@ -58,13 +58,6 @@ enum { OPC_BMZ_V =3D (0x05 << 21) | OPC_MSA_VEC, OPC_BSEL_V =3D (0x06 << 21) | OPC_MSA_VEC, =20 - OPC_MSA_2R =3D (0x18 << 21) | OPC_MSA_VEC, - - /* 2R instruction df(bits 17..16) =3D _b, _h, _w, _d */ - OPC_PCNT_df =3D (0x01 << 18) | OPC_MSA_2R, - OPC_NLOC_df =3D (0x02 << 18) | OPC_MSA_2R, - OPC_NLZC_df =3D (0x03 << 18) | OPC_MSA_2R, - /* 3R instruction df(bits 22..21) =3D _b, _h, _w, d */ OPC_SLL_df =3D (0x0 << 23) | OPC_MSA_3R_0D, OPC_ADDV_df =3D (0x0 << 23) | OPC_MSA_3R_0E, @@ -300,6 +293,7 @@ static inline bool check_msa_enabled(DisasContext *ctx) } =20 typedef void gen_helper_piv(TCGv_ptr, TCGv_i32, TCGv); +typedef void gen_helper_pii(TCGv_ptr, TCGv_i32, TCGv_i32); typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv= _i32); =20 @@ -312,6 +306,9 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_= i32, TCGv_i32, TCGv_i32); #define TRANS_DF_iv(NAME, trans_func, gen_func) \ TRANS_DF_x(iv, NAME, trans_func, gen_func) =20 +#define TRANS_DF_ii(NAME, trans_func, gen_func) \ + TRANS_DF_x(ii, NAME, trans_func, gen_func) + static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, TCGCond cond) { @@ -1835,75 +1832,22 @@ static void gen_msa_3rf(DisasContext *ctx) tcg_temp_free_i32(twt); } =20 -static void gen_msa_2r(DisasContext *ctx) +static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a, + gen_helper_pii *gen_msa_2r) { -#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ - (op & (0x7 << 18))) - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - uint8_t df =3D (ctx->opcode >> 16) & 0x3; - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - - switch (MASK_MSA_2R(ctx->opcode)) { - case OPC_NLOC_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_nloc_b(cpu_env, twd, tws); - break; - case DF_HALF: - gen_helper_msa_nloc_h(cpu_env, twd, tws); - break; - case DF_WORD: - gen_helper_msa_nloc_w(cpu_env, twd, tws); - break; - case DF_DOUBLE: - gen_helper_msa_nloc_d(cpu_env, twd, tws); - break; - } - break; - case OPC_NLZC_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_nlzc_b(cpu_env, twd, tws); - break; - case DF_HALF: - gen_helper_msa_nlzc_h(cpu_env, twd, tws); - break; - case DF_WORD: - gen_helper_msa_nlzc_w(cpu_env, twd, tws); - break; - case DF_DOUBLE: - gen_helper_msa_nlzc_d(cpu_env, twd, tws); - break; - } - break; - case OPC_PCNT_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_pcnt_b(cpu_env, twd, tws); - break; - case DF_HALF: - gen_helper_msa_pcnt_h(cpu_env, twd, tws); - break; - case DF_WORD: - gen_helper_msa_pcnt_w(cpu_env, twd, tws); - break; - case DF_DOUBLE: - gen_helper_msa_pcnt_d(cpu_env, twd, tws); - break; - } - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; + if (!check_msa_enabled(ctx)) { + return true; } =20 - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); + gen_msa_2r(cpu_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws)); + + return true; } =20 +TRANS_DF_ii(PCNT, trans_msa_2r, gen_helper_msa_pcnt); +TRANS_DF_ii(NLOC, trans_msa_2r, gen_helper_msa_nloc); +TRANS_DF_ii(NLZC, trans_msa_2r, gen_helper_msa_nlzc); + static bool trans_FILL(DisasContext *ctx, arg_msa_r *a) { if (TARGET_LONG_BITS !=3D 64 && a->df =3D=3D DF_DOUBLE) { @@ -2010,9 +1954,6 @@ static void gen_msa_vec(DisasContext *ctx) case OPC_BSEL_V: gen_msa_vec_v(ctx); break; - case OPC_MSA_2R: - gen_msa_2r(ctx); - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id o2sm17709609wrg.1.2021.11.02.06.44.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:44:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ITK2jAKvKvh2aGzj1uYLx351dgZJw7ejqPzY8bO8NZY=; b=ci17iVaYK2XvvuPEYq1vLOK21LudqxnYQTP1/CsCugU7g3GQIw7nNeErCtfVbnLDFE 5cU9D/J9gWnqWnpimYQL15ghaJe21FpQf6AN4OBKXSSSmddEaudLzuEDwOFnw30DFbEJ BGR8XLnD1mwENOqN1YZm8AzKpmmcrhabfrtagZtRbUzy49uzbnl9LfhrGS6KZroXD1NV nFFQSTmUpwGXRIHlpGAIyBWlYLjZJGu+ZXW/88lW09k8NAdRNBJokewZLSIUnCsJJL8W P1ziBBWOxitYYRO8O+hqgxSOZRMDYk4fS8rnRHbdX7+xUQLKlcC1VESaGN1ZMwsCVD3e hVRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ITK2jAKvKvh2aGzj1uYLx351dgZJw7ejqPzY8bO8NZY=; b=X6QcDwMtR/1QUQlva4M1+5nt7JMGogXtuTJrJYLE2OX1pjlLI0AdI3DzPsrf526F8m X/Jksilk1dGOEXQ3iJS76WUyByZeExI0+H2FwXaG3hCLC88P301DbF/sC1bj8JKsEOHJ A0dL8pK5+pXqCJwyrt0PAxOUhk1IEXrq378N/6GmVxYSps8JfWr7WnUxEytBuIWOpAn4 vB8TLdoEsR+gwUZF0L6Y6B41eMPRWZsBMnQn3PK+Dg1UtaQcYjrngMe+kcRRMhAvFuIe txuMr1nfz8AEL+/NXIkm5kyvQHEumlxlyatCVxrEhx9yjgFqrfCJNI+lSJVuX9G1Fh+W 7xPQ== X-Gm-Message-State: AOAM532RvGT3h67iQtFZGYzP0+TpKqRXLyXlvhw0pzBWyOft8FmoCYdx cvul7jb4Y610pob/n3Ks+tM= X-Google-Smtp-Source: ABdhPJyYqC2zC3R7c/rj/45vkENLjiyOOrJagYXSEr0dqOfO7IpbK+fKMEOMfUhvyeDA7LnlaqWhNA== X-Received: by 2002:a5d:6481:: with SMTP id o1mr47703211wri.60.1635860658032; Tue, 02 Nov 2021 06:44:18 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 20/41] target/mips: Convert MSA VEC instruction format to decodetree Date: Tue, 2 Nov 2021 14:42:19 +0100 Message-Id: <20211102134240.3036524-21-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860662073100001 Convert 3-register instructions with implicit data formats to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-18-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 8 +++ target/mips/tcg/msa_translate.c | 98 ++++++++------------------------- 2 files changed, 31 insertions(+), 75 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index b6ac80560f6..afcb868aade 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -27,6 +27,7 @@ @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3D3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=3D0 @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=3D0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=3D0 = df=3D%2r_df_w @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @@ -83,6 +84,13 @@ BNZ 010001 111 .. ..... ................= @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit =20 + AND_V 011110 00000 ..... ..... ..... 011110 @vec + OR_V 011110 00001 ..... ..... ..... 011110 @vec + NOR_V 011110 00010 ..... ..... ..... 011110 @vec + XOR_V 011110 00011 ..... ..... ..... 011110 @vec + BMNZ_V 011110 00100 ..... ..... ..... 011110 @vec + BMZ_V 011110 00101 ..... ..... ..... 011110 @vec + BSEL_V 011110 00110 ..... ..... ..... 011110 @vec FILL 011110 11000000 .. ..... ..... 011110 @2r PCNT 011110 11000001 .. ..... ..... 011110 @2r NLOC 011110 11000010 .. ..... ..... 011110 @2r diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index c6e38281a64..45a6b60d547 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -45,19 +45,9 @@ enum { OPC_MSA_3RF_1A =3D 0x1A | OPC_MSA, OPC_MSA_3RF_1B =3D 0x1B | OPC_MSA, OPC_MSA_3RF_1C =3D 0x1C | OPC_MSA, - OPC_MSA_VEC =3D 0x1E | OPC_MSA, }; =20 enum { - /* VEC instruction */ - OPC_AND_V =3D (0x00 << 21) | OPC_MSA_VEC, - OPC_OR_V =3D (0x01 << 21) | OPC_MSA_VEC, - OPC_NOR_V =3D (0x02 << 21) | OPC_MSA_VEC, - OPC_XOR_V =3D (0x03 << 21) | OPC_MSA_VEC, - OPC_BMNZ_V =3D (0x04 << 21) | OPC_MSA_VEC, - OPC_BMZ_V =3D (0x05 << 21) | OPC_MSA_VEC, - OPC_BSEL_V =3D (0x06 << 21) | OPC_MSA_VEC, - /* 3R instruction df(bits 22..21) =3D _b, _h, _w, d */ OPC_SLL_df =3D (0x0 << 23) | OPC_MSA_3R_0D, OPC_ADDV_df =3D (0x0 << 23) | OPC_MSA_3R_0E, @@ -517,6 +507,29 @@ TRANS(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df= ); TRANS(SRARI, trans_msa_bit, gen_helper_msa_srari_df); TRANS(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df); =20 +static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a, + gen_helper_piii *gen_msa_3r) +{ + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_msa_3r(cpu_env, + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->wt)); + + return true; +} + +TRANS(AND_V, trans_msa_3r, gen_helper_msa_and_v); +TRANS(OR_V, trans_msa_3r, gen_helper_msa_or_v); +TRANS(NOR_V, trans_msa_3r, gen_helper_msa_nor_v); +TRANS(XOR_V, trans_msa_3r, gen_helper_msa_xor_v); +TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa_bmnz_v); +TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v); +TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v); + static void gen_msa_3r(DisasContext *ctx) { #define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) @@ -1899,68 +1912,6 @@ TRANS(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_= u_df); TRANS(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df); TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df); =20 -static void gen_msa_vec_v(DisasContext *ctx) -{ -#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21))) - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - - switch (MASK_MSA_VEC(ctx->opcode)) { - case OPC_AND_V: - gen_helper_msa_and_v(cpu_env, twd, tws, twt); - break; - case OPC_OR_V: - gen_helper_msa_or_v(cpu_env, twd, tws, twt); - break; - case OPC_NOR_V: - gen_helper_msa_nor_v(cpu_env, twd, tws, twt); - break; - case OPC_XOR_V: - gen_helper_msa_xor_v(cpu_env, twd, tws, twt); - break; - case OPC_BMNZ_V: - gen_helper_msa_bmnz_v(cpu_env, twd, tws, twt); - break; - case OPC_BMZ_V: - gen_helper_msa_bmz_v(cpu_env, twd, tws, twt); - break; - case OPC_BSEL_V: - gen_helper_msa_bsel_v(cpu_env, twd, tws, twt); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); -} - -static void gen_msa_vec(DisasContext *ctx) -{ - switch (MASK_MSA_VEC(ctx->opcode)) { - case OPC_AND_V: - case OPC_OR_V: - case OPC_NOR_V: - case OPC_XOR_V: - case OPC_BMNZ_V: - case OPC_BMZ_V: - case OPC_BSEL_V: - gen_msa_vec_v(ctx); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } -} - static bool trans_MSA(DisasContext *ctx, arg_MSA *a) { uint32_t opcode =3D ctx->opcode; @@ -1989,9 +1940,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) case OPC_MSA_3RF_1C: gen_msa_3rf(ctx); break; - case OPC_MSA_VEC: - gen_msa_vec(ctx); - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) client-ip=209.85.221.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860664; cv=none; d=zohomail.com; s=zohoarc; b=c2RMPIcc0rm0Qx2Fw/QIUHV62o+1GMcnIj9Jn4kx+TT2OSOpwvy8Fx2OGBb0W7ZdWXVvufXxCHzKJOzrk+HMHnvgF20L/VIHoClQo15SGDiKhdM72rKNse1kRQUTca9Tg2krbzF1rRqT6918gXHWmt0vnFuBnMZlz7MIXjiom8U= ARC-Message-Signature: i=1; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id u6sm2510348wmc.29.2021.11.02.06.44.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:44:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jRFqNue7p0Qm34S0HJ0qJjQT9HmvoceQ86OEjAtLFvk=; b=pqiteujifMRhice6OOFylkLmfsiNwBB0OVa/FNYPS920yjVbn8728dL3eO6B/eacHw ZfG/UWnfXQBRFN5AKXmvvNiEGSXfiHoK3K4/XQjeOeGBQtpTVNIFDS5u115WP19DJ0CR cAvy+RKUCTXTqvTCqFV7mRUSNJ0KJsXVUtx93pxoYloFKwFBBZ6iRcK0CQl5TZbzK1Yt OLRB+TzHe5w1HXkq13rpQf4NaMsmxUxbQJOt0P7RN8FkRrM/UcdTdShmYeFqQTVbbBxl A+ZyVtv0CzMBy9IoJJ1z2vzewHFhG/R+EJw0gjiE2ROBt5CMOcy0cTgqYd+iLvPYn7tg oEbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=jRFqNue7p0Qm34S0HJ0qJjQT9HmvoceQ86OEjAtLFvk=; b=V06z/bfC0nkjKkNBwnpVZJiZZm05rW8g3Jkcfk6BvD4yl+1gizHTigoSyJ17w01uQp qlMX2KyrUqjxU7kGf7K7Q/xaShAaCcwS0tJayeI1MFfNaV6F2es/rNePucg8VldYaHPI RCQUqV2i7qErWJisenqx+0ccP6ygm8MiBwd3uXHQfo68f0dcVjWJtJSeAnoBI/rgoklq JPGEwyhQ5DNvQiJOimlZqd/8R+/Z9+JmvVbBfNoJ5uP7wsC3K4UC6M5PKmW7lQ/w/JBT MHpeARZCZZGL6qqZ0sZX9UxuZ6e93xkNV3pq0LmwF4WBM/U9m7SOtjRoHecxcaz8o5H9 M6MQ== X-Gm-Message-State: AOAM530YqBKt4zHFUw6l0o9NIv5vWonfcVOyEqGIwTxEQZtW/UpaP/mw 1Lf802eHVyqM1V88hfipoLI= X-Google-Smtp-Source: ABdhPJyw5l5nufgzy3+ok/UdzExCChrGpBkSiznPrES6SNvG82VFuouUX01oqVau6lC9Md5NH0a0fA== X-Received: by 2002:a05:6000:1868:: with SMTP id d8mr10860423wri.285.1635860662644; Tue, 02 Nov 2021 06:44:22 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 21/41] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Date: Tue, 2 Nov 2021 14:42:20 +0100 Message-Id: <20211102134240.3036524-22-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860666846100001 Convert 3-register floating-point or fixed-point operations to decodetree. Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20211028210843.2120802-19-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 9 +++++ target/mips/tcg/msa_translate.c | 68 ++++++++++++++------------------- 2 files changed, 38 insertions(+), 39 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index afcb868aade..f90b2d21c92 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -22,6 +22,7 @@ %bit_df 16:7 !function=3Dbit_df %bit_m 16:7 !function=3Dbit_m %2r_df_w 16:1 !function=3Dplus_2 +%3r_df_h 21:1 !function=3Dplus_1 =20 @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @@ -30,6 +31,7 @@ @vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=3D0 @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=3D0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=3D0 = df=3D%2r_df_w +@3rf_h ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=3D%3= r_df_h @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i @i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i @@ -84,6 +86,13 @@ BNZ 010001 111 .. ..... ................= @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit =20 + MUL_Q 011110 0100 . ..... ..... ..... 011100 @3rf_h + MADD_Q 011110 0101 . ..... ..... ..... 011100 @3rf_h + MSUB_Q 011110 0110 . ..... ..... ..... 011100 @3rf_h + MULR_Q 011110 1100 . ..... ..... ..... 011100 @3rf_h + MADDR_Q 011110 1101 . ..... ..... ..... 011100 @3rf_h + MSUBR_Q 011110 1110 . ..... ..... ..... 011100 @3rf_h + AND_V 011110 00000 ..... ..... ..... 011110 @vec OR_V 011110 00001 ..... ..... ..... 011110 @vec NOR_V 011110 00010 ..... ..... ..... 011110 @vec diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 45a6b60d547..65e56b23171 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -20,6 +20,11 @@ static int bit_m(DisasContext *ctx, int x); static int bit_df(DisasContext *ctx, int x); =20 +static inline int plus_1(DisasContext *s, int x) +{ + return x + 1; +} + static inline int plus_2(DisasContext *s, int x) { return x + 2; @@ -138,12 +143,9 @@ enum { OPC_FCNE_df =3D (0x3 << 22) | OPC_MSA_3RF_1C, OPC_FCLT_df =3D (0x4 << 22) | OPC_MSA_3RF_1A, OPC_FMADD_df =3D (0x4 << 22) | OPC_MSA_3RF_1B, - OPC_MUL_Q_df =3D (0x4 << 22) | OPC_MSA_3RF_1C, OPC_FCULT_df =3D (0x5 << 22) | OPC_MSA_3RF_1A, OPC_FMSUB_df =3D (0x5 << 22) | OPC_MSA_3RF_1B, - OPC_MADD_Q_df =3D (0x5 << 22) | OPC_MSA_3RF_1C, OPC_FCLE_df =3D (0x6 << 22) | OPC_MSA_3RF_1A, - OPC_MSUB_Q_df =3D (0x6 << 22) | OPC_MSA_3RF_1C, OPC_FCULE_df =3D (0x7 << 22) | OPC_MSA_3RF_1A, OPC_FEXP2_df =3D (0x7 << 22) | OPC_MSA_3RF_1B, OPC_FSAF_df =3D (0x8 << 22) | OPC_MSA_3RF_1A, @@ -157,13 +159,10 @@ enum { OPC_FSNE_df =3D (0xB << 22) | OPC_MSA_3RF_1C, OPC_FSLT_df =3D (0xC << 22) | OPC_MSA_3RF_1A, OPC_FMIN_df =3D (0xC << 22) | OPC_MSA_3RF_1B, - OPC_MULR_Q_df =3D (0xC << 22) | OPC_MSA_3RF_1C, OPC_FSULT_df =3D (0xD << 22) | OPC_MSA_3RF_1A, OPC_FMIN_A_df =3D (0xD << 22) | OPC_MSA_3RF_1B, - OPC_MADDR_Q_df =3D (0xD << 22) | OPC_MSA_3RF_1C, OPC_FSLE_df =3D (0xE << 22) | OPC_MSA_3RF_1A, OPC_FMAX_df =3D (0xE << 22) | OPC_MSA_3RF_1B, - OPC_MSUBR_Q_df =3D (0xE << 22) | OPC_MSA_3RF_1C, OPC_FSULE_df =3D (0xF << 22) | OPC_MSA_3RF_1A, OPC_FMAX_A_df =3D (0xF << 22) | OPC_MSA_3RF_1B, }; @@ -507,6 +506,22 @@ TRANS(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df= ); TRANS(SRARI, trans_msa_bit, gen_helper_msa_srari_df); TRANS(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df); =20 +static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a, + gen_helper_piiii *gen_msa_3rf) +{ + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_msa_3rf(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->wt)); + + return true; +} + static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a, gen_helper_piii *gen_msa_3r) { @@ -1682,6 +1697,13 @@ static void gen_msa_elm(DisasContext *ctx) gen_msa_elm_df(ctx, df, n); } =20 +TRANS(MUL_Q, trans_msa_3rf, gen_helper_msa_mul_q_df); +TRANS(MADD_Q, trans_msa_3rf, gen_helper_msa_madd_q_df); +TRANS(MSUB_Q, trans_msa_3rf, gen_helper_msa_msub_q_df); +TRANS(MULR_Q, trans_msa_3rf, gen_helper_msa_mulr_q_df); +TRANS(MADDR_Q, trans_msa_3rf, gen_helper_msa_maddr_q_df); +TRANS(MSUBR_Q, trans_msa_3rf, gen_helper_msa_msubr_q_df); + static void gen_msa_3rf(DisasContext *ctx) { #define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) @@ -1693,22 +1715,8 @@ static void gen_msa_3rf(DisasContext *ctx) TCGv_i32 twd =3D tcg_const_i32(wd); TCGv_i32 tws =3D tcg_const_i32(ws); TCGv_i32 twt =3D tcg_const_i32(wt); - TCGv_i32 tdf; - /* adjust df value for floating-point instruction */ - switch (MASK_MSA_3RF(ctx->opcode)) { - case OPC_MUL_Q_df: - case OPC_MADD_Q_df: - case OPC_MSUB_Q_df: - case OPC_MULR_Q_df: - case OPC_MADDR_Q_df: - case OPC_MSUBR_Q_df: - tdf =3D tcg_constant_i32(DF_HALF + df); - break; - default: - tdf =3D tcg_constant_i32(DF_WORD + df); - break; - } + TCGv_i32 tdf =3D tcg_constant_i32(DF_WORD + df); =20 switch (MASK_MSA_3RF(ctx->opcode)) { case OPC_FCAF_df: @@ -1750,24 +1758,15 @@ static void gen_msa_3rf(DisasContext *ctx) case OPC_FMADD_df: gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MUL_Q_df: - gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FCULT_df: gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt); break; case OPC_FMSUB_df: gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MADD_Q_df: - gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FCLE_df: gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MSUB_Q_df: - gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FCULE_df: gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt); break; @@ -1807,27 +1806,18 @@ static void gen_msa_3rf(DisasContext *ctx) case OPC_FMIN_df: gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MULR_Q_df: - gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FSULT_df: gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt); break; case OPC_FMIN_A_df: gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MADDR_Q_df: - gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FSLE_df: gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt); break; case OPC_FMAX_df: gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt); 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id p188sm2658002wmp.30.2021.11.02.06.44.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:44:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CV0/Pzq40wUhlGoyOS/jEmIH7yh4yuHsbpD6mx/MAR8=; b=G+7cHTWiJHYBI9rsoKdJEUhyaBLoYUZ7AyZZVIjxPgjeCkx7w7e1e8GxWErgZ3Hr2v bDkhB69gBhNTplp94rBpv6gyjQTA4483l/avJgaTm8479JnepB4JxgeW1Sd89oU+y4sT 9aW1v505IILShg6HOJ1WIdgd3oJwZ78cukqwBaz0GLY45/mgPUYPHasXqDK+OO0UEXGR OXHi64tY781+5PJKpDZhIt9goPZffrUbLX7+7LB3oRexEdIRMMnPJ/At27LagQSakfOW SU7gMIvniCpR4vK3Uqdou7GbJrLylHe+uHJQGIJrrWJbmpmFu/ZqcwyxugRFTTe6Hs2Z bvwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=CV0/Pzq40wUhlGoyOS/jEmIH7yh4yuHsbpD6mx/MAR8=; b=VtIh/95dZmVYuk4V5GkTBqQUzmNpF31D9Z1F608H2KrnRkmr+uGdKArstanvz+rceE rIUjlPEUGHJ630wysPoaIpqtOFhx0DqLg/XyWVLscaMOEYexLTAC3jWnidHn5pev6+il Ck/WEeQ1JYG5SgTlaAso2dw86dxv43mTEaibAPSoQZBs+fwMN6soXf1TyQduOWgC5Fwf sc9bjp88Vt+wLzK1WQJFImEPAjL3FBYE2aAaH6w4GXFLiMW9wjHgoB1n/95Y4d7qF+kd UD9p5t6YuCiBjHWV5hb+MiUBvVJDe4sFZjP0r3zEzRDpUG3qZxQuKu8rG9eTz1m/wsWP Xr6w== X-Gm-Message-State: AOAM530VpJqtjVMZpQhK5ms4uNsJwGWIjKQKv9QBYRWw8PhSCiL9Djad pU+YsQaHu1SDKvVV2aiUKcc= X-Google-Smtp-Source: ABdhPJw4/0d72P4hbMXJlteZECaFj/qIidNpZBvf4SygwOLvWdYNH9thICJCQ+ScEVxtdAiUy18Naw== X-Received: by 2002:a1c:f402:: with SMTP id z2mr7258136wma.53.1635860667308; Tue, 02 Nov 2021 06:44:27 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 22/41] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Date: Tue, 2 Nov 2021 14:42:21 +0100 Message-Id: <20211102134240.3036524-23-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860669651100001 Convert 3-register floating-point or fixed-point operations to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-20-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 39 ++++++ target/mips/tcg/msa_translate.c | 213 ++++++-------------------------- 2 files changed, 76 insertions(+), 176 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index f90b2d21c92..1d6ada4c142 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -23,6 +23,7 @@ %bit_m 16:7 !function=3Dbit_m %2r_df_w 16:1 !function=3Dplus_2 %3r_df_h 21:1 !function=3Dplus_1 +%3r_df_w 21:1 !function=3Dplus_2 =20 @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @@ -32,6 +33,7 @@ @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=3D0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=3D0 = df=3D%2r_df_w @3rf_h ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=3D%3= r_df_h +@3rf_w ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=3D%3= r_df_w @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i @i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i @@ -86,9 +88,46 @@ BNZ 010001 111 .. ..... ................= @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit =20 + FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w + FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w + FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf_w + FCUEQ 011110 0011 . ..... ..... ..... 011010 @3rf_w + FCLT 011110 0100 . ..... ..... ..... 011010 @3rf_w + FCULT 011110 0101 . ..... ..... ..... 011010 @3rf_w + FCLE 011110 0110 . ..... ..... ..... 011010 @3rf_w + FCULE 011110 0111 . ..... ..... ..... 011010 @3rf_w + FSAF 011110 1000 . ..... ..... ..... 011010 @3rf_w + FSUN 011110 1001 . ..... ..... ..... 011010 @3rf_w + FSEQ 011110 1010 . ..... ..... ..... 011010 @3rf_w + FSUEQ 011110 1011 . ..... ..... ..... 011010 @3rf_w + FSLT 011110 1100 . ..... ..... ..... 011010 @3rf_w + FSULT 011110 1101 . ..... ..... ..... 011010 @3rf_w + FSLE 011110 1110 . ..... ..... ..... 011010 @3rf_w + FSULE 011110 1111 . ..... ..... ..... 011010 @3rf_w + + FADD 011110 0000 . ..... ..... ..... 011011 @3rf_w + FSUB 011110 0001 . ..... ..... ..... 011011 @3rf_w + FMUL 011110 0010 . ..... ..... ..... 011011 @3rf_w + FDIV 011110 0011 . ..... ..... ..... 011011 @3rf_w + FMADD 011110 0100 . ..... ..... ..... 011011 @3rf_w + FMSUB 011110 0101 . ..... ..... ..... 011011 @3rf_w + FEXP2 011110 0111 . ..... ..... ..... 011011 @3rf_w + FEXDO 011110 1000 . ..... ..... ..... 011011 @3rf_w + FTQ 011110 1010 . ..... ..... ..... 011011 @3rf_w + FMIN 011110 1100 . ..... ..... ..... 011011 @3rf_w + FMIN_A 011110 1101 . ..... ..... ..... 011011 @3rf_w + FMAX 011110 1110 . ..... ..... ..... 011011 @3rf_w + FMAX_A 011110 1111 . ..... ..... ..... 011011 @3rf_w + + FCOR 011110 0001 . ..... ..... ..... 011100 @3rf_w + FCUNE 011110 0010 . ..... ..... ..... 011100 @3rf_w + FCNE 011110 0011 . ..... ..... ..... 011100 @3rf_w MUL_Q 011110 0100 . ..... ..... ..... 011100 @3rf_h MADD_Q 011110 0101 . ..... ..... ..... 011100 @3rf_h MSUB_Q 011110 0110 . ..... ..... ..... 011100 @3rf_h + FSOR 011110 1001 . ..... ..... ..... 011100 @3rf_w + FSUNE 011110 1010 . ..... ..... ..... 011100 @3rf_w + FSNE 011110 1011 . ..... ..... ..... 011100 @3rf_w MULR_Q 011110 1100 . ..... ..... ..... 011100 @3rf_h MADDR_Q 011110 1101 . ..... ..... ..... 011100 @3rf_h MSUBR_Q 011110 1110 . ..... ..... ..... 011100 @3rf_h diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 65e56b23171..26d05a87c89 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -47,9 +47,6 @@ enum { OPC_MSA_3R_14 =3D 0x14 | OPC_MSA, OPC_MSA_3R_15 =3D 0x15 | OPC_MSA, OPC_MSA_ELM =3D 0x19 | OPC_MSA, - OPC_MSA_3RF_1A =3D 0x1A | OPC_MSA, - OPC_MSA_3RF_1B =3D 0x1B | OPC_MSA, - OPC_MSA_3RF_1C =3D 0x1C | OPC_MSA, }; =20 enum { @@ -128,43 +125,6 @@ enum { OPC_COPY_U_df =3D (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_INSERT_df =3D (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_INSVE_df =3D (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM, - - /* 3RF instruction _df(bit 21) =3D _w, _d */ - OPC_FCAF_df =3D (0x0 << 22) | OPC_MSA_3RF_1A, - OPC_FADD_df =3D (0x0 << 22) | OPC_MSA_3RF_1B, - OPC_FCUN_df =3D (0x1 << 22) | OPC_MSA_3RF_1A, - OPC_FSUB_df =3D (0x1 << 22) | OPC_MSA_3RF_1B, - OPC_FCOR_df =3D (0x1 << 22) | OPC_MSA_3RF_1C, - OPC_FCEQ_df =3D (0x2 << 22) | OPC_MSA_3RF_1A, - OPC_FMUL_df =3D (0x2 << 22) | OPC_MSA_3RF_1B, - OPC_FCUNE_df =3D (0x2 << 22) | OPC_MSA_3RF_1C, - OPC_FCUEQ_df =3D (0x3 << 22) | OPC_MSA_3RF_1A, - OPC_FDIV_df =3D (0x3 << 22) | OPC_MSA_3RF_1B, - OPC_FCNE_df =3D (0x3 << 22) | OPC_MSA_3RF_1C, - OPC_FCLT_df =3D (0x4 << 22) | OPC_MSA_3RF_1A, - OPC_FMADD_df =3D (0x4 << 22) | OPC_MSA_3RF_1B, - OPC_FCULT_df =3D (0x5 << 22) | OPC_MSA_3RF_1A, - OPC_FMSUB_df =3D (0x5 << 22) | OPC_MSA_3RF_1B, - OPC_FCLE_df =3D (0x6 << 22) | OPC_MSA_3RF_1A, - OPC_FCULE_df =3D (0x7 << 22) | OPC_MSA_3RF_1A, - OPC_FEXP2_df =3D (0x7 << 22) | OPC_MSA_3RF_1B, - OPC_FSAF_df =3D (0x8 << 22) | OPC_MSA_3RF_1A, - OPC_FEXDO_df =3D (0x8 << 22) | OPC_MSA_3RF_1B, - OPC_FSUN_df =3D (0x9 << 22) | OPC_MSA_3RF_1A, - OPC_FSOR_df =3D (0x9 << 22) | OPC_MSA_3RF_1C, - OPC_FSEQ_df =3D (0xA << 22) | OPC_MSA_3RF_1A, - OPC_FTQ_df =3D (0xA << 22) | OPC_MSA_3RF_1B, - OPC_FSUNE_df =3D (0xA << 22) | OPC_MSA_3RF_1C, - OPC_FSUEQ_df =3D (0xB << 22) | OPC_MSA_3RF_1A, - OPC_FSNE_df =3D (0xB << 22) | OPC_MSA_3RF_1C, - OPC_FSLT_df =3D (0xC << 22) | OPC_MSA_3RF_1A, - OPC_FMIN_df =3D (0xC << 22) | OPC_MSA_3RF_1B, - OPC_FSULT_df =3D (0xD << 22) | OPC_MSA_3RF_1A, - OPC_FMIN_A_df =3D (0xD << 22) | OPC_MSA_3RF_1B, - OPC_FSLE_df =3D (0xE << 22) | OPC_MSA_3RF_1A, - OPC_FMAX_df =3D (0xE << 22) | OPC_MSA_3RF_1B, - OPC_FSULE_df =3D (0xF << 22) | OPC_MSA_3RF_1A, - OPC_FMAX_A_df =3D (0xF << 22) | OPC_MSA_3RF_1B, }; =20 static const char msaregnames[][6] =3D { @@ -1697,144 +1657,50 @@ static void gen_msa_elm(DisasContext *ctx) gen_msa_elm_df(ctx, df, n); } =20 +TRANS(FCAF, trans_msa_3rf, gen_helper_msa_fcaf_df); +TRANS(FCUN, trans_msa_3rf, gen_helper_msa_fcun_df); +TRANS(FCEQ, trans_msa_3rf, gen_helper_msa_fceq_df); +TRANS(FCUEQ, trans_msa_3rf, gen_helper_msa_fcueq_df); +TRANS(FCLT, trans_msa_3rf, gen_helper_msa_fclt_df); +TRANS(FCULT, trans_msa_3rf, gen_helper_msa_fcult_df); +TRANS(FCLE, trans_msa_3rf, gen_helper_msa_fcle_df); +TRANS(FCULE, trans_msa_3rf, gen_helper_msa_fcule_df); +TRANS(FSAF, trans_msa_3rf, gen_helper_msa_fsaf_df); +TRANS(FSUN, trans_msa_3rf, gen_helper_msa_fsun_df); +TRANS(FSEQ, trans_msa_3rf, gen_helper_msa_fseq_df); +TRANS(FSUEQ, trans_msa_3rf, gen_helper_msa_fsueq_df); +TRANS(FSLT, trans_msa_3rf, gen_helper_msa_fslt_df); +TRANS(FSULT, trans_msa_3rf, gen_helper_msa_fsult_df); +TRANS(FSLE, trans_msa_3rf, gen_helper_msa_fsle_df); +TRANS(FSULE, trans_msa_3rf, gen_helper_msa_fsule_df); + +TRANS(FADD, trans_msa_3rf, gen_helper_msa_fadd_df); +TRANS(FSUB, trans_msa_3rf, gen_helper_msa_fsub_df); +TRANS(FMUL, trans_msa_3rf, gen_helper_msa_fmul_df); +TRANS(FDIV, trans_msa_3rf, gen_helper_msa_fdiv_df); +TRANS(FMADD, trans_msa_3rf, gen_helper_msa_fmadd_df); +TRANS(FMSUB, trans_msa_3rf, gen_helper_msa_fmsub_df); +TRANS(FEXP2, trans_msa_3rf, gen_helper_msa_fexp2_df); +TRANS(FEXDO, trans_msa_3rf, gen_helper_msa_fexdo_df); +TRANS(FTQ, trans_msa_3rf, gen_helper_msa_ftq_df); +TRANS(FMIN, trans_msa_3rf, gen_helper_msa_fmin_df); +TRANS(FMIN_A, trans_msa_3rf, gen_helper_msa_fmin_a_df); +TRANS(FMAX, trans_msa_3rf, gen_helper_msa_fmax_df); +TRANS(FMAX_A, trans_msa_3rf, gen_helper_msa_fmax_a_df); + +TRANS(FCOR, trans_msa_3rf, gen_helper_msa_fcor_df); +TRANS(FCUNE, trans_msa_3rf, gen_helper_msa_fcune_df); +TRANS(FCNE, trans_msa_3rf, gen_helper_msa_fcne_df); TRANS(MUL_Q, trans_msa_3rf, gen_helper_msa_mul_q_df); TRANS(MADD_Q, trans_msa_3rf, gen_helper_msa_madd_q_df); TRANS(MSUB_Q, trans_msa_3rf, gen_helper_msa_msub_q_df); +TRANS(FSOR, trans_msa_3rf, gen_helper_msa_fsor_df); +TRANS(FSUNE, trans_msa_3rf, gen_helper_msa_fsune_df); +TRANS(FSNE, trans_msa_3rf, gen_helper_msa_fsne_df); TRANS(MULR_Q, trans_msa_3rf, gen_helper_msa_mulr_q_df); TRANS(MADDR_Q, trans_msa_3rf, gen_helper_msa_maddr_q_df); TRANS(MSUBR_Q, trans_msa_3rf, gen_helper_msa_msubr_q_df); =20 -static void gen_msa_3rf(DisasContext *ctx) -{ -#define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) - uint8_t df =3D (ctx->opcode >> 21) & 0x1; - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - /* adjust df value for floating-point instruction */ - TCGv_i32 tdf =3D tcg_constant_i32(DF_WORD + df); - - switch (MASK_MSA_3RF(ctx->opcode)) { - case OPC_FCAF_df: - gen_helper_msa_fcaf_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FADD_df: - gen_helper_msa_fadd_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCUN_df: - gen_helper_msa_fcun_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUB_df: - gen_helper_msa_fsub_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCOR_df: - gen_helper_msa_fcor_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCEQ_df: - gen_helper_msa_fceq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMUL_df: - gen_helper_msa_fmul_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCUNE_df: - gen_helper_msa_fcune_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCUEQ_df: - gen_helper_msa_fcueq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FDIV_df: - gen_helper_msa_fdiv_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCNE_df: - gen_helper_msa_fcne_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCLT_df: - gen_helper_msa_fclt_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMADD_df: - gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCULT_df: - gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMSUB_df: - gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCLE_df: - gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCULE_df: - gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FEXP2_df: - gen_helper_msa_fexp2_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSAF_df: - gen_helper_msa_fsaf_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FEXDO_df: - gen_helper_msa_fexdo_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUN_df: - gen_helper_msa_fsun_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSOR_df: - gen_helper_msa_fsor_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSEQ_df: - gen_helper_msa_fseq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FTQ_df: - gen_helper_msa_ftq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUNE_df: - gen_helper_msa_fsune_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUEQ_df: - gen_helper_msa_fsueq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSNE_df: - gen_helper_msa_fsne_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSLT_df: - gen_helper_msa_fslt_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMIN_df: - gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSULT_df: - gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMIN_A_df: - gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSLE_df: - gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMAX_df: - gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSULE_df: - gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMAX_A_df: - gen_helper_msa_fmax_a_df(cpu_env, tdf, twd, tws, twt); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); -} - static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a, gen_helper_pii *gen_msa_2r) { @@ -1925,11 +1791,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) case OPC_MSA_ELM: gen_msa_elm(ctx); break; - case OPC_MSA_3RF_1A: - case OPC_MSA_3RF_1B: - case OPC_MSA_3RF_1C: - gen_msa_3rf(ctx); - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860673; cv=none; d=zohomail.com; s=zohoarc; b=OPj4q2/TNI02gFy+/p0CPlNc3kcUKRGupuq9fFVDhE4ZKNCI+jWz2zj4/8K3IbJOxyU7A/REts+5qy+j+cI5aKi1SigruE0CiGGBBJu31vltBrvqsJ0Ql2iSvn4frdU1uux1GIAptclVwBPH4Ug63UN80dP/cpRmycQm6JYTIRM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Note, the format definition could be named @3rf_b (for 3R with a df field BYTE-based) but since the instruction class is named '3R', we simply call the format @3r to ease reviewing the msa.decode file. However we directly call the trans_msa_3rf() function, which handles the BYTE-based df field. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-21-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 6 ++++++ target/mips/tcg/msa_translate.c | 17 +++++------------ 2 files changed, 11 insertions(+), 12 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 1d6ada4c142..4b14acce26f 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -32,6 +32,7 @@ @vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=3D0 @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=3D0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=3D0 = df=3D%2r_df_w +@3r ...... ... df:2 wt:5 ws:5 wd:5 ...... &msa_r @3rf_h ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=3D%3= r_df_h @3rf_w ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=3D%3= r_df_w @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @@ -88,6 +89,11 @@ BNZ 010001 111 .. ..... ................= @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit =20 + SLD 011110 000 .. ..... ..... ..... 010100 @3r + SPLAT 011110 001 .. ..... ..... ..... 010100 @3r + + VSHF 011110 000 .. ..... ..... ..... 010101 @3r + FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf_w diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 26d05a87c89..ddc0bd08ddf 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -58,15 +58,12 @@ enum { OPC_SUBS_S_df =3D (0x0 << 23) | OPC_MSA_3R_11, OPC_MULV_df =3D (0x0 << 23) | OPC_MSA_3R_12, OPC_DOTP_S_df =3D (0x0 << 23) | OPC_MSA_3R_13, - OPC_SLD_df =3D (0x0 << 23) | OPC_MSA_3R_14, - OPC_VSHF_df =3D (0x0 << 23) | OPC_MSA_3R_15, OPC_SRA_df =3D (0x1 << 23) | OPC_MSA_3R_0D, OPC_SUBV_df =3D (0x1 << 23) | OPC_MSA_3R_0E, OPC_ADDS_A_df =3D (0x1 << 23) | OPC_MSA_3R_10, OPC_SUBS_U_df =3D (0x1 << 23) | OPC_MSA_3R_11, OPC_MADDV_df =3D (0x1 << 23) | OPC_MSA_3R_12, OPC_DOTP_U_df =3D (0x1 << 23) | OPC_MSA_3R_13, - OPC_SPLAT_df =3D (0x1 << 23) | OPC_MSA_3R_14, OPC_SRAR_df =3D (0x1 << 23) | OPC_MSA_3R_15, OPC_SRL_df =3D (0x2 << 23) | OPC_MSA_3R_0D, OPC_MAX_S_df =3D (0x2 << 23) | OPC_MSA_3R_0E, @@ -505,6 +502,11 @@ TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa= _bmnz_v); TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v); TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v); =20 +TRANS(SLD, trans_msa_3rf, gen_helper_msa_sld_df); +TRANS(SPLAT, trans_msa_3rf, gen_helper_msa_splat_df); + +TRANS(VSHF, trans_msa_3rf, gen_helper_msa_vshf_df); + static void gen_msa_3r(DisasContext *ctx) { #define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) @@ -1255,12 +1257,6 @@ static void gen_msa_3r(DisasContext *ctx) break; } break; - case OPC_SLD_df: - gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_VSHF_df: - gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_SUBV_df: switch (df) { case DF_BYTE: @@ -1293,9 +1289,6 @@ static void gen_msa_3r(DisasContext *ctx) break; } break; - case OPC_SPLAT_df: - gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_SUBSUS_U_df: switch (df) { case DF_BYTE: --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) client-ip=209.85.221.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860678; cv=none; d=zohomail.com; s=zohoarc; b=F+878Kj9QKvrnAd6uu+8Qux0G6MlVdiCAay7BsuWeqosVcWWatN3VxchGDjCJc19F+GirMCeIFkf1V148lEeADXNuMgIznbp27pVVGDQl2vAwACw4AxyZ/dInBG/flsJOLdLYqXJZl89zxUnO2S3csOZj0b8Uzg99dQtgmF79ng= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860678; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NpNslA/nzr/Xf6IxLZdAaJ9lqh01yYVCliSq/aR63zE=; b=M1xJLopeWnuLiskuAR0p5TYYx1R0IgrKCHnXvy42g0OaWbdcDKtduiRR+RZvxhjbHZ/EF+HI+6+pJv0EwzGd6xWABzCLS8sFc5XdEkq2a4aY/9/E16ODAEHDF90h23KjRHTQOSfbedDaeUsKCJPo0gZFrc07SsGZepcf3mESJCs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) by mx.zohomail.com with SMTPS id 1635860678739278.06939080973564; Tue, 2 Nov 2021 06:44:38 -0700 (PDT) Received: by mail-wr1-f43.google.com with SMTP id u1so1801914wru.13 for ; Tue, 02 Nov 2021 06:44:38 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id b10sm1361208wrt.36.2021.11.02.06.44.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:44:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NpNslA/nzr/Xf6IxLZdAaJ9lqh01yYVCliSq/aR63zE=; b=QRwJRcUKwgyaDyyagPeEO0wAi4XNhL49tD/3D8t8XjK1BT0w+QvbNy3SWQikZRM6sr c89D0HzPWf7mfcJKbMtBWy9ovIUa6tr7kiRDSpI4ZF/CXj+5pAAL/Dd5RL/cr2fKfcAx P8vIiI3o3AQOCnFKzRtJaF9AF7S6VU5ySV5V8J7Z/tMMf6YFJujtUlm/A4lxbwt+GKKr EbCe/L4sYXUORsgkfc6fHXnzF74ybFsw0nSO4POGJi5T7Rgh+IcGAiuZHVnS1uy1I7YP dYH84pU8o0ROTc3SFk3vGMLLkf4R3XACFntkwCDKnKqt3N6+up4Ug0LmJB1HdoOvn4Rr 1nmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=NpNslA/nzr/Xf6IxLZdAaJ9lqh01yYVCliSq/aR63zE=; b=kTOQRi/PEYo8u0LD+ppl4YGkQ8gBw2z7kp/TOtxc6lQ4tFrB42UwKeB95B06E8m0gP 7FnpjIC4TAlE95XTq79rgYjKtu8w6q0z6g5wL5Cz0u8phqfNzJ22iOpzDHY5+729OjzO WhjqMKNeKcxrEXVjngjJVjcZOTBszPDcpNGyGT36BsIVsOqvcivtAVN1hSsRzKK5MgtU lLrIu89lIZXNKf6gyfaC2/FPa20POLMCBq5JGPsh4Zah0YLzpT7q7IRktCcwiiRZk8J0 LX5Gct2OWYtAvFpNvRbyF1C04A/c2DQcXZN1JwqcchCo8texHpAQdP3KwCH1NXzJ9lXc 8jCA== X-Gm-Message-State: AOAM530nSYTY8TtzYRS3TXIMRvkIhQtWPvMlqFZW0PIzbslGgtx7xsAw djee55c7bHZ+eC9CMMVD2UM= X-Google-Smtp-Source: ABdhPJy6Zcq1976akzvHbUkKJfQD4WQgcLz5fklVYZY+M6Jot8TpWz2gBTf8NKwHSL8PTEphRwBj1w== X-Received: by 2002:adf:c514:: with SMTP id q20mr29237977wrf.420.1635860676979; Tue, 02 Nov 2021 06:44:36 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 24/41] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Date: Tue, 2 Nov 2021 14:42:23 +0100 Message-Id: <20211102134240.3036524-25-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860679871100001 Convert 3-register operations to decodetree. Per the Encoding of Operation Field for 3R Instruction Format' (Table 3.25), these instructions are not defined for the BYTE format. Therefore the TRANS_DF_iii_b() macro returns 'false' in that case, because no such instruction is decoded. Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20211028210843.2120802-22-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 11 ++ target/mips/tcg/msa_translate.c | 182 +++++--------------------------- 2 files changed, 35 insertions(+), 158 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 4b14acce26f..0e2f474cde6 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -89,10 +89,21 @@ BNZ 010001 111 .. ..... ...............= . @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit =20 + DOTP_S 011110 000.. ..... ..... ..... 010011 @3r + DOTP_U 011110 001.. ..... ..... ..... 010011 @3r + DPADD_S 011110 010.. ..... ..... ..... 010011 @3r + DPADD_U 011110 011.. ..... ..... ..... 010011 @3r + DPSUB_S 011110 100.. ..... ..... ..... 010011 @3r + DPSUB_U 011110 101.. ..... ..... ..... 010011 @3r + SLD 011110 000 .. ..... ..... ..... 010100 @3r SPLAT 011110 001 .. ..... ..... ..... 010100 @3r =20 VSHF 011110 000 .. ..... ..... ..... 010101 @3r + HADD_S 011110 100.. ..... ..... ..... 010101 @3r + HADD_U 011110 101.. ..... ..... ..... 010101 @3r + HSUB_S 011110 110.. ..... ..... ..... 010101 @3r + HSUB_U 011110 111.. ..... ..... ..... 010101 @3r =20 FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index ddc0bd08ddf..5f3e1573e43 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -57,13 +57,11 @@ enum { OPC_ADD_A_df =3D (0x0 << 23) | OPC_MSA_3R_10, OPC_SUBS_S_df =3D (0x0 << 23) | OPC_MSA_3R_11, OPC_MULV_df =3D (0x0 << 23) | OPC_MSA_3R_12, - OPC_DOTP_S_df =3D (0x0 << 23) | OPC_MSA_3R_13, OPC_SRA_df =3D (0x1 << 23) | OPC_MSA_3R_0D, OPC_SUBV_df =3D (0x1 << 23) | OPC_MSA_3R_0E, OPC_ADDS_A_df =3D (0x1 << 23) | OPC_MSA_3R_10, OPC_SUBS_U_df =3D (0x1 << 23) | OPC_MSA_3R_11, OPC_MADDV_df =3D (0x1 << 23) | OPC_MSA_3R_12, - OPC_DOTP_U_df =3D (0x1 << 23) | OPC_MSA_3R_13, OPC_SRAR_df =3D (0x1 << 23) | OPC_MSA_3R_15, OPC_SRL_df =3D (0x2 << 23) | OPC_MSA_3R_0D, OPC_MAX_S_df =3D (0x2 << 23) | OPC_MSA_3R_0E, @@ -71,7 +69,6 @@ enum { OPC_ADDS_S_df =3D (0x2 << 23) | OPC_MSA_3R_10, OPC_SUBSUS_U_df =3D (0x2 << 23) | OPC_MSA_3R_11, OPC_MSUBV_df =3D (0x2 << 23) | OPC_MSA_3R_12, - OPC_DPADD_S_df =3D (0x2 << 23) | OPC_MSA_3R_13, OPC_PCKEV_df =3D (0x2 << 23) | OPC_MSA_3R_14, OPC_SRLR_df =3D (0x2 << 23) | OPC_MSA_3R_15, OPC_BCLR_df =3D (0x3 << 23) | OPC_MSA_3R_0D, @@ -79,7 +76,6 @@ enum { OPC_CLT_U_df =3D (0x3 << 23) | OPC_MSA_3R_0F, OPC_ADDS_U_df =3D (0x3 << 23) | OPC_MSA_3R_10, OPC_SUBSUU_S_df =3D (0x3 << 23) | OPC_MSA_3R_11, - OPC_DPADD_U_df =3D (0x3 << 23) | OPC_MSA_3R_13, OPC_PCKOD_df =3D (0x3 << 23) | OPC_MSA_3R_14, OPC_BSET_df =3D (0x4 << 23) | OPC_MSA_3R_0D, OPC_MIN_S_df =3D (0x4 << 23) | OPC_MSA_3R_0E, @@ -87,30 +83,24 @@ enum { OPC_AVE_S_df =3D (0x4 << 23) | OPC_MSA_3R_10, OPC_ASUB_S_df =3D (0x4 << 23) | OPC_MSA_3R_11, OPC_DIV_S_df =3D (0x4 << 23) | OPC_MSA_3R_12, - OPC_DPSUB_S_df =3D (0x4 << 23) | OPC_MSA_3R_13, OPC_ILVL_df =3D (0x4 << 23) | OPC_MSA_3R_14, - OPC_HADD_S_df =3D (0x4 << 23) | OPC_MSA_3R_15, OPC_BNEG_df =3D (0x5 << 23) | OPC_MSA_3R_0D, OPC_MIN_U_df =3D (0x5 << 23) | OPC_MSA_3R_0E, OPC_CLE_U_df =3D (0x5 << 23) | OPC_MSA_3R_0F, OPC_AVE_U_df =3D (0x5 << 23) | OPC_MSA_3R_10, OPC_ASUB_U_df =3D (0x5 << 23) | OPC_MSA_3R_11, OPC_DIV_U_df =3D (0x5 << 23) | OPC_MSA_3R_12, - OPC_DPSUB_U_df =3D (0x5 << 23) | OPC_MSA_3R_13, OPC_ILVR_df =3D (0x5 << 23) | OPC_MSA_3R_14, - OPC_HADD_U_df =3D (0x5 << 23) | OPC_MSA_3R_15, OPC_BINSL_df =3D (0x6 << 23) | OPC_MSA_3R_0D, OPC_MAX_A_df =3D (0x6 << 23) | OPC_MSA_3R_0E, OPC_AVER_S_df =3D (0x6 << 23) | OPC_MSA_3R_10, OPC_MOD_S_df =3D (0x6 << 23) | OPC_MSA_3R_12, OPC_ILVEV_df =3D (0x6 << 23) | OPC_MSA_3R_14, - OPC_HSUB_S_df =3D (0x6 << 23) | OPC_MSA_3R_15, OPC_BINSR_df =3D (0x7 << 23) | OPC_MSA_3R_0D, OPC_MIN_A_df =3D (0x7 << 23) | OPC_MSA_3R_0E, OPC_AVER_U_df =3D (0x7 << 23) | OPC_MSA_3R_10, OPC_MOD_U_df =3D (0x7 << 23) | OPC_MSA_3R_12, OPC_ILVOD_df =3D (0x7 << 23) | OPC_MSA_3R_14, - OPC_HSUB_U_df =3D (0x7 << 23) | OPC_MSA_3R_15, =20 /* ELM instructions df(bits 21..16) =3D _b, _h, _w, _d */ OPC_SLDI_df =3D (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM, @@ -255,6 +245,15 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv= _i32, TCGv_i32, TCGv_i32); #define TRANS_DF_ii(NAME, trans_func, gen_func) \ TRANS_DF_x(ii, NAME, trans_func, gen_func) =20 +#define TRANS_DF_iii_b(NAME, trans_func, gen_func) \ + static gen_helper_piii * const NAME##_tab[4] =3D { \ + NULL, gen_func##_h, gen_func##_w, gen_func##_d \ + }; \ + static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ + { \ + return trans_func(ctx, a, NAME##_tab[a->df]); \ + } + static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, TCGCond cond) { @@ -482,6 +481,10 @@ static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r= *a, static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a, gen_helper_piii *gen_msa_3r) { + if (!gen_msa_3r) { + return false; + } + if (!check_msa_enabled(ctx)) { return true; } @@ -502,10 +505,21 @@ TRANS(BMNZ_V, trans_msa_3r, gen_helper_ms= a_bmnz_v); TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v); TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v); =20 +TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s); +TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u); +TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s); +TRANS_DF_iii_b(DPADD_U, trans_msa_3r, gen_helper_msa_dpadd_u); +TRANS_DF_iii_b(DPSUB_S, trans_msa_3r, gen_helper_msa_dpsub_s); +TRANS_DF_iii_b(DPSUB_U, trans_msa_3r, gen_helper_msa_dpsub_u); + TRANS(SLD, trans_msa_3rf, gen_helper_msa_sld_df); TRANS(SPLAT, trans_msa_3rf, gen_helper_msa_splat_df); =20 TRANS(VSHF, trans_msa_3rf, gen_helper_msa_vshf_df); +TRANS_DF_iii_b(HADD_S, trans_msa_3r, gen_helper_msa_hadd_s); +TRANS_DF_iii_b(HADD_U, trans_msa_3r, gen_helper_msa_hadd_u); +TRANS_DF_iii_b(HSUB_S, trans_msa_3r, gen_helper_msa_hsub_s); +TRANS_DF_iii_b(HSUB_U, trans_msa_3r, gen_helper_msa_hsub_u); =20 static void gen_msa_3r(DisasContext *ctx) { @@ -1321,154 +1335,6 @@ static void gen_msa_3r(DisasContext *ctx) break; } break; - - case OPC_DOTP_S_df: - case OPC_DOTP_U_df: - case OPC_DPADD_S_df: - case OPC_DPADD_U_df: - case OPC_DPSUB_S_df: - case OPC_HADD_S_df: - case OPC_DPSUB_U_df: - case OPC_HADD_U_df: - case OPC_HSUB_S_df: - case OPC_HSUB_U_df: - if (df =3D=3D DF_BYTE) { - gen_reserved_instruction(ctx); - break; - } - switch (MASK_MSA_3R(ctx->opcode)) { - case OPC_HADD_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hadd_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hadd_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hadd_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_HADD_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hadd_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hadd_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hadd_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_HSUB_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hsub_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hsub_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hsub_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_HSUB_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hsub_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hsub_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hsub_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DOTP_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dotp_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dotp_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dotp_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DOTP_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dotp_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dotp_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dotp_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPADD_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpadd_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpadd_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpadd_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPADD_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpadd_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpadd_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpadd_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPSUB_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpsub_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpsub_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpsub_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPSUB_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpsub_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpsub_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpsub_u_d(cpu_env, twd, tws, twt); - break; - } - break; - } - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) client-ip=209.85.221.52; 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Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-23-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 3 +++ target/mips/tcg/msa_translate.c | 40 +++++---------------------------- 2 files changed, 9 insertions(+), 34 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 0e2f474cde6..f2bacbaea86 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -89,6 +89,9 @@ BNZ 010001 111 .. ..... ................ = @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit =20 + BINSL 011110 110.. ..... ..... ..... 001101 @3r + BINSR 011110 111.. ..... ..... ..... 001101 @3r + DOTP_S 011110 000.. ..... ..... ..... 010011 @3r DOTP_U 011110 001.. ..... ..... ..... 010011 @3r DPADD_S 011110 010.. ..... ..... ..... 010011 @3r diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 5f3e1573e43..c52913632c5 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -91,12 +91,10 @@ enum { OPC_ASUB_U_df =3D (0x5 << 23) | OPC_MSA_3R_11, OPC_DIV_U_df =3D (0x5 << 23) | OPC_MSA_3R_12, OPC_ILVR_df =3D (0x5 << 23) | OPC_MSA_3R_14, - OPC_BINSL_df =3D (0x6 << 23) | OPC_MSA_3R_0D, OPC_MAX_A_df =3D (0x6 << 23) | OPC_MSA_3R_0E, OPC_AVER_S_df =3D (0x6 << 23) | OPC_MSA_3R_10, OPC_MOD_S_df =3D (0x6 << 23) | OPC_MSA_3R_12, OPC_ILVEV_df =3D (0x6 << 23) | OPC_MSA_3R_14, - OPC_BINSR_df =3D (0x7 << 23) | OPC_MSA_3R_0D, OPC_MIN_A_df =3D (0x7 << 23) | OPC_MSA_3R_0E, OPC_AVER_U_df =3D (0x7 << 23) | OPC_MSA_3R_10, OPC_MOD_U_df =3D (0x7 << 23) | OPC_MSA_3R_12, @@ -245,6 +243,9 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_= i32, TCGv_i32, TCGv_i32); #define TRANS_DF_ii(NAME, trans_func, gen_func) \ TRANS_DF_x(ii, NAME, trans_func, gen_func) =20 +#define TRANS_DF_iii(NAME, trans_func, gen_func) \ + TRANS_DF_x(iii, NAME, trans_func, gen_func) + #define TRANS_DF_iii_b(NAME, trans_func, gen_func) \ static gen_helper_piii * const NAME##_tab[4] =3D { \ NULL, gen_func##_h, gen_func##_w, gen_func##_d \ @@ -505,6 +506,9 @@ TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa_= bmnz_v); TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v); TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v); =20 +TRANS_DF_iii(BINSL, trans_msa_3r, gen_helper_msa_binsl); +TRANS_DF_iii(BINSR, trans_msa_3r, gen_helper_msa_binsr); + TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s); TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u); TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s); @@ -535,38 +539,6 @@ static void gen_msa_3r(DisasContext *ctx) TCGv_i32 twt =3D tcg_const_i32(wt); =20 switch (MASK_MSA_3R(ctx->opcode)) { - case OPC_BINSL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_binsl_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_binsl_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_binsl_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_binsl_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BINSR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_binsr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_binsr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_binsr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_binsr_d(cpu_env, twd, tws, twt); - break; - } - break; case OPC_BCLR_df: switch (df) { case DF_BYTE: --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) client-ip=209.85.128.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id j12sm2098257wmq.37.2021.11.02.06.44.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:44:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NlrQCAF2Zn7A0VJQoF1a72S7C3Z75Jm56PHmZOvKU/o=; b=ea76zQDKxNjNfTTMPD7wYPphHxwP4S2Bji6Mf8MtGYf1LmMTvGvGzSDjfVClAMTLI5 lb2OHtZZl7ZNJBj+ai2xRvm+yDDbO+ccbFS4TMkQWXDzfJdw+UBmHWgKpFjwvkmqTsTP NYfLCzf6BTHmyzl6VU4lh9ywFm3fQaAdoMprSIIwCkasQKSvlVHM512CGZFJXT93arW7 CRvz7ka53pkoBx4X07/GpJCcjE9XawFRUu4pSAWRp1uWgZen0U3i0C4ahC17jnU8Gsei AK0vgi/crh68Hyeas5l2VBEP3YTGzUZ4+n2GgzzDkVyroYMGswuozN/SzMO7AthPTYlO Ja9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=NlrQCAF2Zn7A0VJQoF1a72S7C3Z75Jm56PHmZOvKU/o=; b=uk0bQVd60iRoGBD9itJoytMmXSefJ5jUNpdEUeC1b83oMKQmYVB+2gB2Wz6proLZmn MFz333LjDEFksAJcUepG/xoCN4/H3HKi9JRBDLA/RdQ8HV8olJkDHSw57G32MfUtHsK9 Xbsnouu4avz6w3xpVKcz4g08Iru8URrvl2EX+UuFh9NwDilkSar4wJLeogvVvFxhvJx+ 0d5MH536OB1ynsi4zJQ/JfR68EFL0xB2s1QIgd3k7qLdRoB3xipZmUb7TVh2zQZ5xZ+Z 0woAX0K97KmSnjm8mreDhTftOHQt1r5EFChZLd5Kk6JGdC+AvLu0c5uoM2d8brRY9UNz 7dQw== X-Gm-Message-State: AOAM533i37MuLe5JrEspn+DDkjte+BVbT9qjt4yU3ZvBmBP4Uk9cr9Px ARTCVUpB0LinJLr29h29e/c= X-Google-Smtp-Source: ABdhPJxXRCBkSnX2Sjqqz6rOiE/8pgQer88LJPc6z4ImEKc7JdI4uw5YxYt5wiVCE/7Rz0Ki6O7xXQ== X-Received: by 2002:a7b:c049:: with SMTP id u9mr7284897wmc.102.1635860686691; Tue, 02 Nov 2021 06:44:46 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 26/41] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Date: Tue, 2 Nov 2021 14:42:25 +0100 Message-Id: <20211102134240.3036524-27-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860689190100001 Convert 3-register operations to decodetree. Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-24-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 53 ++ target/mips/tcg/msa_translate.c | 916 ++------------------------------ 2 files changed, 106 insertions(+), 863 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index f2bacbaea86..391261109a5 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -89,9 +89,54 @@ BNZ 010001 111 .. ..... ................= @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit =20 + SLL 011110 000.. ..... ..... ..... 001101 @3r + SRA 011110 001.. ..... ..... ..... 001101 @3r + SRL 011110 010.. ..... ..... ..... 001101 @3r + BCLR 011110 011.. ..... ..... ..... 001101 @3r + BSET 011110 100.. ..... ..... ..... 001101 @3r + BNEG 011110 101.. ..... ..... ..... 001101 @3r BINSL 011110 110.. ..... ..... ..... 001101 @3r BINSR 011110 111.. ..... ..... ..... 001101 @3r =20 + ADDV 011110 000.. ..... ..... ..... 001110 @3r + SUBV 011110 001.. ..... ..... ..... 001110 @3r + MAX_S 011110 010.. ..... ..... ..... 001110 @3r + MAX_U 011110 011.. ..... ..... ..... 001110 @3r + MIN_S 011110 100.. ..... ..... ..... 001110 @3r + MIN_U 011110 101.. ..... ..... ..... 001110 @3r + MAX_A 011110 110.. ..... ..... ..... 001110 @3r + MIN_A 011110 111.. ..... ..... ..... 001110 @3r + + CEQ 011110 000.. ..... ..... ..... 001111 @3r + CLT_S 011110 010.. ..... ..... ..... 001111 @3r + CLT_U 011110 011.. ..... ..... ..... 001111 @3r + CLE_S 011110 100.. ..... ..... ..... 001111 @3r + CLE_U 011110 101.. ..... ..... ..... 001111 @3r + + ADD_A 011110 000.. ..... ..... ..... 010000 @3r + ADDS_A 011110 001.. ..... ..... ..... 010000 @3r + ADDS_S 011110 010.. ..... ..... ..... 010000 @3r + ADDS_U 011110 011.. ..... ..... ..... 010000 @3r + AVE_S 011110 100.. ..... ..... ..... 010000 @3r + AVE_U 011110 101.. ..... ..... ..... 010000 @3r + AVER_S 011110 110.. ..... ..... ..... 010000 @3r + AVER_U 011110 111.. ..... ..... ..... 010000 @3r + + SUBS_S 011110 000.. ..... ..... ..... 010001 @3r + SUBS_U 011110 001.. ..... ..... ..... 010001 @3r + SUBSUS_U 011110 010.. ..... ..... ..... 010001 @3r + SUBSUU_S 011110 011.. ..... ..... ..... 010001 @3r + ASUB_S 011110 100.. ..... ..... ..... 010001 @3r + ASUB_U 011110 101.. ..... ..... ..... 010001 @3r + + MULV 011110 000.. ..... ..... ..... 010010 @3r + MADDV 011110 001.. ..... ..... ..... 010010 @3r + MSUBV 011110 010.. ..... ..... ..... 010010 @3r + DIV_S 011110 100.. ..... ..... ..... 010010 @3r + DIV_U 011110 101.. ..... ..... ..... 010010 @3r + MOD_S 011110 110.. ..... ..... ..... 010010 @3r + MOD_U 011110 111.. ..... ..... ..... 010010 @3r + DOTP_S 011110 000.. ..... ..... ..... 010011 @3r DOTP_U 011110 001.. ..... ..... ..... 010011 @3r DPADD_S 011110 010.. ..... ..... ..... 010011 @3r @@ -101,8 +146,16 @@ BNZ 010001 111 .. ..... ..............= .. @bz =20 SLD 011110 000 .. ..... ..... ..... 010100 @3r SPLAT 011110 001 .. ..... ..... ..... 010100 @3r + PCKEV 011110 010 .. ..... ..... ..... 010100 @3r + PCKOD 011110 011 .. ..... ..... ..... 010100 @3r + ILVL 011110 100 .. ..... ..... ..... 010100 @3r + ILVR 011110 101 .. ..... ..... ..... 010100 @3r + ILVEV 011110 110 .. ..... ..... ..... 010100 @3r + ILVOD 011110 111 .. ..... ..... ..... 010100 @3r =20 VSHF 011110 000 .. ..... ..... ..... 010101 @3r + SRAR 011110 001 .. ..... ..... ..... 010101 @3r + SRLR 011110 010 .. ..... ..... ..... 010101 @3r HADD_S 011110 100.. ..... ..... ..... 010101 @3r HADD_U 011110 101.. ..... ..... ..... 010101 @3r HSUB_S 011110 110.. ..... ..... ..... 010101 @3r diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index c52913632c5..3b95e081a04 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -37,69 +37,10 @@ static inline int plus_2(DisasContext *s, int x) =20 #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) enum { - OPC_MSA_3R_0D =3D 0x0D | OPC_MSA, - OPC_MSA_3R_0E =3D 0x0E | OPC_MSA, - OPC_MSA_3R_0F =3D 0x0F | OPC_MSA, - OPC_MSA_3R_10 =3D 0x10 | OPC_MSA, - OPC_MSA_3R_11 =3D 0x11 | OPC_MSA, - OPC_MSA_3R_12 =3D 0x12 | OPC_MSA, - OPC_MSA_3R_13 =3D 0x13 | OPC_MSA, - OPC_MSA_3R_14 =3D 0x14 | OPC_MSA, - OPC_MSA_3R_15 =3D 0x15 | OPC_MSA, OPC_MSA_ELM =3D 0x19 | OPC_MSA, }; =20 enum { - /* 3R instruction df(bits 22..21) =3D _b, _h, _w, d */ - OPC_SLL_df =3D (0x0 << 23) | OPC_MSA_3R_0D, - OPC_ADDV_df =3D (0x0 << 23) | OPC_MSA_3R_0E, - OPC_CEQ_df =3D (0x0 << 23) | OPC_MSA_3R_0F, - OPC_ADD_A_df =3D (0x0 << 23) | OPC_MSA_3R_10, - OPC_SUBS_S_df =3D (0x0 << 23) | OPC_MSA_3R_11, - OPC_MULV_df =3D (0x0 << 23) | OPC_MSA_3R_12, - OPC_SRA_df =3D (0x1 << 23) | OPC_MSA_3R_0D, - OPC_SUBV_df =3D (0x1 << 23) | OPC_MSA_3R_0E, - OPC_ADDS_A_df =3D (0x1 << 23) | OPC_MSA_3R_10, - OPC_SUBS_U_df =3D (0x1 << 23) | OPC_MSA_3R_11, - OPC_MADDV_df =3D (0x1 << 23) | OPC_MSA_3R_12, - OPC_SRAR_df =3D (0x1 << 23) | OPC_MSA_3R_15, - OPC_SRL_df =3D (0x2 << 23) | OPC_MSA_3R_0D, - OPC_MAX_S_df =3D (0x2 << 23) | OPC_MSA_3R_0E, - OPC_CLT_S_df =3D (0x2 << 23) | OPC_MSA_3R_0F, - OPC_ADDS_S_df =3D (0x2 << 23) | OPC_MSA_3R_10, - OPC_SUBSUS_U_df =3D (0x2 << 23) | OPC_MSA_3R_11, - OPC_MSUBV_df =3D (0x2 << 23) | OPC_MSA_3R_12, - OPC_PCKEV_df =3D (0x2 << 23) | OPC_MSA_3R_14, - OPC_SRLR_df =3D (0x2 << 23) | OPC_MSA_3R_15, - OPC_BCLR_df =3D (0x3 << 23) | OPC_MSA_3R_0D, - OPC_MAX_U_df =3D (0x3 << 23) | OPC_MSA_3R_0E, - OPC_CLT_U_df =3D (0x3 << 23) | OPC_MSA_3R_0F, - OPC_ADDS_U_df =3D (0x3 << 23) | OPC_MSA_3R_10, - OPC_SUBSUU_S_df =3D (0x3 << 23) | OPC_MSA_3R_11, - OPC_PCKOD_df =3D (0x3 << 23) | OPC_MSA_3R_14, - OPC_BSET_df =3D (0x4 << 23) | OPC_MSA_3R_0D, - OPC_MIN_S_df =3D (0x4 << 23) | OPC_MSA_3R_0E, - OPC_CLE_S_df =3D (0x4 << 23) | OPC_MSA_3R_0F, - OPC_AVE_S_df =3D (0x4 << 23) | OPC_MSA_3R_10, - OPC_ASUB_S_df =3D (0x4 << 23) | OPC_MSA_3R_11, - OPC_DIV_S_df =3D (0x4 << 23) | OPC_MSA_3R_12, - OPC_ILVL_df =3D (0x4 << 23) | OPC_MSA_3R_14, - OPC_BNEG_df =3D (0x5 << 23) | OPC_MSA_3R_0D, - OPC_MIN_U_df =3D (0x5 << 23) | OPC_MSA_3R_0E, - OPC_CLE_U_df =3D (0x5 << 23) | OPC_MSA_3R_0F, - OPC_AVE_U_df =3D (0x5 << 23) | OPC_MSA_3R_10, - OPC_ASUB_U_df =3D (0x5 << 23) | OPC_MSA_3R_11, - OPC_DIV_U_df =3D (0x5 << 23) | OPC_MSA_3R_12, - OPC_ILVR_df =3D (0x5 << 23) | OPC_MSA_3R_14, - OPC_MAX_A_df =3D (0x6 << 23) | OPC_MSA_3R_0E, - OPC_AVER_S_df =3D (0x6 << 23) | OPC_MSA_3R_10, - OPC_MOD_S_df =3D (0x6 << 23) | OPC_MSA_3R_12, - OPC_ILVEV_df =3D (0x6 << 23) | OPC_MSA_3R_14, - OPC_MIN_A_df =3D (0x7 << 23) | OPC_MSA_3R_0E, - OPC_AVER_U_df =3D (0x7 << 23) | OPC_MSA_3R_10, - OPC_MOD_U_df =3D (0x7 << 23) | OPC_MSA_3R_12, - OPC_ILVOD_df =3D (0x7 << 23) | OPC_MSA_3R_14, - /* ELM instructions df(bits 21..16) =3D _b, _h, _w, _d */ OPC_SLDI_df =3D (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_CTCMSA =3D (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, @@ -506,9 +447,54 @@ TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa= _bmnz_v); TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v); TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v); =20 +TRANS_DF_iii(SLL, trans_msa_3r, gen_helper_msa_sll); +TRANS_DF_iii(SRA, trans_msa_3r, gen_helper_msa_sra); +TRANS_DF_iii(SRL, trans_msa_3r, gen_helper_msa_srl); +TRANS_DF_iii(BCLR, trans_msa_3r, gen_helper_msa_bclr); +TRANS_DF_iii(BSET, trans_msa_3r, gen_helper_msa_bset); +TRANS_DF_iii(BNEG, trans_msa_3r, gen_helper_msa_bneg); TRANS_DF_iii(BINSL, trans_msa_3r, gen_helper_msa_binsl); TRANS_DF_iii(BINSR, trans_msa_3r, gen_helper_msa_binsr); =20 +TRANS_DF_iii(ADDV, trans_msa_3r, gen_helper_msa_addv); +TRANS_DF_iii(SUBV, trans_msa_3r, gen_helper_msa_subv); +TRANS_DF_iii(MAX_S, trans_msa_3r, gen_helper_msa_max_s); +TRANS_DF_iii(MAX_U, trans_msa_3r, gen_helper_msa_max_u); +TRANS_DF_iii(MIN_S, trans_msa_3r, gen_helper_msa_min_s); +TRANS_DF_iii(MIN_U, trans_msa_3r, gen_helper_msa_min_u); +TRANS_DF_iii(MAX_A, trans_msa_3r, gen_helper_msa_max_a); +TRANS_DF_iii(MIN_A, trans_msa_3r, gen_helper_msa_min_a); + +TRANS_DF_iii(CEQ, trans_msa_3r, gen_helper_msa_ceq); +TRANS_DF_iii(CLT_S, trans_msa_3r, gen_helper_msa_clt_s); +TRANS_DF_iii(CLT_U, trans_msa_3r, gen_helper_msa_clt_u); +TRANS_DF_iii(CLE_S, trans_msa_3r, gen_helper_msa_cle_s); +TRANS_DF_iii(CLE_U, trans_msa_3r, gen_helper_msa_cle_u); + +TRANS_DF_iii(ADD_A, trans_msa_3r, gen_helper_msa_add_a); +TRANS_DF_iii(ADDS_A, trans_msa_3r, gen_helper_msa_adds_a); +TRANS_DF_iii(ADDS_S, trans_msa_3r, gen_helper_msa_adds_s); +TRANS_DF_iii(ADDS_U, trans_msa_3r, gen_helper_msa_adds_u); +TRANS_DF_iii(AVE_S, trans_msa_3r, gen_helper_msa_ave_s); +TRANS_DF_iii(AVE_U, trans_msa_3r, gen_helper_msa_ave_u); +TRANS_DF_iii(AVER_S, trans_msa_3r, gen_helper_msa_aver_s); +TRANS_DF_iii(AVER_U, trans_msa_3r, gen_helper_msa_aver_u); + +TRANS_DF_iii(SUBS_S, trans_msa_3r, gen_helper_msa_subs_s); +TRANS_DF_iii(SUBS_U, trans_msa_3r, gen_helper_msa_subs_u); +TRANS_DF_iii(SUBSUS_U, trans_msa_3r, gen_helper_msa_subsus_u); +TRANS_DF_iii(SUBSUU_S, trans_msa_3r, gen_helper_msa_subsuu_s); +TRANS_DF_iii(ASUB_S, trans_msa_3r, gen_helper_msa_asub_s); +TRANS_DF_iii(ASUB_U, trans_msa_3r, gen_helper_msa_asub_u); + +TRANS_DF_iii(MULV, trans_msa_3r, gen_helper_msa_mulv); +TRANS_DF_iii(MADDV, trans_msa_3r, gen_helper_msa_maddv); +TRANS_DF_iii(MSUBV, trans_msa_3r, gen_helper_msa_msubv); +TRANS_DF_iii(DIV_S, trans_msa_3r, gen_helper_msa_div_s); +TRANS_DF_iii(DIV_U, trans_msa_3r, gen_helper_msa_div_u); +TRANS_DF_iii(MOD_S, trans_msa_3r, gen_helper_msa_mod_s); +TRANS_DF_iii(MOD_U, trans_msa_3r, gen_helper_msa_mod_u); + TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s); TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u); TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s); @@ -518,806 +504,21 @@ TRANS_DF_iii_b(DPSUB_U, trans_msa_3r, gen_helper_m= sa_dpsub_u); =20 TRANS(SLD, trans_msa_3rf, gen_helper_msa_sld_df); TRANS(SPLAT, trans_msa_3rf, gen_helper_msa_splat_df); +TRANS_DF_iii(PCKEV, trans_msa_3r, gen_helper_msa_pckev); +TRANS_DF_iii(PCKOD, trans_msa_3r, gen_helper_msa_pckod); +TRANS_DF_iii(ILVL, trans_msa_3r, gen_helper_msa_ilvl); +TRANS_DF_iii(ILVR, trans_msa_3r, gen_helper_msa_ilvr); +TRANS_DF_iii(ILVEV, trans_msa_3r, gen_helper_msa_ilvev); +TRANS_DF_iii(ILVOD, trans_msa_3r, gen_helper_msa_ilvod); =20 TRANS(VSHF, trans_msa_3rf, gen_helper_msa_vshf_df); +TRANS_DF_iii(SRAR, trans_msa_3r, gen_helper_msa_srar); +TRANS_DF_iii(SRLR, trans_msa_3r, gen_helper_msa_srlr); TRANS_DF_iii_b(HADD_S, trans_msa_3r, gen_helper_msa_hadd_s); TRANS_DF_iii_b(HADD_U, trans_msa_3r, gen_helper_msa_hadd_u); TRANS_DF_iii_b(HSUB_S, trans_msa_3r, gen_helper_msa_hsub_s); TRANS_DF_iii_b(HSUB_U, trans_msa_3r, gen_helper_msa_hsub_u); =20 -static void gen_msa_3r(DisasContext *ctx) -{ -#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) - uint8_t df =3D (ctx->opcode >> 21) & 0x3; - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 tdf =3D tcg_const_i32(df); - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - - switch (MASK_MSA_3R(ctx->opcode)) { - case OPC_BCLR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_bclr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_bclr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_bclr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_bclr_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BNEG_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_bneg_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_bneg_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_bneg_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_bneg_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BSET_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_bset_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_bset_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_bset_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_bset_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADD_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_add_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_add_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_add_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_add_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDS_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_adds_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_adds_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_adds_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_adds_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDS_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_adds_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_adds_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_adds_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_adds_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDS_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_adds_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_adds_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_adds_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_adds_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_addv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_addv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_addv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_addv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVE_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ave_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ave_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ave_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ave_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVE_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ave_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ave_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ave_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ave_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVER_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_aver_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_aver_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_aver_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_aver_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVER_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_aver_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_aver_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_aver_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_aver_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CEQ_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ceq_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ceq_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ceq_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ceq_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLE_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_cle_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_cle_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_cle_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_cle_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLE_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_cle_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_cle_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_cle_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_cle_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLT_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_clt_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_clt_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_clt_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_clt_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLT_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_clt_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_clt_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_clt_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_clt_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DIV_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_div_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_div_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_div_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_div_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DIV_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_div_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_div_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_div_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_div_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MAX_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_max_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_max_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_max_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_max_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MAX_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_max_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_max_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_max_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_max_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MAX_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_max_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_max_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_max_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_max_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MIN_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_min_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_min_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_min_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_min_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MIN_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_min_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_min_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_min_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_min_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MIN_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_min_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_min_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_min_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_min_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MOD_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_mod_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_mod_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_mod_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_mod_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MOD_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_mod_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_mod_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_mod_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_mod_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MADDV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_maddv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_maddv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_maddv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_maddv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MSUBV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_msubv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_msubv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_msubv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_msubv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ASUB_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_asub_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_asub_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_asub_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_asub_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ASUB_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_asub_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_asub_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_asub_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_asub_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVEV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvev_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvev_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvev_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvev_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVOD_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvod_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvod_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvod_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvod_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvl_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvl_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvl_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvl_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvr_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_PCKEV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_pckev_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_pckev_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_pckev_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_pckev_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_PCKOD_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_pckod_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_pckod_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_pckod_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_pckod_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SLL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_sll_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_sll_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_sll_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_sll_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRA_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_sra_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_sra_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_sra_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_sra_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRAR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_srar_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_srar_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_srar_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_srar_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_srl_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_srl_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_srl_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_srl_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRLR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_srlr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_srlr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_srlr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_srlr_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBS_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subs_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subs_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subs_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subs_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MULV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_mulv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_mulv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_mulv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_mulv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBS_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subs_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subs_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subs_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subs_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBSUS_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subsus_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subsus_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subsus_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subsus_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBSUU_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subsuu_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subsuu_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subsuu_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subsuu_s_d(cpu_env, twd, tws, twt); - break; - } - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); - tcg_temp_free_i32(tdf); -} - static void gen_msa_elm_3e(DisasContext *ctx) { #define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) @@ -1608,17 +809,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) } =20 switch (MASK_MSA_MINOR(opcode)) { - case OPC_MSA_3R_0D: - case OPC_MSA_3R_0E: - case OPC_MSA_3R_0F: - case OPC_MSA_3R_10: - case OPC_MSA_3R_11: - case OPC_MSA_3R_12: - case OPC_MSA_3R_13: - case OPC_MSA_3R_14: - case OPC_MSA_3R_15: - gen_msa_3r(ctx); - break; case OPC_MSA_ELM: gen_msa_elm(ctx); break; --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) client-ip=209.85.221.46; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id a1sm9053281wri.89.2021.11.02.06.44.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:44:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sNrUNW9aVz2ixvALVPGW8JPx1J4reeP0whjPhiYCgSg=; b=XtGDsNL70IJSHDlbXlqwA7X063T5p1gOImjA2QLjBPqHwT5fi5ZFY3iO/2nvONJB4L miN9CV7rMLTaLJUiCDn+eS4TKbOCuTMQb3LNd7gbtaNOS0+Wxz7x2fx/ba+YuOFuPQpW q4rUMwOy9skidcjmWHzxhEcrvhaK5NmOceMO/n8iPuGJWJSWoODsbPO2dt7EnedThNZE ZbRr1VNWvm4yNa8gVrSB8YtznrA+5whBioTNaMxJl3FPX+S011mdnZYwMGuF3XE50/9H UhEVUwNA3t4cFZq10JHyM+VXgWF2uZQF0+paxrd9yjv6p9DZu4KtDRv95O8UgyZlU8cF wu1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sNrUNW9aVz2ixvALVPGW8JPx1J4reeP0whjPhiYCgSg=; b=QZGO2LIB6t30Q7UBuS6PJrSmYe/jmC9j5KV44UN20UvcwPo1SRUJrukpT5LPfHMPH5 7PHrfEbndxVE1l7wRhY1+3K2M6AWcNFMmIE8C1Op7wc7NMEn7BGs7nzG4O8gidXp+YiV uAJnTyIx9Y+zhIR6q8WpkdKrTaoCswaNWkUbclPNWBHKYewvNtpuTqtFAHgS2UI+MnXE UPJIn/eXKNPnlNVPb7KXl5wGJQZDjIeqLsasOObhFKXDaMBs7a6FsnYwrwOKHtot+Gu+ MEAaK0hLFoMHhLUnZiZLantiJlMzkAwx447swiy8IJEP/+l9UBZRsn+CuNhcIxTsnp3x kURQ== X-Gm-Message-State: AOAM5302MqPbR3dlhi2v46ggT1DtiPmvKzx99JPeJG3Rpuom0GX1qNV4 N0wS28uNoSYuukBkRtvJmP0= X-Google-Smtp-Source: ABdhPJzV3/KYbRd5Ex+klrLidenNOqJlN2UCxmW6n1L7Q95T90F0ZiOeGd+EyPSPHDLUbG+1TK8Pdw== X-Received: by 2002:adf:f681:: with SMTP id v1mr26088243wrp.367.1635860691418; Tue, 02 Nov 2021 06:44:51 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 27/41] target/mips: Convert MSA ELM instruction format to decodetree Date: Tue, 2 Nov 2021 14:42:26 +0100 Message-Id: <20211102134240.3036524-28-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860693966100003 Convert instructions with an immediate element index and data format df/n to decodetree. Since the 'data format' and 'n' fields are constant values, use tcg_constant_i32() instead of a TCG temporaries. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-25-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 8 +++++ target/mips/tcg/msa_translate.c | 57 +++++++++++++++++++++++++-------- 2 files changed, 52 insertions(+), 13 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 391261109a5..bf014524eed 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -18,7 +18,10 @@ &msa_ldi df wd sa &msa_i df wd ws sa &msa_bit df wd ws m +&msa_elm_df df wd ws n =20 +%elm_df 16:6 !function=3Delm_df +%elm_n 16:6 !function=3Delm_n %bit_df 16:7 !function=3Dbit_df %bit_m 16:7 !function=3Dbit_m %2r_df_w 16:1 !function=3Dplus_2 @@ -29,6 +32,7 @@ @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3D3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@elm_df ...... .... ...... ws:5 wd:5 ...... &msa_elm_df df= =3D%elm_df n=3D%elm_n @vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=3D0 @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=3D0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=3D0 = df=3D%2r_df_w @@ -161,6 +165,10 @@ BNZ 010001 111 .. ..... ..............= .. @bz HSUB_S 011110 110.. ..... ..... ..... 010101 @3r HSUB_U 011110 111.. ..... ..... ..... 010101 @3r =20 + SLDI 011110 0000 ...... ..... ..... 011001 @elm_df + SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df + INSVE 011110 0101 ...... ..... ..... 011001 @elm_df + FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf_w diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 3b95e081a04..14e0a8879c4 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -17,6 +17,8 @@ #include "fpu_helper.h" #include "internal.h" =20 +static int elm_n(DisasContext *ctx, int x); +static int elm_df(DisasContext *ctx, int x); static int bit_m(DisasContext *ctx, int x); static int bit_df(DisasContext *ctx, int x); =20 @@ -42,15 +44,12 @@ enum { =20 enum { /* ELM instructions df(bits 21..16) =3D _b, _h, _w, _d */ - OPC_SLDI_df =3D (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_CTCMSA =3D (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_SPLATI_df =3D (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_CFCMSA =3D (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, OPC_COPY_S_df =3D (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_MOVE_V =3D (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM, OPC_COPY_U_df =3D (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_INSERT_df =3D (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM, - OPC_INSVE_df =3D (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM, }; =20 static const char msaregnames[][6] =3D { @@ -107,6 +106,24 @@ static int df_extract_df(DisasContext *ctx, int x, con= st struct dfe *s) return -1; } =20 +static const struct dfe df_elm[] =3D { + /* Table 3.26 ELM Instruction Format */ + [DF_BYTE] =3D {4, 2, 0b00}, + [DF_HALF] =3D {3, 3, 0b100}, + [DF_WORD] =3D {2, 4, 0b1100}, + [DF_DOUBLE] =3D {1, 5, 0b11100} +}; + +static int elm_n(DisasContext *ctx, int x) +{ + return df_extract_val(ctx, x, df_elm); +} + +static int elm_df(DisasContext *ctx, int x) +{ + return df_extract_df(ctx, x, df_elm); +} + static const struct dfe df_bit[] =3D { /* Table 3.28 BIT Instruction Format */ [DF_BYTE] =3D {3, 4, 0b1110}, @@ -551,6 +568,30 @@ static void gen_msa_elm_3e(DisasContext *ctx) tcg_temp_free_i32(tsr); } =20 +static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a, + gen_helper_piiii *gen_msa_elm_df) +{ + if (a->df < 0) { + return false; + } + + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_msa_elm_df(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->n)); + + return true; +} + +TRANS(SLDI, trans_msa_elm, gen_helper_msa_sldi_df); +TRANS(SPLATI, trans_msa_elm, gen_helper_msa_splati_df); +TRANS(INSVE, trans_msa_elm, gen_helper_msa_insve_df); + static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) { #define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) @@ -560,18 +601,8 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t= df, uint32_t n) TCGv_i32 tws =3D tcg_const_i32(ws); TCGv_i32 twd =3D tcg_const_i32(wd); TCGv_i32 tn =3D tcg_const_i32(n); - TCGv_i32 tdf =3D tcg_constant_i32(df); =20 switch (MASK_MSA_ELM(ctx->opcode)) { - case OPC_SLDI_df: - gen_helper_msa_sldi_df(cpu_env, tdf, twd, tws, tn); - break; - case OPC_SPLATI_df: - gen_helper_msa_splati_df(cpu_env, tdf, twd, tws, tn); - break; - case OPC_INSVE_df: - gen_helper_msa_insve_df(cpu_env, tdf, twd, tws, tn); - break; case OPC_COPY_S_df: case OPC_COPY_U_df: case OPC_INSERT_df: --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) client-ip=209.85.221.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860697; cv=none; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id o1sm9829205wrn.63.2021.11.02.06.44.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:44:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+FTos3rUD6fh/en8KLJV4G7L5LRqhFG+pDtfRWiJ4eE=; b=ctT36Ei1sKj8ERU9fl0kgbstOmU5U8rquWzVyy1s+u1GlKAv+7cC8ayTYYCGkC51vp Jm7TpQ0ZaSgLWZlNakEVoruIW8/+Y2hdqata0z5Jc/5zRfqmViVEsLIwQA5YyXSSiaj4 Wt6Zmj5A7+fLjhnBnEZc3+Gr/DyN7WzQWCJNmIhMfxhC1sUskhqYWzwWXboECJ/htq2A ZNOprvibizMVStEtu9c9kG3p7M9S5KxZBgaK1pT5PWdYNSvuYE2mk/usaUNrD3Py3cYd E88vh6BBf67mKGiJ1SS4OF+uRKlbYLX+HFfL4IdT8r1ulYRtq3whKI2UY0a93W8K7IVO 5Vxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=+FTos3rUD6fh/en8KLJV4G7L5LRqhFG+pDtfRWiJ4eE=; b=G3U+LTV+J1id07Y6lZUatd0c5jN3WYmni9zJylibuo/RoQe5ci5Hd6McTjjck/hGmd 9PfGsZQ7tvGB7bCtcFNVsrj1sjFQ6TDA5TqP3cUtCDLMASMDIUy7LAMPZ2ebWFEnyt60 iHMwEriYjm92/1jUK9n0ADy4PSCCY0T4G84iRfIH/CIbagdEqgRC9Rncz6XXtOaz25wF fQRt0+7DA0KfvIJG+oF3gekaeIKb6pqr3PCgFWM4cVMN0yqsyXYnAnuJ4nfhv4IKdzSZ ISByoPqGsLszeksbU1JNLTwM4KVKz451j+KQxBaNLUydmhH2XJ9XKFHoryrfQFGDNTQE vuwA== X-Gm-Message-State: AOAM530PLKgTHILuvGxhKEi/4knWesOUVZV2Sss4eNrrADBkzvDM4UMB OZ7mPJ1dMHfvKwOZSaygKZc= X-Google-Smtp-Source: ABdhPJxYZ4rbaHcILzyWlE9KPQBwWGWiRKoO2wyI8Bh+kB5SFzpBeW1pnZlg6mZzO2YIMXHeq7hQhg== X-Received: by 2002:adf:a143:: with SMTP id r3mr47198040wrr.8.1635860696069; Tue, 02 Nov 2021 06:44:56 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 28/41] target/mips: Convert MSA COPY_U opcode to decodetree Date: Tue, 2 Nov 2021 14:42:27 +0100 Message-Id: <20211102134240.3036524-29-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860698740100001 Convert the COPY_U opcode (Element Copy to GPR Unsigned) to decodetree. Since the 'n' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20211028210843.2120802-26-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 1 + target/mips/tcg/msa_translate.c | 66 ++++++++++++++++++++------------- 2 files changed, 41 insertions(+), 26 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index bf014524eed..0e166a4e61d 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -167,6 +167,7 @@ BNZ 010001 111 .. ..... ...............= . @bz =20 SLDI 011110 0000 ...... ..... ..... 011001 @elm_df SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df + COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df INSVE 011110 0101 ...... ..... ..... 011001 @elm_df =20 FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 14e0a8879c4..4c560aa1e16 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -48,7 +48,6 @@ enum { OPC_CFCMSA =3D (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, OPC_COPY_S_df =3D (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_MOVE_V =3D (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_COPY_U_df =3D (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_INSERT_df =3D (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM, }; =20 @@ -592,6 +591,46 @@ TRANS(SLDI, trans_msa_elm, gen_helper_msa_sldi_df); TRANS(SPLATI, trans_msa_elm, gen_helper_msa_splati_df); TRANS(INSVE, trans_msa_elm, gen_helper_msa_insve_df); =20 +static bool trans_msa_elm_fn(DisasContext *ctx, arg_msa_elm_df *a, + gen_helper_piii * const gen_msa_elm[4]) +{ + if (a->df < 0 || !gen_msa_elm[a->df]) { + return false; + } + + if (check_msa_enabled(ctx)) { + return true; + } + + if (a->wd =3D=3D 0) { + /* Treat as NOP. */ + return true; + } + + gen_msa_elm[a->df](cpu_env, + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->n)); + + return true; +} + +#if defined(TARGET_MIPS64) +#define NULL_IF_MIPS32(function) function +#else +#define NULL_IF_MIPS32(function) NULL +#endif + +static bool trans_COPY_U(DisasContext *ctx, arg_msa_elm_df *a) +{ + static gen_helper_piii * const gen_msa_copy_u[4] =3D { + gen_helper_msa_copy_u_b, gen_helper_msa_copy_u_h, + NULL_IF_MIPS32(gen_helper_msa_copy_u_w), NULL + }; + + return trans_msa_elm_fn(ctx, a, gen_msa_copy_u); +} + static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) { #define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) @@ -604,7 +643,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t = df, uint32_t n) =20 switch (MASK_MSA_ELM(ctx->opcode)) { case OPC_COPY_S_df: - case OPC_COPY_U_df: case OPC_INSERT_df: #if !defined(TARGET_MIPS64) /* Double format valid only for MIPS64 */ @@ -612,11 +650,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t= df, uint32_t n) gen_reserved_instruction(ctx); break; } - if ((MASK_MSA_ELM(ctx->opcode) =3D=3D OPC_COPY_U_df) && - (df =3D=3D DF_WORD)) { - gen_reserved_instruction(ctx); - break; - } #endif switch (MASK_MSA_ELM(ctx->opcode)) { case OPC_COPY_S_df: @@ -635,25 +668,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t= df, uint32_t n) case DF_DOUBLE: gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn); break; -#endif - default: - assert(0); - } - } - break; - case OPC_COPY_U_df: - if (likely(wd !=3D 0)) { - switch (df) { - case DF_BYTE: - gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn); - break; - case DF_HALF: - gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn); - break; -#if defined(TARGET_MIPS64) - case DF_WORD: - gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn); - break; #endif default: assert(0); --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) client-ip=209.85.221.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860702; cv=none; d=zohomail.com; s=zohoarc; b=mQJTg31QVGpz4qnII0fL5NASOCizfdA9iMee7bLsxvo705ML1PhHdPdY/dzTfmi7v39/3Zm3XmMevxleI3s2ixtJ2aZjgwLTZUi1HjU38S961WRO9SQ4quhmf0L9j8DR8cEcC7TE0Y7ZiOvgfoeqZ1cOBGTRwJwvr54qYaPNtJs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id t6sm2834762wmq.31.2021.11.02.06.44.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:45:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SlIBW0robKr1+JSzc0Vq8Mi+aqJxXBwqayvOnhZrQto=; b=ZFxYgnYXX8ZlTxteR4x3XzMDFS5AhaBXGzM4o9OCV61MyeBpiBHJVtMJ9chFg+amJ4 u42Tj3G7TEahDDgjlxLs8hlSmmb0TnUUViDmcAYy/vK8PkPVk20lk45r1L6wWobdqKXt lzqpLRc+W9qNPWNG+Qmx8VkPd8M8tOV9Ae9lPcZ+BRNHD6qxAjZVoUjgOugJs3PHYH7u IwBf0yaz2PgdlTfSi0rphnDhN/zxxVytuN8oowXE5L2/qhbQiREtd7lR/Jp2+Mec3WHY dIkPZicVWf5mzAW+9nW9rHUL9cjhR7+eH4BJHKJ8mfaHIZSyiZosnIHh2gvW9x1J5fMP gz3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=SlIBW0robKr1+JSzc0Vq8Mi+aqJxXBwqayvOnhZrQto=; b=bzrZdMfDKhG6o/CS2uB3aZf1IiYQ3kOv6UAnXg/dgXEFduK6EQtFVLvKzeyA7SaCA6 g/mKNmD8JTWzY8yppem/dMtNaHA9tzAXWTcZO/wYnqu22OtwRl9cNZPWuiN56Q8WYYwP BdviAmOh7VjEFzfeB+UsNsnDHQ4NLteCsOSK0a09JFs2rITwg0U4SHN5vcqQm3yl7kQg cJujVH2bUkmsCPuWShewFXQ7XIqq25i71GjBLxXHNvfIXFwxNeZZV8ahgT0DAZFY/bKj APjLhRjVPI/CvNUN9OzUk+IwS5uwgMr2kt/99xVs+i98mv5OxQTfFiWZt9HXSqjueccz EP6g== X-Gm-Message-State: AOAM533xi5tBXe1hToOPUgDfqgvZZsqBjpKqS78N6egVt1PUziR8CMZg synJKo7LCLVnCTLCCKi3Ikc= X-Google-Smtp-Source: ABdhPJypKqL5rAeQdO8OogJb29MKKqNjkPAWIVWFeRVJI3/h4KSVqiHA3JdW4Ei7duFCDE1dT7OGNA== X-Received: by 2002:adf:ba0d:: with SMTP id o13mr46518334wrg.339.1635860700796; Tue, 02 Nov 2021 06:45:00 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 29/41] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree Date: Tue, 2 Nov 2021 14:42:28 +0100 Message-Id: <20211102134240.3036524-30-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860703441100001 Convert the COPY_S (Element Copy to GPR Signed) opcode and INSERT (GPR Insert Element) opcode to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-27-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 2 + target/mips/tcg/msa_translate.c | 103 +++++--------------------------- 2 files changed, 18 insertions(+), 87 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 0e166a4e61d..9aac6808fc5 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -167,7 +167,9 @@ BNZ 010001 111 .. ..... ...............= . @bz =20 SLDI 011110 0000 ...... ..... ..... 011001 @elm_df SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df + COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df + INSERT 011110 0100 ...... ..... ..... 011001 @elm_df INSVE 011110 0101 ...... ..... ..... 011001 @elm_df =20 FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 4c560aa1e16..6a034831efd 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -46,9 +46,7 @@ enum { /* ELM instructions df(bits 21..16) =3D _b, _h, _w, _d */ OPC_CTCMSA =3D (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, OPC_CFCMSA =3D (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_COPY_S_df =3D (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_MOVE_V =3D (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_INSERT_df =3D (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM, }; =20 static const char msaregnames[][6] =3D { @@ -631,98 +629,31 @@ static bool trans_COPY_U(DisasContext *ctx, arg_msa_e= lm_df *a) return trans_msa_elm_fn(ctx, a, gen_msa_copy_u); } =20 -static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) +static bool trans_COPY_S(DisasContext *ctx, arg_msa_elm_df *a) { -#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + static gen_helper_piii * const gen_msa_copy_s[4] =3D { + gen_helper_msa_copy_s_b, gen_helper_msa_copy_s_h, + gen_helper_msa_copy_s_w, NULL_IF_MIPS32(gen_helper_msa_copy_s_d) + }; =20 - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tn =3D tcg_const_i32(n); + return trans_msa_elm_fn(ctx, a, gen_msa_copy_s); +} =20 - switch (MASK_MSA_ELM(ctx->opcode)) { - case OPC_COPY_S_df: - case OPC_INSERT_df: -#if !defined(TARGET_MIPS64) - /* Double format valid only for MIPS64 */ - if (df =3D=3D DF_DOUBLE) { - gen_reserved_instruction(ctx); - break; - } -#endif - switch (MASK_MSA_ELM(ctx->opcode)) { - case OPC_COPY_S_df: - if (likely(wd !=3D 0)) { - switch (df) { - case DF_BYTE: - gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn); - break; - case DF_HALF: - gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn); - break; - case DF_WORD: - gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn); - break; -#if defined(TARGET_MIPS64) - case DF_DOUBLE: - gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn); - break; -#endif - default: - assert(0); - } - } - break; - case OPC_INSERT_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_insert_b(cpu_env, twd, tws, tn); - break; - case DF_HALF: - gen_helper_msa_insert_h(cpu_env, twd, tws, tn); - break; - case DF_WORD: - gen_helper_msa_insert_w(cpu_env, twd, tws, tn); - break; -#if defined(TARGET_MIPS64) - case DF_DOUBLE: - gen_helper_msa_insert_d(cpu_env, twd, tws, tn); - break; -#endif - default: - assert(0); - } - break; - } - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - } - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(tn); +static bool trans_INSERT(DisasContext *ctx, arg_msa_elm_df *a) +{ + static gen_helper_piii * const gen_msa_insert[4] =3D { + gen_helper_msa_insert_b, gen_helper_msa_insert_h, + gen_helper_msa_insert_w, NULL_IF_MIPS32(gen_helper_msa_insert_d) + }; + + return trans_msa_elm_fn(ctx, a, gen_msa_insert); } =20 static void gen_msa_elm(DisasContext *ctx) { uint8_t dfn =3D (ctx->opcode >> 16) & 0x3f; - uint32_t df =3D 0, n =3D 0; =20 - if ((dfn & 0x30) =3D=3D 0x00) { - n =3D dfn & 0x0f; - df =3D DF_BYTE; - } else if ((dfn & 0x38) =3D=3D 0x20) { - n =3D dfn & 0x07; - df =3D DF_HALF; - } else if ((dfn & 0x3c) =3D=3D 0x30) { - n =3D dfn & 0x03; - df =3D DF_WORD; - } else if ((dfn & 0x3e) =3D=3D 0x38) { - n =3D dfn & 0x01; - df =3D DF_DOUBLE; - } else if (dfn =3D=3D 0x3E) { + if (dfn =3D=3D 0x3E) { /* CTCMSA, CFCMSA, MOVE.V */ gen_msa_elm_3e(ctx); return; @@ -730,8 +661,6 @@ static void gen_msa_elm(DisasContext *ctx) gen_reserved_instruction(ctx); return; } - - gen_msa_elm_df(ctx, df, n); } =20 TRANS(FCAF, trans_msa_3rf, gen_helper_msa_fcaf_df); --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) client-ip=209.85.128.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860708; cv=none; d=zohomail.com; s=zohoarc; b=UV1Vg6cmm6KXpIQ7+xgwxikhWwWqsnureTWtK0SVG5WGRPGAA9sMfmNul91lSst/qL734ERDLUaX4MLYV3qaB7QFuw7HT/wDWgzm4UkWxPXMpIRPwD5WAW8hGZKosD4y6RHTBsJpXsL4g7n778tThuWdxD6c2AJKxbLJtn69mCI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860708; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; 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Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-28-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 7 ++++++- target/mips/tcg/msa_translate.c | 19 ++++++++++++++----- 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 9aac6808fc5..d1b6a63b526 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -19,6 +19,7 @@ &msa_i df wd ws sa &msa_bit df wd ws m &msa_elm_df df wd ws n +&msa_elm wd ws =20 %elm_df 16:6 !function=3Delm_df %elm_n 16:6 !function=3Delm_n @@ -33,6 +34,7 @@ @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3D3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz @elm_df ...... .... ...... ws:5 wd:5 ...... &msa_elm_df df= =3D%elm_df n=3D%elm_n +@elm ...... .......... ws:5 wd:5 ...... &msa_elm @vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=3D0 @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=3D0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=3D0 = df=3D%2r_df_w @@ -167,7 +169,10 @@ BNZ 010001 111 .. ..... ..............= .. @bz =20 SLDI 011110 0000 ...... ..... ..... 011001 @elm_df SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df - COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df + { + MOVE_V 011110 0010111110 ..... ..... 011001 @elm + COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df + } COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df INSERT 011110 0100 ...... ..... ..... 011001 @elm_df INSVE 011110 0101 ...... ..... ..... 011001 @elm_df diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 6a034831efd..ea572413ed6 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -46,7 +46,6 @@ enum { /* ELM instructions df(bits 21..16) =3D _b, _h, _w, _d */ OPC_CTCMSA =3D (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, OPC_CFCMSA =3D (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_MOVE_V =3D (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM, }; =20 static const char msaregnames[][6] =3D { @@ -533,6 +532,19 @@ TRANS_DF_iii_b(HADD_U, trans_msa_3r, gen_helper_msa= _hadd_u); TRANS_DF_iii_b(HSUB_S, trans_msa_3r, gen_helper_msa_hsub_s); TRANS_DF_iii_b(HSUB_U, trans_msa_3r, gen_helper_msa_hsub_u); =20 +static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm *a) +{ + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_helper_msa_move_v(cpu_env, + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws)); + + return true; +} + static void gen_msa_elm_3e(DisasContext *ctx) { #define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) @@ -551,9 +563,6 @@ static void gen_msa_elm_3e(DisasContext *ctx) gen_helper_msa_cfcmsa(telm, cpu_env, tsr); gen_store_gpr(telm, dest); break; - case OPC_MOVE_V: - gen_helper_msa_move_v(cpu_env, tdt, tsr); - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); @@ -654,7 +663,7 @@ static void gen_msa_elm(DisasContext *ctx) uint8_t dfn =3D (ctx->opcode >> 16) & 0x3f; =20 if (dfn =3D=3D 0x3E) { - /* CTCMSA, CFCMSA, MOVE.V */ + /* CTCMSA, CFCMSA */ gen_msa_elm_3e(ctx); return; } else { --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) client-ip=209.85.128.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860712; cv=none; d=zohomail.com; s=zohoarc; b=PMk0+BwRZlO10kbr2aP8JosjHfUnJlcnYsmChwimc4xqhWrl0Oc1E+IIEy0hcoiPDuNW5xxJ2hZhP+S0eAxyhY6GQyS6W6QEjlVeAyEh54N2iWK2WdXP6ZloCVz5jBx17MszCsCOa1QwfdhabDIQzWzOerPNvxzhGRy2A/etfIs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860712; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DfN9KCH7LHaF1iy9iJEh7uoGdvWg3DwUxmG5SexE/XE=; b=m4rPNyYKPzf4QFU1ydszcf4VmjmAjGZ60sXGwTptzI1/YXIg5vwUuFXdyxqhfZymGyvfjiSBUIutw0uokU0jsVl0qmwSpIoxt0V9WYn9469D8huWysser7fz9ni71l/YQ0zQcPW33bDU2E/+DG/YdlWj/tJfIH3NePLsFwD2WW0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.zohomail.com with SMTPS id 1635860712805275.20274493178; Tue, 2 Nov 2021 06:45:12 -0700 (PDT) Received: by mail-wm1-f43.google.com with SMTP id 77-20020a1c0450000000b0033123de3425so2013652wme.0 for ; Tue, 02 Nov 2021 06:45:12 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id t9sm12015195wrx.72.2021.11.02.06.45.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:45:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DfN9KCH7LHaF1iy9iJEh7uoGdvWg3DwUxmG5SexE/XE=; b=W972MXEskOIMjt5eoN+FbQFPGivD0lkA/d1clF00bKipEViIjaI3nTqpyfgJWwpbEH jQ8jpOoziDHfRl3yHi56L+qVtzJ8oH0jjDlovG7D4J0NAU+BhOd3McLNn3UWwsc6YclS cIDXebNBOJbp9NSbqQKlTz4wyisxCMHcgEp2O0Kyxv9kHlutPP+JLq6CuyNPry9rbDhz jezAuqah3ZYybqa2cwXwun5M96oByixSgO+FLNoBiXpa72jqC8ze54DwybFVEF+Dq5Db oizh2JqGPWV1Gw+UvWcbdSe2Tv2xooQYtCuH7uCIKuFUfGcOOySe/6EEHrNesh8vKrXR HpMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=DfN9KCH7LHaF1iy9iJEh7uoGdvWg3DwUxmG5SexE/XE=; b=E470zU/hhbcc8r72w6TTkI77T0oc1Cx7A7OFKKIjsZsm1nJ23yBxnuJQjjTiiKFgcY YbYHC0s76rcSMEWh94gPwQYb4Mbb6tpDNXMd1RH0O5uywc5J/FTfbN8iA8mugFuggeec mHLC/kLnR4GweMpx16+SQseEjwSNMvlTO6wKQkXMInt1ta323z3PhbbgfeuZMKexqupW naaP65OXyBH7C/PHrTFmsX+p7wJPVjMUs4ELH7DgZRUrBbJYbP4g4LXNq0QqZEbpf6qJ L3wPZ6rmUbrDgZTBvWPXuQJ1F6Ff49mc7Hn3MhGbag6JKSecIZ5q9Q+IzqkhsruVg8GY W4hw== X-Gm-Message-State: AOAM533ddUZrIrbDjiGpxuTeekHECJxrlRWnVvTGzn/16nwGZQDUpjca nX4YMTNnTtwdiDkJiDA9LLg= X-Google-Smtp-Source: ABdhPJwMPAMKHGD3ORbkhhUh4k7lcmo3N1u2r21hRp2Fef3htBn/lwMi03FucnXkcow1V02CRCFPfw== X-Received: by 2002:a7b:cb07:: with SMTP id u7mr7108742wmj.178.1635860711109; Tue, 02 Nov 2021 06:45:11 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 31/41] target/mips: Convert CFCMSA opcode to decodetree Date: Tue, 2 Nov 2021 14:42:30 +0100 Message-Id: <20211102134240.3036524-32-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860714791100003 Convert the CFCMSA (Copy From Control MSA register) opcode to decodetree. Since it overlaps with the SPLATI opcode, use a decodetree overlap group. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-29-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 5 ++++- target/mips/tcg/msa_translate.c | 27 +++++++++++++++++++-------- 2 files changed, 23 insertions(+), 9 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index d1b6a63b526..de8153a89bf 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -168,7 +168,10 @@ BNZ 010001 111 .. ..... ..............= .. @bz HSUB_U 011110 111.. ..... ..... ..... 010101 @3r =20 SLDI 011110 0000 ...... ..... ..... 011001 @elm_df - SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df + { + CFCMSA 011110 0001111110 ..... ..... 011001 @elm + SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df + } { MOVE_V 011110 0010111110 ..... ..... 011001 @elm COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index ea572413ed6..764b33741aa 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -45,7 +45,6 @@ enum { enum { /* ELM instructions df(bits 21..16) =3D _b, _h, _w, _d */ OPC_CTCMSA =3D (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_CFCMSA =3D (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, }; =20 static const char msaregnames[][6] =3D { @@ -551,7 +550,6 @@ static void gen_msa_elm_3e(DisasContext *ctx) uint8_t source =3D (ctx->opcode >> 11) & 0x1f; uint8_t dest =3D (ctx->opcode >> 6) & 0x1f; TCGv telm =3D tcg_temp_new(); - TCGv_i32 tsr =3D tcg_const_i32(source); TCGv_i32 tdt =3D tcg_const_i32(dest); =20 switch (MASK_MSA_ELM_DF3E(ctx->opcode)) { @@ -559,10 +557,6 @@ static void gen_msa_elm_3e(DisasContext *ctx) gen_load_gpr(telm, source); gen_helper_msa_ctcmsa(cpu_env, telm, tdt); break; - case OPC_CFCMSA: - gen_helper_msa_cfcmsa(telm, cpu_env, tsr); - gen_store_gpr(telm, dest); - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); @@ -571,7 +565,24 @@ static void gen_msa_elm_3e(DisasContext *ctx) =20 tcg_temp_free(telm); tcg_temp_free_i32(tdt); - tcg_temp_free_i32(tsr); +} + +static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a) +{ + TCGv telm; + + if (!check_msa_enabled(ctx)) { + return true; + } + + telm =3D tcg_temp_new(); + + gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws)); + gen_store_gpr(telm, a->wd); + + tcg_temp_free(telm); + + return true; } =20 static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a, @@ -663,7 +674,7 @@ static void gen_msa_elm(DisasContext *ctx) uint8_t dfn =3D (ctx->opcode >> 16) & 0x3f; =20 if (dfn =3D=3D 0x3E) { - /* CTCMSA, CFCMSA */ + /* CTCMSA */ gen_msa_elm_3e(ctx); return; } else { --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860717; cv=none; d=zohomail.com; s=zohoarc; b=RCXY87XpaTp1XQOHdJIDS7e9HIjGoklWrIfabgLpicrETdDUdnNrvQC8/YJWzTEpflZJa3SQWqHdY6bqgwoqCnikcjlwaZ34uEakCmI+ImtGaRzTO3REqrgacx+cavsOdJweB0NnLPqd/c3vJBppY8GufsvWy5ZKkkKyGF6Uv+4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860717; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+rHZaBWEEW+7a68nLLkWFu30mkgdivQFeUDplAmDWZU=; b=Ds9iXQIpI3S4Eaw3N9psGxLJZLtgahIiSi/HgNLRiu1JKUZv0ElW6uBj8gvDlpK/W2PDN9V5EkTHcdlDckHiopNkRMH60igEjt0yQe6XW+kzpXIqqRtVP3zjNIz+D34ijRGHaUBIYt/6MH9W+kABiplydWWlqZeCdH7trcL4hnM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mx.zohomail.com with SMTPS id 1635860717801804.218803823178; Tue, 2 Nov 2021 06:45:17 -0700 (PDT) Received: by mail-wr1-f53.google.com with SMTP id t30so8564144wra.10 for ; Tue, 02 Nov 2021 06:45:17 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id n66sm2715401wmn.2.2021.11.02.06.45.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:45:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+rHZaBWEEW+7a68nLLkWFu30mkgdivQFeUDplAmDWZU=; b=fa+8apDxxvoDqszJQTf/rav9DFVyqYIRWCHzyMBLhoblac2ti7v7v9z2yogOxyLqFr TmHioWGAY+CJ9Hu6yUSzXgqhNAlGye2Y6nhWOEi1aZZmpAeHIw1n8iIqyD7C/zL8nPGt 9jU0Ip4rVZuXxt6/LXNs80tQr70o4UOtDZa6YWw/iiqFvZGS6VfJz0Kj5GmtAMWcvYII oHUjBKQEJMf68MY0q5JlKLMEE6sdCSZQ3wMlsoi3Fe5z69HyyIZJTfQRGjVUdGczeuHt KJ8lNXzNl2NcorBjHZznQnkid181wEKgJsFEKXER4u5o6MWAlY4rgGRCzl+vlNuljZjH ZMbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=+rHZaBWEEW+7a68nLLkWFu30mkgdivQFeUDplAmDWZU=; b=74cv5/07LjPOHhPlKrklSkEULh/bFOQCI8gKXFzCKZxzVXS50VuHllJbPPIV1ZJgg3 QYx4re5ezjmf6WxcE45fqUMD/I52mWaYM+j2lgx8Fzh3Ek2QKEHkdLZlwmTBU+39L078 zY0CzwM9ASKNRn1UQtMpvObwxEOdfl4uuNDaXtuB76uKYFB9gwVqNiwX2yTItb5lp/d4 mYX0i0TzhFs52NW9OxkfDSUpNpFA3pKmxnJhEm7GWDWUcMbI1R5rRu05nCR82hGvmRgs bWnvYkRzAn5vi78TcOCj58rSgrb2Ft1V80Axvwpn8wRPVT+mxIoSiLvsCThF5IFh2m6n Q8Cw== X-Gm-Message-State: AOAM531zEz/Yw2K9a+HUXdAPj/z0ul3DHRrB6GwLLHRrKDA2y61fIuJX cM2c+q2Z+wN+AL4Jr7+2CMY= X-Google-Smtp-Source: ABdhPJyQGK1+TNNqiHTyFmdt1b9R4keO05MVCSs/XfUa+4664lMyOMVvcrrBtxmCEnENnZOpBF3Nhg== X-Received: by 2002:adf:959a:: with SMTP id p26mr46426802wrp.342.1635860716043; Tue, 02 Nov 2021 06:45:16 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 32/41] target/mips: Convert CTCMSA opcode to decodetree Date: Tue, 2 Nov 2021 14:42:31 +0100 Message-Id: <20211102134240.3036524-33-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860719767100001 Convert the CTCMSA (Copy To Control MSA register) opcode to decodetree. Since it overlaps with the SLDI opcode, use a decodetree overlap group. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-30-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 5 ++- target/mips/tcg/msa_translate.c | 69 ++++++--------------------------- 2 files changed, 16 insertions(+), 58 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index de8153a89bf..a4c7cceb15f 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -167,7 +167,10 @@ BNZ 010001 111 .. ..... ..............= .. @bz HSUB_S 011110 110.. ..... ..... ..... 010101 @3r HSUB_U 011110 111.. ..... ..... ..... 010101 @3r =20 - SLDI 011110 0000 ...... ..... ..... 011001 @elm_df + { + CTCMSA 011110 0000111110 ..... ..... 011001 @elm + SLDI 011110 0000 ...... ..... ..... 011001 @elm_df + } { CFCMSA 011110 0001111110 ..... ..... 011001 @elm SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 764b33741aa..c054a05f8ba 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -35,18 +35,6 @@ static inline int plus_2(DisasContext *s, int x) /* Include the auto-generated decoder. */ #include "decode-msa.c.inc" =20 -#define OPC_MSA (0x1E << 26) - -#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) -enum { - OPC_MSA_ELM =3D 0x19 | OPC_MSA, -}; - -enum { - /* ELM instructions df(bits 21..16) =3D _b, _h, _w, _d */ - OPC_CTCMSA =3D (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, -}; - static const char msaregnames[][6] =3D { "w0.d0", "w0.d1", "w1.d0", "w1.d1", "w2.d0", "w2.d1", "w3.d0", "w3.d1", @@ -544,27 +532,22 @@ static bool trans_MOVE_V(DisasContext *ctx, arg_msa_e= lm *a) return true; } =20 -static void gen_msa_elm_3e(DisasContext *ctx) +static bool trans_CTCMSA(DisasContext *ctx, arg_msa_elm *a) { -#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) - uint8_t source =3D (ctx->opcode >> 11) & 0x1f; - uint8_t dest =3D (ctx->opcode >> 6) & 0x1f; - TCGv telm =3D tcg_temp_new(); - TCGv_i32 tdt =3D tcg_const_i32(dest); + TCGv telm; =20 - switch (MASK_MSA_ELM_DF3E(ctx->opcode)) { - case OPC_CTCMSA: - gen_load_gpr(telm, source); - gen_helper_msa_ctcmsa(cpu_env, telm, tdt); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; + if (!check_msa_enabled(ctx)) { + return true; } =20 + telm =3D tcg_temp_new(); + + gen_load_gpr(telm, a->ws); + gen_helper_msa_ctcmsa(cpu_env, telm, tcg_constant_i32(a->wd)); + tcg_temp_free(telm); - tcg_temp_free_i32(tdt); + + return true; } =20 static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a) @@ -669,20 +652,6 @@ static bool trans_INSERT(DisasContext *ctx, arg_msa_el= m_df *a) return trans_msa_elm_fn(ctx, a, gen_msa_insert); } =20 -static void gen_msa_elm(DisasContext *ctx) -{ - uint8_t dfn =3D (ctx->opcode >> 16) & 0x3f; - - if (dfn =3D=3D 0x3E) { - /* CTCMSA */ - gen_msa_elm_3e(ctx); - return; - } else { - gen_reserved_instruction(ctx); - return; - } -} - TRANS(FCAF, trans_msa_3rf, gen_helper_msa_fcaf_df); TRANS(FCUN, trans_msa_3rf, gen_helper_msa_fcun_df); TRANS(FCEQ, trans_msa_3rf, gen_helper_msa_fceq_df); @@ -796,21 +765,7 @@ TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_= df); =20 static bool trans_MSA(DisasContext *ctx, arg_MSA *a) { - uint32_t opcode =3D ctx->opcode; - - if (!check_msa_enabled(ctx)) { - return true; - } - - switch (MASK_MSA_MINOR(opcode)) { - case OPC_MSA_ELM: - gen_msa_elm(ctx); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } + gen_reserved_instruction(ctx); =20 return true; } --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) client-ip=209.85.128.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860722; cv=none; d=zohomail.com; s=zohoarc; b=jnGP4CmymozO8g8XUZa4y4V/5n+tfVyWm6ovEY3ZM1Bw/Ak5xBYCv0YkzOIvVmhjoI4vryK5X8TDTlRjo8f6eGmhhXmvH3DOOB6pab0bHtsWlzqyUHAxyE0hGOL1Bi7r1x0yb92mkbz+pvXU6tX2tQ2pbRGW7+bOG7kQpgGo5qM= ARC-Message-Signature: i=1; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id f24sm2476764wmb.33.2021.11.02.06.45.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:45:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I5Etaa8zIcgqaaU17Qo9AH5Dp8AYr3wzcYrvFLqw+7U=; b=F+qjG1XNhbAIR0xn75ds+/5R2Is3lLlYOBIZ3IHDQwb8p0sCnJmSn59UrjhWrlof4X Zh339WDCwqDhQFyfLJdVEGaTdiZlsQfmFOShvqASR01Qnh8BU+tNHXF07+Hf6UXT6QuZ 4Ga7h61pX/tpI8LwvDha7kX5TvqkPt2RzaeyEfkMbUj/hs4P8MUNC2toZxZNG5xB6Yfd cXJZiP0V2WBN9p6hPqf50amPZGpTdlYPNxoOt05z0Y3dtebxOHYiugjdxGBhuUTk1r9w BE5QbXe4+KdNJ1wZ2Fj8r/NMJLLqK2PH7r6g6UlhHyjn4qlCa9VlFYWZ8F4Tv7qohSSn tkeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=I5Etaa8zIcgqaaU17Qo9AH5Dp8AYr3wzcYrvFLqw+7U=; b=Tpm7qGZHnhrC0n0wIjKTbAcRpgRO19pTxzfnTR4Lf6sCJrHhknhUTbT2dPeeGreJNM /xKxYkxybxQM4RJKaTF5OwCjCND4pr5IZdt4ld4yGZ7JkNH5KwQfvwDYw+cpLcDJgHOW 3vzpigPPvCsigx2jqnRGBh53y1hJlaSxgholXgN6WXCBuSDpkU4fpGEyz27CkZbnPcBO X+if9cYuh0f+rYEEUxXLsqakY/cdYrG8aagUMJFCmCgoDTEKvW2MVjfTtEnjS/3nwb8E mp4v/9J1ADpxB+jjeKG8k3tcgaTucACWlMlFvPapOuY3rdGdkdnJr+WlgNZAUmfW2kw9 PSzQ== X-Gm-Message-State: AOAM531GjElgt0ogkXDRneiWZxyAas9n8jrXffXrr+EfKUthSaQuoMu6 u1V/vGfc5mnVuRk/fie1lnU= X-Google-Smtp-Source: ABdhPJxXpVY6CmCg9NFGa8sYZJzj5dZyYftuJ9cfGLdr2WXcOoE4WJ1Oh0CJKpZw9q0IVXETjcttvA== X-Received: by 2002:a05:600c:ad0:: with SMTP id c16mr6864761wmr.176.1635860721141; Tue, 02 Nov 2021 06:45:21 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 33/41] target/mips: Remove generic MSA opcode Date: Tue, 2 Nov 2021 14:42:32 +0100 Message-Id: <20211102134240.3036524-34-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860724448100001 All opcodes have been converted to decodetree. The generic MSA handler is now pointless, remove it. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-31-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 2 -- target/mips/tcg/msa_translate.c | 7 ------- 2 files changed, 9 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index a4c7cceb15f..124768132ba 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -257,6 +257,4 @@ BNZ 010001 111 .. ..... ...............= . @bz =20 LD 011110 .......... ..... ..... 1000 .. @ldst ST 011110 .......... ..... ..... 1001 .. @ldst - - MSA 011110 -------------------------- } diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index c054a05f8ba..7576b3ed86b 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -763,13 +763,6 @@ TRANS(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_= df); TRANS(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df); TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df); =20 -static bool trans_MSA(DisasContext *ctx, arg_MSA *a) -{ - gen_reserved_instruction(ctx); - - return true; -} - static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, gen_helper_piv *gen_msa_ldst) { --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860727; cv=none; d=zohomail.com; s=zohoarc; b=lhoT2nHtiueOOZWd8nvkD62q0GEhwMPlhIcxLdflcgSTN+wodGn/0BthS1t3Zxd6PTNCuLcqsbYRw/RBdCXWvMrgRNvqg/kxQ/0RKCxY1B11D+MmfhAQo5yP+h+dh15kOnL/gEb7Wa+c4jkAgThI5eoBTBD6ciVBNl1WA6ICqqU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860727; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mbPpFP9IPA2wXzUBxuHciFVrxDYF6qdrb181+WZfmQs=; b=ii7NEe426xq5GcYXarKxCtkMwjGcRRzvQu85NrNsU+tCXf9A3P+xwbFAbLcBkb5CGVqEYlAo0WZz5dN6UvPeBShufr053D9d0Q5vZOnme2Gp9HgHr5ebhOFFuPMLCWRkT6m7XqkSecL5yxf4G0lc4imYj9GQtSAURbdo+xtkkVM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mx.zohomail.com with SMTPS id 1635860727797121.32313141455109; Tue, 2 Nov 2021 06:45:27 -0700 (PDT) Received: by mail-wr1-f53.google.com with SMTP id b12so28963024wrh.4 for ; Tue, 02 Nov 2021 06:45:27 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id t8sm16205177wrv.30.2021.11.02.06.45.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:45:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mbPpFP9IPA2wXzUBxuHciFVrxDYF6qdrb181+WZfmQs=; b=L3/1I++TwT1CxQEdRc/8VEj/aHwFhzzc423CdOKhlj8U/Il38H3kV0UOxKilB3BDVr RN+jY/0n4eDq1CqwERNnlt61koYIgdIJXgv7CtVADQpksgGy7Ci+r84diHNQyd9y1RiL jdWL4FMs5+sQ0aPBC0nRH5o6zQsdt3oEyByu6ZK4LEzIJjljNTmO2OGaM/gqRGrHj6Bw mOpm778iJXlebX0ETZr+NoOZk7vO5biPiNUvlg7KhOxAjxh48NYEJrtEJihSz9DynS+7 wTTrBw6E47zmyV4bVN5ijYiEDHvLYANnXV8U8pAEqJnwjK52IXsEzG30sXh/rCZjCwxK 8qlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=mbPpFP9IPA2wXzUBxuHciFVrxDYF6qdrb181+WZfmQs=; b=Q9qtB4Gztr5W1nK1FhwTnMGD9lV7GmQK6vj3jZC6qf1sRfD3aAjTQESoMh9PVSxWQn XnljASrJkLKV+zpb6eXznGsAcDnuyV4Dmte73np9T8FVBGyAH1YFRaSpv5JV/7idRU8n EzOx8sHmLK06XLRHVaUMm05uMI1ZAITx9laGACT2GMLXeL6dUJeHXaQBmCRMBg6CRgq/ xgaGkOv3J2plGz7aIpM8SB8gNnAuZsxEeG9wlEe+wcFf6pS+eNa9+rFHlfezs9HxSIsm sthWIK+8IEbHgdxcXfPSJcyC0bPkaAI5VVaIZ9IEQPvFeXmp+XRVtCc9Mz6ljJ6HVJqY cg1Q== X-Gm-Message-State: AOAM530j2UhqUJ9gzD/a0csNvFHxXhtK1Z03JRO229PwblTf0Hzd/vhu Gew1Sc5mgPlpLGUdpTvS6SY= X-Google-Smtp-Source: ABdhPJytiQ3pv+1KR6l9PwquMBmGrXD16wmojFZKFzwZA6jHvjfQGgVDgDOVuv46TucjxmM2Yc7UCQ== X-Received: by 2002:a05:6000:1849:: with SMTP id c9mr48646466wri.394.1635860725821; Tue, 02 Nov 2021 06:45:25 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 34/41] target/mips: Remove one MSA unnecessary decodetree overlap group Date: Tue, 2 Nov 2021 14:42:33 +0100 Message-Id: <20211102134240.3036524-35-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860728949100003 Only the MSA generic opcode was overlapping with the other instructions. Since the previous commit removed it, we can now remove the overlap group. The decodetree script forces us to re-indent the opcodes. Diff trivial to review using `git-diff --ignore-all-space`. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211028210843.2120802-32-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 398 ++++++++++++++++++------------------- 1 file changed, 198 insertions(+), 200 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 124768132ba..95752891956 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -56,205 +56,203 @@ BNZ_V 010001 01111 ..... .............= ... @bz_v BZ 010001 110 .. ..... ................ @bz BNZ 010001 111 .. ..... ................ @bz =20 +ANDI 011110 00 ........ ..... ..... 000000 @i8 +ORI 011110 01 ........ ..... ..... 000000 @i8 +NORI 011110 10 ........ ..... ..... 000000 @i8 +XORI 011110 11 ........ ..... ..... 000000 @i8 +BMNZI 011110 00 ........ ..... ..... 000001 @i8 +BMZI 011110 01 ........ ..... ..... 000001 @i8 +BSELI 011110 10 ........ ..... ..... 000001 @i8 +SHF 011110 .. ........ ..... ..... 000010 @i8_df + +ADDVI 011110 000 .. ..... ..... ..... 000110 @u5 +SUBVI 011110 001 .. ..... ..... ..... 000110 @u5 +MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5 +MAXI_U 011110 011 .. ..... ..... ..... 000110 @u5 +MINI_S 011110 100 .. ..... ..... ..... 000110 @s5 +MINI_U 011110 101 .. ..... ..... ..... 000110 @u5 + +CEQI 011110 000 .. ..... ..... ..... 000111 @s5 +CLTI_S 011110 010 .. ..... ..... ..... 000111 @s5 +CLTI_U 011110 011 .. ..... ..... ..... 000111 @u5 +CLEI_S 011110 100 .. ..... ..... ..... 000111 @s5 +CLEI_U 011110 101 .. ..... ..... ..... 000111 @u5 + +LDI 011110 110 .. .......... ..... 000111 @ldi + +SLLI 011110 000 ....... ..... ..... 001001 @bit +SRAI 011110 001 ....... ..... ..... 001001 @bit +SRLI 011110 010 ....... ..... ..... 001001 @bit +BCLRI 011110 011 ....... ..... ..... 001001 @bit +BSETI 011110 100 ....... ..... ..... 001001 @bit +BNEGI 011110 101 ....... ..... ..... 001001 @bit +BINSLI 011110 110 ....... ..... ..... 001001 @bit +BINSRI 011110 111 ....... ..... ..... 001001 @bit + +SAT_S 011110 000 ....... ..... ..... 001010 @bit +SAT_U 011110 001 ....... ..... ..... 001010 @bit +SRARI 011110 010 ....... ..... ..... 001010 @bit +SRLRI 011110 011 ....... ..... ..... 001010 @bit + +SLL 011110 000.. ..... ..... ..... 001101 @3r +SRA 011110 001.. ..... ..... ..... 001101 @3r +SRL 011110 010.. ..... ..... ..... 001101 @3r +BCLR 011110 011.. ..... ..... ..... 001101 @3r +BSET 011110 100.. ..... ..... ..... 001101 @3r +BNEG 011110 101.. ..... ..... ..... 001101 @3r +BINSL 011110 110.. ..... ..... ..... 001101 @3r +BINSR 011110 111.. ..... ..... ..... 001101 @3r + +ADDV 011110 000.. ..... ..... ..... 001110 @3r +SUBV 011110 001.. ..... ..... ..... 001110 @3r +MAX_S 011110 010.. ..... ..... ..... 001110 @3r +MAX_U 011110 011.. ..... ..... ..... 001110 @3r +MIN_S 011110 100.. ..... ..... ..... 001110 @3r +MIN_U 011110 101.. ..... ..... ..... 001110 @3r +MAX_A 011110 110.. ..... ..... ..... 001110 @3r +MIN_A 011110 111.. ..... ..... ..... 001110 @3r + +CEQ 011110 000.. ..... ..... ..... 001111 @3r +CLT_S 011110 010.. ..... ..... ..... 001111 @3r +CLT_U 011110 011.. ..... ..... ..... 001111 @3r +CLE_S 011110 100.. ..... ..... ..... 001111 @3r +CLE_U 011110 101.. ..... ..... ..... 001111 @3r + +ADD_A 011110 000.. ..... ..... ..... 010000 @3r +ADDS_A 011110 001.. ..... ..... ..... 010000 @3r +ADDS_S 011110 010.. ..... ..... ..... 010000 @3r +ADDS_U 011110 011.. ..... ..... ..... 010000 @3r +AVE_S 011110 100.. ..... ..... ..... 010000 @3r +AVE_U 011110 101.. ..... ..... ..... 010000 @3r +AVER_S 011110 110.. ..... ..... ..... 010000 @3r +AVER_U 011110 111.. ..... ..... ..... 010000 @3r + +SUBS_S 011110 000.. ..... ..... ..... 010001 @3r +SUBS_U 011110 001.. ..... ..... ..... 010001 @3r +SUBSUS_U 011110 010.. ..... ..... ..... 010001 @3r +SUBSUU_S 011110 011.. ..... ..... ..... 010001 @3r +ASUB_S 011110 100.. ..... ..... ..... 010001 @3r +ASUB_U 011110 101.. ..... ..... ..... 010001 @3r + +MULV 011110 000.. ..... ..... ..... 010010 @3r +MADDV 011110 001.. ..... ..... ..... 010010 @3r +MSUBV 011110 010.. ..... ..... ..... 010010 @3r +DIV_S 011110 100.. ..... ..... ..... 010010 @3r +DIV_U 011110 101.. ..... ..... ..... 010010 @3r +MOD_S 011110 110.. ..... ..... ..... 010010 @3r +MOD_U 011110 111.. ..... ..... ..... 010010 @3r + +DOTP_S 011110 000.. ..... ..... ..... 010011 @3r +DOTP_U 011110 001.. ..... ..... ..... 010011 @3r +DPADD_S 011110 010.. ..... ..... ..... 010011 @3r +DPADD_U 011110 011.. ..... ..... ..... 010011 @3r +DPSUB_S 011110 100.. ..... ..... ..... 010011 @3r +DPSUB_U 011110 101.. ..... ..... ..... 010011 @3r + +SLD 011110 000 .. ..... ..... ..... 010100 @3r +SPLAT 011110 001 .. ..... ..... ..... 010100 @3r +PCKEV 011110 010 .. ..... ..... ..... 010100 @3r +PCKOD 011110 011 .. ..... ..... ..... 010100 @3r +ILVL 011110 100 .. ..... ..... ..... 010100 @3r +ILVR 011110 101 .. ..... ..... ..... 010100 @3r +ILVEV 011110 110 .. ..... ..... ..... 010100 @3r +ILVOD 011110 111 .. ..... ..... ..... 010100 @3r + +VSHF 011110 000 .. ..... ..... ..... 010101 @3r +SRAR 011110 001 .. ..... ..... ..... 010101 @3r +SRLR 011110 010 .. ..... ..... ..... 010101 @3r +HADD_S 011110 100.. ..... ..... ..... 010101 @3r +HADD_U 011110 101.. ..... ..... ..... 010101 @3r +HSUB_S 011110 110.. ..... ..... ..... 010101 @3r +HSUB_U 011110 111.. ..... ..... ..... 010101 @3r + { - ANDI 011110 00 ........ ..... ..... 000000 @i8 - ORI 011110 01 ........ ..... ..... 000000 @i8 - NORI 011110 10 ........ ..... ..... 000000 @i8 - XORI 011110 11 ........ ..... ..... 000000 @i8 - BMNZI 011110 00 ........ ..... ..... 000001 @i8 - BMZI 011110 01 ........ ..... ..... 000001 @i8 - BSELI 011110 10 ........ ..... ..... 000001 @i8 - SHF 011110 .. ........ ..... ..... 000010 @i8_df - - ADDVI 011110 000 .. ..... ..... ..... 000110 @u5 - SUBVI 011110 001 .. ..... ..... ..... 000110 @u5 - MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5 - MAXI_U 011110 011 .. ..... ..... ..... 000110 @u5 - MINI_S 011110 100 .. ..... ..... ..... 000110 @s5 - MINI_U 011110 101 .. ..... ..... ..... 000110 @u5 - - CEQI 011110 000 .. ..... ..... ..... 000111 @s5 - CLTI_S 011110 010 .. ..... ..... ..... 000111 @s5 - CLTI_U 011110 011 .. ..... ..... ..... 000111 @u5 - CLEI_S 011110 100 .. ..... ..... ..... 000111 @s5 - CLEI_U 011110 101 .. ..... ..... ..... 000111 @u5 - - LDI 011110 110 .. .......... ..... 000111 @ldi - - SLLI 011110 000 ....... ..... ..... 001001 @bit - SRAI 011110 001 ....... ..... ..... 001001 @bit - SRLI 011110 010 ....... ..... ..... 001001 @bit - BCLRI 011110 011 ....... ..... ..... 001001 @bit - BSETI 011110 100 ....... ..... ..... 001001 @bit - BNEGI 011110 101 ....... ..... ..... 001001 @bit - BINSLI 011110 110 ....... ..... ..... 001001 @bit - BINSRI 011110 111 ....... ..... ..... 001001 @bit - - SAT_S 011110 000 ....... ..... ..... 001010 @bit - SAT_U 011110 001 ....... ..... ..... 001010 @bit - SRARI 011110 010 ....... ..... ..... 001010 @bit - SRLRI 011110 011 ....... ..... ..... 001010 @bit - - SLL 011110 000.. ..... ..... ..... 001101 @3r - SRA 011110 001.. ..... ..... ..... 001101 @3r - SRL 011110 010.. ..... ..... ..... 001101 @3r - BCLR 011110 011.. ..... ..... ..... 001101 @3r - BSET 011110 100.. ..... ..... ..... 001101 @3r - BNEG 011110 101.. ..... ..... ..... 001101 @3r - BINSL 011110 110.. ..... ..... ..... 001101 @3r - BINSR 011110 111.. ..... ..... ..... 001101 @3r - - ADDV 011110 000.. ..... ..... ..... 001110 @3r - SUBV 011110 001.. ..... ..... ..... 001110 @3r - MAX_S 011110 010.. ..... ..... ..... 001110 @3r - MAX_U 011110 011.. ..... ..... ..... 001110 @3r - MIN_S 011110 100.. ..... ..... ..... 001110 @3r - MIN_U 011110 101.. ..... ..... ..... 001110 @3r - MAX_A 011110 110.. ..... ..... ..... 001110 @3r - MIN_A 011110 111.. ..... ..... ..... 001110 @3r - - CEQ 011110 000.. ..... ..... ..... 001111 @3r - CLT_S 011110 010.. ..... ..... ..... 001111 @3r - CLT_U 011110 011.. ..... ..... ..... 001111 @3r - CLE_S 011110 100.. ..... ..... ..... 001111 @3r - CLE_U 011110 101.. ..... ..... ..... 001111 @3r - - ADD_A 011110 000.. ..... ..... ..... 010000 @3r - ADDS_A 011110 001.. ..... ..... ..... 010000 @3r - ADDS_S 011110 010.. ..... ..... ..... 010000 @3r - ADDS_U 011110 011.. ..... ..... ..... 010000 @3r - AVE_S 011110 100.. ..... ..... ..... 010000 @3r - AVE_U 011110 101.. ..... ..... ..... 010000 @3r - AVER_S 011110 110.. ..... ..... ..... 010000 @3r - AVER_U 011110 111.. ..... ..... ..... 010000 @3r - - SUBS_S 011110 000.. ..... ..... ..... 010001 @3r - SUBS_U 011110 001.. ..... ..... ..... 010001 @3r - SUBSUS_U 011110 010.. ..... ..... ..... 010001 @3r - SUBSUU_S 011110 011.. ..... ..... ..... 010001 @3r - ASUB_S 011110 100.. ..... ..... ..... 010001 @3r - ASUB_U 011110 101.. ..... ..... ..... 010001 @3r - - MULV 011110 000.. ..... ..... ..... 010010 @3r - MADDV 011110 001.. ..... ..... ..... 010010 @3r - MSUBV 011110 010.. ..... ..... ..... 010010 @3r - DIV_S 011110 100.. ..... ..... ..... 010010 @3r - DIV_U 011110 101.. ..... ..... ..... 010010 @3r - MOD_S 011110 110.. ..... ..... ..... 010010 @3r - MOD_U 011110 111.. ..... ..... ..... 010010 @3r - - DOTP_S 011110 000.. ..... ..... ..... 010011 @3r - DOTP_U 011110 001.. ..... ..... ..... 010011 @3r - DPADD_S 011110 010.. ..... ..... ..... 010011 @3r - DPADD_U 011110 011.. ..... ..... ..... 010011 @3r - DPSUB_S 011110 100.. ..... ..... ..... 010011 @3r - DPSUB_U 011110 101.. ..... ..... ..... 010011 @3r - - SLD 011110 000 .. ..... ..... ..... 010100 @3r - SPLAT 011110 001 .. ..... ..... ..... 010100 @3r - PCKEV 011110 010 .. ..... ..... ..... 010100 @3r - PCKOD 011110 011 .. ..... ..... ..... 010100 @3r - ILVL 011110 100 .. ..... ..... ..... 010100 @3r - ILVR 011110 101 .. ..... ..... ..... 010100 @3r - ILVEV 011110 110 .. ..... ..... ..... 010100 @3r - ILVOD 011110 111 .. ..... ..... ..... 010100 @3r - - VSHF 011110 000 .. ..... ..... ..... 010101 @3r - SRAR 011110 001 .. ..... ..... ..... 010101 @3r - SRLR 011110 010 .. ..... ..... ..... 010101 @3r - HADD_S 011110 100.. ..... ..... ..... 010101 @3r - HADD_U 011110 101.. ..... ..... ..... 010101 @3r - HSUB_S 011110 110.. ..... ..... ..... 010101 @3r - HSUB_U 011110 111.. ..... ..... ..... 010101 @3r - - { - CTCMSA 011110 0000111110 ..... ..... 011001 @elm - SLDI 011110 0000 ...... ..... ..... 011001 @elm_df - } - { - CFCMSA 011110 0001111110 ..... ..... 011001 @elm - SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df - } - { - MOVE_V 011110 0010111110 ..... ..... 011001 @elm - COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df - } - COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df - INSERT 011110 0100 ...... ..... ..... 011001 @elm_df - INSVE 011110 0101 ...... ..... ..... 011001 @elm_df - - FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w - FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w - FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf_w - FCUEQ 011110 0011 . ..... ..... ..... 011010 @3rf_w - FCLT 011110 0100 . ..... ..... ..... 011010 @3rf_w - FCULT 011110 0101 . ..... ..... ..... 011010 @3rf_w - FCLE 011110 0110 . ..... ..... ..... 011010 @3rf_w - FCULE 011110 0111 . ..... ..... ..... 011010 @3rf_w - FSAF 011110 1000 . ..... ..... ..... 011010 @3rf_w - FSUN 011110 1001 . ..... ..... ..... 011010 @3rf_w - FSEQ 011110 1010 . ..... ..... ..... 011010 @3rf_w - FSUEQ 011110 1011 . ..... ..... ..... 011010 @3rf_w - FSLT 011110 1100 . ..... ..... ..... 011010 @3rf_w - FSULT 011110 1101 . ..... ..... ..... 011010 @3rf_w - FSLE 011110 1110 . ..... ..... ..... 011010 @3rf_w - FSULE 011110 1111 . ..... ..... ..... 011010 @3rf_w - - FADD 011110 0000 . ..... ..... ..... 011011 @3rf_w - FSUB 011110 0001 . ..... ..... ..... 011011 @3rf_w - FMUL 011110 0010 . ..... ..... ..... 011011 @3rf_w - FDIV 011110 0011 . ..... ..... ..... 011011 @3rf_w - FMADD 011110 0100 . ..... ..... ..... 011011 @3rf_w - FMSUB 011110 0101 . ..... ..... ..... 011011 @3rf_w - FEXP2 011110 0111 . ..... ..... ..... 011011 @3rf_w - FEXDO 011110 1000 . ..... ..... ..... 011011 @3rf_w - FTQ 011110 1010 . ..... ..... ..... 011011 @3rf_w - FMIN 011110 1100 . ..... ..... ..... 011011 @3rf_w - FMIN_A 011110 1101 . ..... ..... ..... 011011 @3rf_w - FMAX 011110 1110 . ..... ..... ..... 011011 @3rf_w - FMAX_A 011110 1111 . ..... ..... ..... 011011 @3rf_w - - FCOR 011110 0001 . ..... ..... ..... 011100 @3rf_w - FCUNE 011110 0010 . ..... ..... ..... 011100 @3rf_w - FCNE 011110 0011 . ..... ..... ..... 011100 @3rf_w - MUL_Q 011110 0100 . ..... ..... ..... 011100 @3rf_h - MADD_Q 011110 0101 . ..... ..... ..... 011100 @3rf_h - MSUB_Q 011110 0110 . ..... ..... ..... 011100 @3rf_h - FSOR 011110 1001 . ..... ..... ..... 011100 @3rf_w - FSUNE 011110 1010 . ..... ..... ..... 011100 @3rf_w - FSNE 011110 1011 . ..... ..... ..... 011100 @3rf_w - MULR_Q 011110 1100 . ..... ..... ..... 011100 @3rf_h - MADDR_Q 011110 1101 . ..... ..... ..... 011100 @3rf_h - MSUBR_Q 011110 1110 . ..... ..... ..... 011100 @3rf_h - - AND_V 011110 00000 ..... ..... ..... 011110 @vec - OR_V 011110 00001 ..... ..... ..... 011110 @vec - NOR_V 011110 00010 ..... ..... ..... 011110 @vec - XOR_V 011110 00011 ..... ..... ..... 011110 @vec - BMNZ_V 011110 00100 ..... ..... ..... 011110 @vec - BMZ_V 011110 00101 ..... ..... ..... 011110 @vec - BSEL_V 011110 00110 ..... ..... ..... 011110 @vec - FILL 011110 11000000 .. ..... ..... 011110 @2r - PCNT 011110 11000001 .. ..... ..... 011110 @2r - NLOC 011110 11000010 .. ..... ..... 011110 @2r - NLZC 011110 11000011 .. ..... ..... 011110 @2r - FCLASS 011110 110010000 . ..... ..... 011110 @2rf - FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf - FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf - FSQRT 011110 110010011 . ..... ..... 011110 @2rf - FRSQRT 011110 110010100 . ..... ..... 011110 @2rf - FRCP 011110 110010101 . ..... ..... 011110 @2rf - FRINT 011110 110010110 . ..... ..... 011110 @2rf - FLOG2 011110 110010111 . ..... ..... 011110 @2rf - FEXUPL 011110 110011000 . ..... ..... 011110 @2rf - FEXUPR 011110 110011001 . ..... ..... 011110 @2rf - FFQL 011110 110011010 . ..... ..... 011110 @2rf - FFQR 011110 110011011 . ..... ..... 011110 @2rf - FTINT_S 011110 110011100 . ..... ..... 011110 @2rf - FTINT_U 011110 110011101 . ..... ..... 011110 @2rf - FFINT_S 011110 110011110 . ..... ..... 011110 @2rf - FFINT_U 011110 110011111 . ..... ..... 011110 @2rf - - LD 011110 .......... ..... ..... 1000 .. @ldst - ST 011110 .......... ..... ..... 1001 .. @ldst + CTCMSA 011110 0000111110 ..... ..... 011001 @elm + SLDI 011110 0000 ...... ..... ..... 011001 @elm_df } +{ + CFCMSA 011110 0001111110 ..... ..... 011001 @elm + SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df +} +{ + MOVE_V 011110 0010111110 ..... ..... 011001 @elm + COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df +} +COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df +INSERT 011110 0100 ...... ..... ..... 011001 @elm_df +INSVE 011110 0101 ...... ..... ..... 011001 @elm_df + +FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w +FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w +FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf_w +FCUEQ 011110 0011 . ..... ..... ..... 011010 @3rf_w +FCLT 011110 0100 . ..... ..... ..... 011010 @3rf_w +FCULT 011110 0101 . ..... ..... ..... 011010 @3rf_w +FCLE 011110 0110 . ..... ..... ..... 011010 @3rf_w +FCULE 011110 0111 . ..... ..... ..... 011010 @3rf_w +FSAF 011110 1000 . ..... ..... ..... 011010 @3rf_w +FSUN 011110 1001 . ..... ..... ..... 011010 @3rf_w +FSEQ 011110 1010 . ..... ..... ..... 011010 @3rf_w +FSUEQ 011110 1011 . ..... ..... ..... 011010 @3rf_w +FSLT 011110 1100 . ..... ..... ..... 011010 @3rf_w +FSULT 011110 1101 . ..... ..... ..... 011010 @3rf_w +FSLE 011110 1110 . ..... ..... ..... 011010 @3rf_w +FSULE 011110 1111 . ..... ..... ..... 011010 @3rf_w + +FADD 011110 0000 . ..... ..... ..... 011011 @3rf_w +FSUB 011110 0001 . ..... ..... ..... 011011 @3rf_w +FMUL 011110 0010 . ..... ..... ..... 011011 @3rf_w +FDIV 011110 0011 . ..... ..... ..... 011011 @3rf_w +FMADD 011110 0100 . ..... ..... ..... 011011 @3rf_w +FMSUB 011110 0101 . ..... ..... ..... 011011 @3rf_w +FEXP2 011110 0111 . ..... ..... ..... 011011 @3rf_w +FEXDO 011110 1000 . ..... ..... ..... 011011 @3rf_w +FTQ 011110 1010 . ..... ..... ..... 011011 @3rf_w +FMIN 011110 1100 . ..... ..... ..... 011011 @3rf_w +FMIN_A 011110 1101 . ..... ..... ..... 011011 @3rf_w +FMAX 011110 1110 . ..... ..... ..... 011011 @3rf_w +FMAX_A 011110 1111 . ..... ..... ..... 011011 @3rf_w + +FCOR 011110 0001 . ..... ..... ..... 011100 @3rf_w +FCUNE 011110 0010 . ..... ..... ..... 011100 @3rf_w +FCNE 011110 0011 . ..... ..... ..... 011100 @3rf_w +MUL_Q 011110 0100 . ..... ..... ..... 011100 @3rf_h +MADD_Q 011110 0101 . ..... ..... ..... 011100 @3rf_h +MSUB_Q 011110 0110 . ..... ..... ..... 011100 @3rf_h +FSOR 011110 1001 . ..... ..... ..... 011100 @3rf_w +FSUNE 011110 1010 . ..... ..... ..... 011100 @3rf_w +FSNE 011110 1011 . ..... ..... ..... 011100 @3rf_w +MULR_Q 011110 1100 . ..... ..... ..... 011100 @3rf_h +MADDR_Q 011110 1101 . ..... ..... ..... 011100 @3rf_h +MSUBR_Q 011110 1110 . ..... ..... ..... 011100 @3rf_h + +AND_V 011110 00000 ..... ..... ..... 011110 @vec +OR_V 011110 00001 ..... ..... ..... 011110 @vec +NOR_V 011110 00010 ..... ..... ..... 011110 @vec +XOR_V 011110 00011 ..... ..... ..... 011110 @vec +BMNZ_V 011110 00100 ..... ..... ..... 011110 @vec +BMZ_V 011110 00101 ..... ..... ..... 011110 @vec +BSEL_V 011110 00110 ..... ..... ..... 011110 @vec +FILL 011110 11000000 .. ..... ..... 011110 @2r +PCNT 011110 11000001 .. ..... ..... 011110 @2r +NLOC 011110 11000010 .. ..... ..... 011110 @2r +NLZC 011110 11000011 .. ..... ..... 011110 @2r +FCLASS 011110 110010000 . ..... ..... 011110 @2rf +FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf +FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf +FSQRT 011110 110010011 . ..... ..... 011110 @2rf +FRSQRT 011110 110010100 . ..... ..... 011110 @2rf +FRCP 011110 110010101 . ..... ..... 011110 @2rf +FRINT 011110 110010110 . ..... ..... 011110 @2rf +FLOG2 011110 110010111 . ..... ..... 011110 @2rf +FEXUPL 011110 110011000 . ..... ..... 011110 @2rf +FEXUPR 011110 110011001 . ..... ..... 011110 @2rf +FFQL 011110 110011010 . ..... ..... 011110 @2rf +FFQR 011110 110011011 . ..... ..... 011110 @2rf +FTINT_S 011110 110011100 . ..... ..... 011110 @2rf +FTINT_U 011110 110011101 . ..... ..... 011110 @2rf +FFINT_S 011110 110011110 . ..... ..... 011110 @2rf +FFINT_U 011110 110011111 . ..... ..... 011110 @2rf + +LD 011110 .......... ..... ..... 1000 .. @ldst +ST 011110 .......... ..... ..... 1001 .. @ldst --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) client-ip=209.85.221.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id z135sm3251061wmc.45.2021.11.02.06.45.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:45:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BdKVw9TlNp6lyAe8Rmmb2tz09x4lQMmwRPIlm3JD41A=; b=CK0+iMW32oYymqg2H3E6m+ZBfxpARWhRr2iKvOEZizQ5frHvFF9zc8OgAxxQsVeify kcYMYAWCI8RbrzUr4XCjEMb3Y8TT5FTxu7h72XPHnClRwUcK+GbGfURfYx6Xzc0JTpk3 Y9KO0FGK4hiaz28uc5sfkWrD3dj39qeCEGETxe1el3kuXfapnzd7XD0rS6g7r8dkSBET Y/IXG7aO2cxt7MbnYwNDWpYF8A+82c7aLaMYgGulp8IQy76Y5HD1oaBXmY3S5EkrYKst JRIYvqBTWNq7GuZq29fLBw7csnOAx8VdjXYdc0jClRRllSJyUpNFCY+qOpbF7VHLYWzh /W7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=BdKVw9TlNp6lyAe8Rmmb2tz09x4lQMmwRPIlm3JD41A=; b=CmRIf/FYofZ6W/nQSh7J5csX8cfZMp3svR3/sLUkTV8AFA2V+wMUT5wgscWw/cHCUy A7jeVQXF1g1KkhhHi6lkK/kNcXLB/nWdabI97ofCzJZIAYkwNLy2iaPwyuwrpFhGGQCU yn/PvjUFS1hqyH9/d33CiJ+Sdq/gdgCWsv2jkVduEqBsuIFurfdbwioAQglWA4AFefxg zbldhLfuSS6oO5QXfJHX1ZWiqrstwVcXkVJ1BEozkU3VbuOqK2V/wbHqSCO3UPXJlO3P SRDxKE2bVyvyMTei5tmpQCnFmyKg5Vg+kJY2fF2TUVkPQWdvFT3Byt5XrToewYwiIjbp 2ZjQ== X-Gm-Message-State: AOAM530JFlXelFPwbF8bhmca4cOvECjnd/2t0W+fanx/F1sgn6G45US+ fUgC8RG98sNhXIXOwtZWGlk= X-Google-Smtp-Source: ABdhPJx2Viy0RIkjgWxwB6QSFJE1G+yJgbR6BuZp6JrjihqzMUL8UKyq6uyP7/os+/XxN7jxWy+fFA== X-Received: by 2002:adf:fed0:: with SMTP id q16mr41688272wrs.276.1635860730818; Tue, 02 Nov 2021 06:45:30 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PULL 35/41] target/mips: Fix Loongson-3A4000 MSAIR config register Date: Tue, 2 Nov 2021 14:42:34 +0100 Message-Id: <20211102134240.3036524-36-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860733425100001 When using the Loongson-3A4000 CPU, the MSAIR is returned with a zero value (because unimplemented). Checking on real hardware, this value appears incorrect: $ cat /proc/cpuinfo system type : generic-loongson-machine machine : loongson,generic cpu model : Loongson-3 V0.4 FPU V0.1 model name : Loongson-3A R4 (Loongson-3A4000) @ 1800MHz isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r= 1 mips64r2 ASEs implemented : vz msa loongson-mmi loongson-cam loongson-ext l= oongson-ext2 ... Checking the CFCMSA opcode result with gdb we get 0x60140: Breakpoint 1, 0x00000001200037c4 in main () 1: x/i $pc =3D> 0x1200037c4 : cfcmsa v0,msa_ir (gdb) si 0x00000001200037c8 in main () (gdb) i r v0 v0: 0x60140 MSAIR bits 17 and 18 are "reserved" per the spec revision 1.12, so mask them out, and set MSAIR=3D0x0140 for the Loongson-3A4000 CPU model added in commit af868995e1b. Cc: Huacai Chen Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211026180920.1085516-1-f4bug@amsat.org> --- target/mips/cpu-defs.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index cbc45fcb0e8..ee8b322a564 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -886,6 +886,7 @@ const mips_def_t mips_defs[] =3D (0x1 << FCR0_D) | (0x1 << FCR0_S), .CP1_fcr31 =3D 0, .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, + .MSAIR =3D (0x01 << MSAIR_ProcID) | (0x40 << MSAIR_Rev), .SEGBITS =3D 48, .PABITS =3D 48, .insn_flags =3D CPU_MIPS64R2 | INSN_LOONGSON3A | --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) client-ip=209.85.221.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860737; cv=none; d=zohomail.com; s=zohoarc; b=jwIvZ1q8B9evWl9D6stxRGkD517cX7hcVoFmU4WzQBEfNfrc18zAc1KpJ15LAuJMlfN5gtT6Ak2DSz0k85nrKO3b+ZoMKT9qe82KxYXCqOvueJyraXYNJrkNDIKN0TWQYrM37E8krDI3kFfAMPGy3IX9HuGaV79/XodIEQLJtmQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860737; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vEW9qyLcIIcmU7FBn9bHd1IYCxVAVro4srRgHcoUWnM=; b=J9usx/ND+TLUTLdivMlT9E9eXbVBw+Rt9BMEGLbJQcV8gTidYQxwwEADDoABk5MnE1OE+e6I8imCCw5C17nncMgzPFZf0Vw2TUAZ0+eD9Fmkey4loDhfrfYGctc6Ob70XLAAnRwvJPFRFhH/tC/ftaUO7rxxsnQ7HD2QNDAYIL0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) by mx.zohomail.com with SMTPS id 1635860737201990.6067278421028; Tue, 2 Nov 2021 06:45:37 -0700 (PDT) Received: by mail-wr1-f50.google.com with SMTP id i5so25762531wrb.2 for ; Tue, 02 Nov 2021 06:45:36 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id k21sm2548453wmj.45.2021.11.02.06.45.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:45:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vEW9qyLcIIcmU7FBn9bHd1IYCxVAVro4srRgHcoUWnM=; b=Y6mh/hhEl5X6+OwRBWIeovWQn5DlPYzS8E0aBMS2uW3A5uYmn17Ess44QghLrkSs+o esT/yxYnQA4pgSMhvSmj8nR7UHaseAPJV49jLHL+H4ITsREWtelHDGbxNzcFz/P8dON8 v18WWAbqCOvIgZF0LKEDy5ULjajfjA2/Favt2ba+pYg2XQzsQNe2U/HFFOJ/BipSm/Ni mp4sd+5P4l4opyiXz7KYh1uTbb4ajOikFAI7TpNI2iHIpdTmvUf3pMAUQ9tt+ffIk9FC IuJyEv8P9SrCEI5lldqS4fSZCmfZufpk9WobPL4BM2amxXyU7V3ROqbZesm0JTysvcSb jCMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=vEW9qyLcIIcmU7FBn9bHd1IYCxVAVro4srRgHcoUWnM=; b=TXTJSlX1uw0In6/BGyDe7RRgicWU5rFiQ2yZ8ob5v6gUUdw6th7GyQDE2TU5/KREFy aDw/yQb5eFqvlP6Uhggn35zVo2BaR8/s64r5EeigukM3x6tYJ+yAuvfkYyGabpjbOPvg nwKPH9t4iLxpL/08ZSV1C7qM4jxCiMi8oBHuHHVktKk+4eIjiQkw1f8ugGNpEaYe0rMh zjhO9P8JlARM2g2ncHoh2ehJ8a5sRDD83HocYxKHgXBT0qVJWcFcSNkGOJ8M+ORMVBQk upiEFqIS4CoKMdVgtMJn+IFCw51APHWHs5xpIL4yFvEB6/dUKzjMDWmjt9pvO2kil3Ja AnEg== X-Gm-Message-State: AOAM530/AnxR60xG+20tl5m1IWiGg3iB9AWt8SSD6atO8274UAjos70d XMjbgJu9niSWOaZf9wcGub8= X-Google-Smtp-Source: ABdhPJzPXpgrCy6Ccm/ItK8e6C/L1MVibb2Uk+ilwL19PEvQcxOw5AXy6Yq4vRoF/hYx4KnWZDrtww== X-Received: by 2002:a05:6000:10cb:: with SMTP id b11mr35288742wrx.71.1635860735501; Tue, 02 Nov 2021 06:45:35 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 36/41] target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU Date: Tue, 2 Nov 2021 14:42:35 +0100 Message-Id: <20211102134240.3036524-37-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860738269100001 FCR0_HAS2008 flag has been enabled in commit ba5c79f2622 ("target-mips: indicate presence of IEEE 754-2008 FPU in R6/R5+MSA CPUs"), so remove the obsolete FIXME comment. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Message-Id: <20211028212103.2126176-1-f4bug@amsat.org> --- target/mips/cpu-defs.c.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index ee8b322a564..582f9400702 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -369,7 +369,6 @@ const mips_def_t mips_defs[] =3D * Config3: VZ, CTXTC, CDMM, TL * Config4: MMUExtDef * Config5: MRP - * FIR(FCR0): Has2008 * */ .name =3D "P5600", .CP0_PRid =3D 0x0001A800, --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) client-ip=209.85.128.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860741; cv=none; d=zohomail.com; s=zohoarc; b=Q0DkKd4ymiHrLtXzAzU1MPZgyh3NCos602E+tgVLlIeCJAeXqMjxa12gPzVX1yRvcq8l6QfiswH3ZLFPQqvuTtt9uTNoCOyFI6OJH8hfg4R6vXSqOUoFqTeuHhiGnufzlydByS1rrt/DzhgYapVA42aR2FwAUzt5Uez0a85Dyic= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860741; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Q3s3GZhFWrGY7gjToiSxwFx4tiZft1tygbK630ikQq4=; b=EBXGLqxPSpDf7Meen0podJWmrY6PFou2RZ9cQVzfE9q4o2sK1Vj8lnkqw563beLjbIJ16lBsQZ4RW7REGKv4BuU02NT5cy8THka7kpwuaosih/v36Zyq85VXw/tEl7/pWo7d9OymRIZ7/R3Yl3dn+n+ZszdavH4YTMDsLYJQWIQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) by mx.zohomail.com with SMTPS id 1635860741810393.4401137561496; Tue, 2 Nov 2021 06:45:41 -0700 (PDT) Received: by mail-wm1-f54.google.com with SMTP id f7-20020a1c1f07000000b0032ee11917ceso2158010wmf.0 for ; Tue, 02 Nov 2021 06:45:41 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id n4sm1914383wri.41.2021.11.02.06.45.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:45:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q3s3GZhFWrGY7gjToiSxwFx4tiZft1tygbK630ikQq4=; b=c7Qxh2W/gvJC+ZMbM9AIK5MB27JSopJ7oBjsjfZkFk6diZvgJxApW9r34awjtXzalu 96lFEhEzysywCG6mhgc++D2QeBFrF8+tzQdZrcLtJ63HgrzD297KIu5fil0cfwXqRaZW CTZj0rdMtNYFPU2da273WapIP0MgRTyhpPQMKoeVI8hr+DLkChyFFFxUHXd84PIcY8Pu GjOqJ+ZNRGUdKbg8iskGU0SXJy2idiw6CoFBFl4uBxvh1v23GxaiyOPJJIs6SKIgnlMC iCOqt3n321TT8MYiqxb2/M7eaNRdOjTAEHbKp6j5LdSdIqO0zR7vsDSx4xCe6gQml1Xv 9KjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Q3s3GZhFWrGY7gjToiSxwFx4tiZft1tygbK630ikQq4=; b=PqkTWrXLJFpJ6bKz46LZGrjukYFrE1cHomSM3ujTZrKj+x2jyJkNO2Ep5OP3RLvR6N vqIKFpgn+29ywoXgdAF4Unowe3z15oPjIctj/UphsAMv9fKkPAa01KLTi8Mxs1PGzDMh KEH1YfcBtQkCYCFNuNC3G74CPIVXRlMkbsfNu18SsY6r7UxJ0tLvMauGgQ3mSBGSIVTp biizK1TuYrwcvAcjbvM3v9XOGRZBMkh/fqowEhhp389csyzfupGUW5+zABWyOIRGhjKT 4fbpHzx0Vu37KWldMqte3L2NB8jJEIuLYXvyNtISpcHICoeLiN/z/oLhaA7ZAZ4PJDvc rxvw== X-Gm-Message-State: AOAM533/eKMm8Njo30Qu+9/Pyp9Z9v08EPuuSQeFBORGvgwm1wYWCqNW MlrcD6iUo5oHkbHm1Htxxm0= X-Google-Smtp-Source: ABdhPJxVhrZr5cPgss8IK5GR/TPqyAJTlEqc1/8SCbxMCmgQKEzFEFSTXZ5/QG+ZeLOfw2wjjw7h7A== X-Received: by 2002:a05:600c:35d0:: with SMTP id r16mr6644516wmq.24.1635860740035; Tue, 02 Nov 2021 06:45:40 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 37/41] usb/uhci: Misc clean up Date: Tue, 2 Nov 2021 14:42:36 +0100 Message-Id: <20211102134240.3036524-38-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860743000100001 From: BALATON Zoltan Fix a comment for coding style so subsequent patch will not get checkpatch error and simplify and shorten uhci_update_irq(). Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/usb/hcd-uhci.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c index 0cb02a64321..c557566ec26 100644 --- a/hw/usb/hcd-uhci.c +++ b/hw/usb/hcd-uhci.c @@ -290,7 +290,7 @@ static UHCIAsync *uhci_async_find_td(UHCIState *s, uint= 32_t td_addr) =20 static void uhci_update_irq(UHCIState *s) { - int level; + int level =3D 0; if (((s->status2 & 1) && (s->intr & (1 << 2))) || ((s->status2 & 2) && (s->intr & (1 << 3))) || ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || @@ -298,8 +298,6 @@ static void uhci_update_irq(UHCIState *s) (s->status & UHCI_STS_HSERR) || (s->status & UHCI_STS_HCPERR)) { level =3D 1; - } else { - level =3D 0; } pci_set_irq(&s->dev, level); } @@ -1170,8 +1168,7 @@ void usb_uhci_common_realize(PCIDevice *dev, Error **= errp) =20 pci_conf[PCI_CLASS_PROG] =3D 0x00; /* TODO: reset value should be 0. */ - pci_conf[USB_SBRN] =3D USB_RELEASE_1; // release number - + pci_conf[USB_SBRN] =3D USB_RELEASE_1; /* release number */ pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1); =20 if (s->masterbus) { --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860746; cv=none; d=zohomail.com; s=zohoarc; b=YLIu0P2WWs1stCZIa26ElecPHQNBuED3WEpYf6Y5O8t+DDqgPzSuYUNxOo5yq4Wq4ifqqGpdkNI/hONmAGUFMaPpawTZpC0Ot/ds6kh5FZE6eQBZrvxg1cSpHqcY8QjSZyS5YyblZNl5SYddpUGnJHd5WO8AtQ8TcH2MS8t+w1M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860746; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=S5e6ssV22qr/J5Dlfe80AVdnMPyE0wzeS1Wogbg1ZY0=; b=NwwhPDeyNwYki4EDRF2ofjP6k0bKmki/QKVw3Dgnpeq50HB+HZiBsi/4xMGzruph08aGXdky5ddZqZhNYY9cjwUDZmSzbduvEWRFwK7zinq7yu9hxMNkF2UVKZdExS3tIY0p1A75Ccp8FgLx8s9djNNfEbKBg9rXAishHb7VHhk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by mx.zohomail.com with SMTPS id 1635860746437969.5074559257108; Tue, 2 Nov 2021 06:45:46 -0700 (PDT) Received: by mail-wr1-f48.google.com with SMTP id u18so33428985wrg.5 for ; Tue, 02 Nov 2021 06:45:45 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id z14sm250991wrp.70.2021.11.02.06.45.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:45:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S5e6ssV22qr/J5Dlfe80AVdnMPyE0wzeS1Wogbg1ZY0=; b=bZR1gmgiHlu68wfIa5Ld7MWd6anYAPX9zZMdLQc9OyM9yo3pI8knOBiN9HCQJkYXpr PiwZN4kQqy0LYik9wFKHc4e5AkDZuZxR0/BGeuSmbRP+pYhYQ37YopQ+HJctsEZgstJL VCw1SDrKETDT7A4BLX4f03sOyCSpuQsMJ6bVkju+fFFuOpFvYeXd3zW1P0Eq6WLFdreD aBlFp0npF8xW+MHqHjCYa4Xf6AYJBlnXvNZGU6yRSmCOBiTOsPNgTnz2pp4n/yBEIMJW t8JaS2luy07UYrYXHbCbxC5P4pg/uiVDijwqNTzg2Dnlo2M/QbtXYTjBcnLy///LCBW8 ++pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=S5e6ssV22qr/J5Dlfe80AVdnMPyE0wzeS1Wogbg1ZY0=; b=gYqCvgtoyQY3tJy5RlgezUBI9ZZn31qApxGYlwt8oqj8rMdBR7TbyzmHxRMieNhgk4 DQI5jVT0ynnOBMxWROtqwYnsud+O37eorlGHA5Pd+63VoOSPf56AnYC/8cYsiFP04txZ f8DQMSbLF6TsZn32boiq3tWuyQa1vzqryqoXVLSs8NWlDBEo7AhWVt+ukjhFGak9x0U3 YgmQVTwkKO2q6GaABsPK9+1NkzKd+GQ2jODCWMHUCDhw+hj13o/QhkgK79h6DWkAZnIY XYG0Rc5l4drkf5RTZBQ6kg67E/HttNTiPtLRb8fx0mPmWUWW5I06OYTgktONYb4Cvin6 T4WQ== X-Gm-Message-State: AOAM5307sslZzG/mKfdXsgkoGts8FZEt+bf3/wrKfnOiBXPv2HYNZuTf 2879kCl2bgrA8dNp1cFqvq0= X-Google-Smtp-Source: ABdhPJyoi/yhH5K4aON6loe3Z0jXcGN94EnXsrOLoLpStqRi1/TEPNbtMOsMRN7wO6KaDlOGH6a3GA== X-Received: by 2002:adf:d1c3:: with SMTP id b3mr44847488wrd.273.1635860744693; Tue, 02 Nov 2021 06:45:44 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , BALATON Zoltan , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 38/41] usb/uhci: Disallow user creating a vt82c686-uhci-pci device Date: Tue, 2 Nov 2021 14:42:37 +0100 Message-Id: <20211102134240.3036524-39-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860747546100001 From: BALATON Zoltan Because this device only works as part of VIA superio chips set user creatable to false. Since the class init method is common for UHCI variants introduce a flag in UHCIInfo for this. Signed-off-by: BALATON Zoltan Reviewed-by: Gerd Hoffmann Message-Id: Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/usb/hcd-uhci.h | 1 + hw/usb/hcd-uhci.c | 3 +++ hw/usb/vt82c686-uhci-pci.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/hw/usb/hcd-uhci.h b/hw/usb/hcd-uhci.h index e61d8fcb192..316693f80bd 100644 --- a/hw/usb/hcd-uhci.h +++ b/hw/usb/hcd-uhci.h @@ -85,6 +85,7 @@ typedef struct UHCIInfo { uint8_t irq_pin; void (*realize)(PCIDevice *dev, Error **errp); bool unplug; + bool notuser; /* disallow user_creatable */ } UHCIInfo; =20 void uhci_data_class_init(ObjectClass *klass, void *data); diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c index c557566ec26..7d26e351942 100644 --- a/hw/usb/hcd-uhci.c +++ b/hw/usb/hcd-uhci.c @@ -1282,6 +1282,9 @@ void uhci_data_class_init(ObjectClass *klass, void *d= ata) } else { device_class_set_props(dc, uhci_properties_standalone); } + if (info->notuser) { + dc->user_creatable =3D false; + } u->info =3D *info; } =20 diff --git a/hw/usb/vt82c686-uhci-pci.c b/hw/usb/vt82c686-uhci-pci.c index b109c216033..ea262e6d709 100644 --- a/hw/usb/vt82c686-uhci-pci.c +++ b/hw/usb/vt82c686-uhci-pci.c @@ -25,6 +25,8 @@ static UHCIInfo uhci_info[] =3D { .irq_pin =3D 3, .realize =3D usb_uhci_vt82c686b_realize, .unplug =3D true, + /* Reason: only works as USB function of VT82xx superio chips */ + .notuser =3D true, } }; =20 --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860751; cv=none; d=zohomail.com; s=zohoarc; b=LM+ultEi5yc2nJaymkKM0FySgSutdv2KiSSubFd/rNZcC7nHsdngf5w7t8oE+jWHX53ia9j48QLxF1bztXly3frWNgwF6SCStZ877vVfoOLqTnvtmK5fFveZB2e1umFUEXOe5wwXk2QC/vZ/w07kuCQOZA9QXZxpqEdeBLaYbvg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860751; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CX4TDYxHmqmiiR24yF6hrsJep+v1xIl7VYK9/UVuiFE=; b=Xdtobn4OsAhu1F4ZajrrXct9c2f2zEY9ZZi/WJ5NxmrUTWJovE0AQk93EiP3Fb+B/iYTM5gLBmFRNJYdmyf73i5EAk+M7Wn6vZHjqeoEG9Z8oqHQaWQ69jYviG8pGtMB1xeDG6mzF0cag2UciA/AiHtvk/87GzejY5utZa2Aj3k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by mx.zohomail.com with SMTPS id 1635860751143922.6282933505809; Tue, 2 Nov 2021 06:45:51 -0700 (PDT) Received: by mail-wr1-f49.google.com with SMTP id d24so2827283wra.0 for ; Tue, 02 Nov 2021 06:45:50 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id z15sm6096355wrr.65.2021.11.02.06.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:45:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CX4TDYxHmqmiiR24yF6hrsJep+v1xIl7VYK9/UVuiFE=; b=bArEW0RPuk8NGIaE6nAs8gLpoqiLIBR+HMim0K8JK5R36RKYCkU/zCXKiRPHC/ZykM nkzCx/OkhvhmrAhYE0UNhz0WMiVb2V77Q7w/cBncuq5nRJwxvIERLtQ2E6brWaJtt8oY VoYqNT0vnx2wVWCwLl7k7qh2vxwrUnei10WP3zGaD/F6B4X3JMf1RhJsaA4Exg4BM6nd 1B4AcbpnYoU+mDkxAc33VrPVQ2Wz6Y0RLGQbWPpR946FOXw64OcHroG69T5iRkBIs3ZI n2/OvX47hLHh00lkpMIRQb7OG2KSAOexe/ddBoHvkHBQL0EoRW0ZQV4fzt4LvLVqo1Ww fF1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=CX4TDYxHmqmiiR24yF6hrsJep+v1xIl7VYK9/UVuiFE=; b=BcA63tbt2SVgp27jU0mFX+FLT1gU/6r/+P1d08R4WjXlqo8uknk+/CvGnIFDmuejx3 52HGLy21daY+9OHIGWp+64i6RFqlCXfaS+VQF/Al2lXRSJM5tR0Dz87FHQN5DtnoENBr JIvAA8I7Qk4zlRnmhcV8UnZkkeakHhWYfRXJO2NmQr9wXoOFDDnzJ+vBv+kpstx3BzF5 X6W4ShLPyrGuQcf6XrSksLHnkfM3DfRr6JjxQd8ZkRWtFH2muWfbrWZjptFqACEzZE+z VeYzyOU6xPG9t2WxFeDUV1qKs5HvNV4C8GMADY1B7kVuXE9Q8qj7UTYDP/C0gpuqETYt btHw== X-Gm-Message-State: AOAM530L/msPBcahl3fiOnTbuMgXfl+/5q8WrYogWWDdqSFHnYyIlIpt IiVCJjw9EgtDfve5xp+dIQM= X-Google-Smtp-Source: ABdhPJxA7zw8DqffVCkFUuDn588vE7WSlqWk7ccOuqfII328SfFey975t26Tdr0b6buapBDQmxSEqw== X-Received: by 2002:a5d:59ae:: with SMTP id p14mr9305165wrr.365.1635860749445; Tue, 02 Nov 2021 06:45:49 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , BALATON Zoltan , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 39/41] usb/uhci: Replace pci_set_irq with qemu_set_irq Date: Tue, 2 Nov 2021 14:42:38 +0100 Message-Id: <20211102134240.3036524-40-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860752020100001 From: BALATON Zoltan Instead of using pci_set_irq, store the irq in the device state and use it explicitly so variants having different interrupt handling can use their own. Signed-off-by: BALATON Zoltan Reviewed-by: Gerd Hoffmann Message-Id: Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/usb/hcd-uhci.h | 2 +- hw/usb/hcd-uhci.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/usb/hcd-uhci.h b/hw/usb/hcd-uhci.h index 316693f80bd..c85ab7868ee 100644 --- a/hw/usb/hcd-uhci.h +++ b/hw/usb/hcd-uhci.h @@ -60,7 +60,7 @@ typedef struct UHCIState { uint32_t frame_bandwidth; bool completions_only; UHCIPort ports[NB_PORTS]; - + qemu_irq irq; /* Interrupts that should be raised at the end of the current frame. = */ uint32_t pending_int_mask; =20 diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c index 7d26e351942..d1b5657d722 100644 --- a/hw/usb/hcd-uhci.c +++ b/hw/usb/hcd-uhci.c @@ -31,6 +31,7 @@ #include "hw/usb/uhci-regs.h" #include "migration/vmstate.h" #include "hw/pci/pci.h" +#include "hw/irq.h" #include "hw/qdev-properties.h" #include "qapi/error.h" #include "qemu/timer.h" @@ -299,7 +300,7 @@ static void uhci_update_irq(UHCIState *s) (s->status & UHCI_STS_HCPERR)) { level =3D 1; } - pci_set_irq(&s->dev, level); + qemu_set_irq(s->irq, level); } =20 static void uhci_reset(DeviceState *dev) @@ -1170,6 +1171,7 @@ void usb_uhci_common_realize(PCIDevice *dev, Error **= errp) /* TODO: reset value should be 0. */ pci_conf[USB_SBRN] =3D USB_RELEASE_1; /* release number */ pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1); + s->irq =3D pci_allocate_irq(dev); =20 if (s->masterbus) { USBPort *ports[NB_PORTS]; --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860756; cv=none; d=zohomail.com; s=zohoarc; b=RTD/b42tZQExS46T1mJA3tK/KvCXT7awX2nRHuVEpcCtRYVFhToD2q2oDWIq2eB2GVvgRPKnpbmJeiFoj8Rdx3UDt29UbgZi2zj57hfBcLneI+bsI2qxQWGGvBBh3KjKvOKFIb8/ElCeIXCzjviHlyOdm1AptdYTMMeieVHdtDg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860756; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3GPMsZfnn4ZfssdGOMr+SGtI/4dHR+YaPHIAKWs/umE=; b=SGXzaIL9VS1/V8OSPPUxUjoq7izVzicbPeLNsGTR9aGeHpReLieple2/ehEvajH9+GPn3lRsZk04HHK0/8XEBlLh7jv6EmwY6MzWKNXo8HFCn2kt9UPB6nmHjf9Z0lHvUOBAFFb4rjYe4QkUfXufVgNmY4MXSXMfUeWWAAsp+Y4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by mx.zohomail.com with SMTPS id 1635860756008275.13484438893045; Tue, 2 Nov 2021 06:45:56 -0700 (PDT) Received: by mail-wr1-f42.google.com with SMTP id d3so33375615wrh.8 for ; Tue, 02 Nov 2021 06:45:55 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id p18sm2628776wmq.4.2021.11.02.06.45.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:45:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3GPMsZfnn4ZfssdGOMr+SGtI/4dHR+YaPHIAKWs/umE=; b=LDyxw8yH/CG3bJ5Viu8sk/v7TzrgApxn7X4WhbnbCFPNpK79B3BX8MiH6NiiIhCWv0 9AHUAsCViY9uqS2nW2CIslqKPAbxGE/npYK94mbXzKTsioXxwS0US7/2HLzYkfz747Xt YaPIYKSEiE6pRJHQd9VkPxr3HyNg2qlMoovgZHv1Lg/dbYxL/6G0I9XzHQGoahkKdZ4X x8RvJmdPIgrMYukY6TnLl9DNi3FA4DHvhxAOasoTrOG0QGoP95Zc2TdD6/AfL/1iL/zi 4WdNWkPlW25rlQ2ymKnKw8DWvQyi+LlvPOaTXgyoQrjyc2ufYjQR6W3Je3Qm/SfacQ+G oFJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=3GPMsZfnn4ZfssdGOMr+SGtI/4dHR+YaPHIAKWs/umE=; b=HycswTEUj6co+fmCS4JtX8SzGgXO1O0Y4XA+J2xDNJjJ3gRtyIdTeNf3qVU7hFQhVO owjES5uvlk9gzP17CobP18sorcX8N+RxxcrjEhYbAq7Tb0Wfuex7kjiSZaf7iSZGrApC JzKEPMkXcskDzY/WOdvUekdB4GKuuJI8JDLcZ1OWsOV4wc7BKOSELgQ32oKbCSGv3ojh ecACRHv75+mnTCYvmd9GDwa29zv/6m2J15v8McabpninPKnlvYBKkeqkSzxfFD9tv3Wf Gfr5wUs6ILn3R5Et77029uJZGXz85zM/z+a/isQrYcuGseDWbw5m83ixMU08heAx0IYd dwaA== X-Gm-Message-State: AOAM530W5Xc1WmG2Zr+2qfLX84o/O7e+kTGv5SWm9M6O3L1Qi2h7t3Xp xuHUO0PlduHRokxvMBd6MlnZpNoKOzc= X-Google-Smtp-Source: ABdhPJwEoRphZm/JsjD5xLIu2zrH1++egeiXxJuRGXvFM5CnC4ixGBrK/3RdQd1VaVsdnxSP5mfg8g== X-Received: by 2002:a05:6000:2ca:: with SMTP id o10mr46156758wry.383.1635860754088; Tue, 02 Nov 2021 06:45:54 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , BALATON Zoltan , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 40/41] hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts Date: Tue, 2 Nov 2021 14:42:39 +0100 Message-Id: <20211102134240.3036524-41-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860758612100001 From: BALATON Zoltan This device is part of a superio/ISA bridge chip and IRQs from it are routed to an ISA interrupt set by the Interrupt Line PCI config register. Implement this in a vt82c686-uhci-pci specific irq handler Using via_isa_set_irq(). Signed-off-by: BALATON Zoltan Reviewed-by: Jiaxun Yang Reviewed-by: Gerd Hoffmann Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <8d7ed385e33a847d8ddc669163a68b5ca57f82ce.1635161629.git.balato= n@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/usb/vt82c686-uhci-pci.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/usb/vt82c686-uhci-pci.c b/hw/usb/vt82c686-uhci-pci.c index ea262e6d709..0bf2b72ff08 100644 --- a/hw/usb/vt82c686-uhci-pci.c +++ b/hw/usb/vt82c686-uhci-pci.c @@ -1,6 +1,17 @@ #include "qemu/osdep.h" +#include "hw/irq.h" +#include "hw/isa/vt82c686.h" #include "hcd-uhci.h" =20 +static void uhci_isa_set_irq(void *opaque, int irq_num, int level) +{ + UHCIState *s =3D opaque; + uint8_t irq =3D pci_get_byte(s->dev.config + PCI_INTERRUPT_LINE); + if (irq > 0 && irq < 15) { + via_isa_set_irq(pci_get_function_0(&s->dev), irq, level); + } +} + static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp) { UHCIState *s =3D UHCI(dev); @@ -14,6 +25,8 @@ static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Er= ror **errp) pci_set_long(pci_conf + 0xc0, 0x00002000); =20 usb_uhci_common_realize(dev, errp); + object_unref(s->irq); + s->irq =3D qemu_allocate_irq(uhci_isa_set_irq, s, 0); } =20 static UHCIInfo uhci_info[] =3D { --=20 2.31.1 From nobody Mon Feb 9 16:20:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) client-ip=209.85.221.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1635860760; cv=none; d=zohomail.com; s=zohoarc; b=BqeHA0s6hcWfmYL4bgelJpmSF4o6suGRD1Cl6QCHh2VZLc2c0/SKrqq37qhuBtvpvFnNUmiusVLJ1tGp7vyvjHFT883+qgLrNl5BlWt/MMLOBdNgpqwqzSOa64HJXFNTKc8bbXX66ovD5NrhhaIUaVw83jPVbphPtPW/HdPHmhY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635860760; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UPgr2/raxy90/7F3aXd2gpTt47Yic566Ru6PdSvILyI=; b=Dwy+argIFNMCoxZqarKdSpoGZr6eCtETuGrYgdlzrOor6hg032i3UNGcvjQ32JQLinWlzWtPYXZnXCDwXDCsox9Tg5DRJktrFglzZ8LH1dJkN75YM6QTunh3KSsQaydaFPXXjQ7hD1k5ynbGVh7C2BK/Y49n4o8iJpnbSlCUzBs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) by mx.zohomail.com with SMTPS id 163586076069222.113520529531684; Tue, 2 Nov 2021 06:46:00 -0700 (PDT) Received: by mail-wr1-f52.google.com with SMTP id s13so26263809wrb.3 for ; Tue, 02 Nov 2021 06:46:00 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id n32sm915830wms.42.2021.11.02.06.45.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:45:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UPgr2/raxy90/7F3aXd2gpTt47Yic566Ru6PdSvILyI=; b=cntFLM9MCfKJtCX3xVHrA8VfWxeSiVhFfZPch7sfIS9/qVPinFRQJA2h/u7jWPAMXW VE+YvzLCS/L/KydvYTY07/Kw6QinHNbyC72bZiDJfbzsxqyYmlL0bqHGiDTAu6MPH9xx JGs2isGDlRZj4jwwzbbuqKefzuY2krF+82UfRIyzV9uSayy1Wu3JIiv0E71JRYxOSzHT 8lnDdwo+ldpAj2hZW4HyKYFKbRsfmc+h3f1fMywBTRGhkBLjzYGC7EG4DTprWJm2z8sZ 1azWHaUC+Qi+d3pVFJiGQ8HJGoQJIDmhnHCyCKdFeBAeSYApy7PScdQrGOOpxlUMNesI 6KBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=UPgr2/raxy90/7F3aXd2gpTt47Yic566Ru6PdSvILyI=; b=nXGiXH20jXSyeqmwOPMSq1rRsCqwdPaZR8Utqt+D1w18YxFkNgCJLUnvphJt6CwC7Z 0nOrgMHW4VXAJj+5tkPfDdELwMKx1uYs+zjsMxDdtnNMNDSpz2SxK7HeX/JyCo06P4Mf U4ioU9Y8rtLD8zX4Vz9o2x0PAjZanmslxkblxK3fb6BGzvVzE30bgiXstB+4bSOJYmy6 4O6x7OqX4XAMbW9V61qZg0R2vIX1Lu1LrZYa+cvDljOwtcaqzt3RX2kGJnGpnkdg6hSK D7U/0PcLsWo90j4KAszuEp5TbwqcChK8iB7kYNpgPqJPbQWjF9Rz8f5Obke3sux8EtOx /srg== X-Gm-Message-State: AOAM531TQd3EIruGfb74sbq4yfcMe1lAFgkHanrjL45Xms7cDIhQ6ALS OJ3bBeNE8VBmHfaH/8cHIRI= X-Google-Smtp-Source: ABdhPJyBJyBnU8S/20ugPI9BTfzIE/jr8mYPqPQrEBxaBEjgiCg68I0ImSkLVBcCSTxO5KrxyjOtKg== X-Received: by 2002:adf:f904:: with SMTP id b4mr47730038wrr.403.1635860758855; Tue, 02 Nov 2021 06:45:58 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 41/41] Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too" Date: Tue, 2 Nov 2021 14:42:40 +0100 Message-Id: <20211102134240.3036524-42-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635860762250100001 Per the "P32 Porting Guide" (rev 1.2) [1], chapter 2: p32 ABI Overview ---------------- The Application Binary Interface, or ABI, is the set of rules that all binaries must follow in order to run on a nanoMIPS system. This includes, for example, object file format, instruction set, data layout, subroutine calling convention, and system call numbers. The ABI is one part of the mechanism that maintains binary compatibility across all nanoMIPS platforms. p32 improves on o32 to provide an ABI that is efficient in both code density and performance. p32 is required for the nanoMIPS architecture. So far QEMU only support the MIPS o32 / n32 / n64 ABIs. The p32 ABI is not implemented, therefore we can not run any nanoMIPS binary. Revert commit f72541f3a59 ("elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too"). See also the "ELF ABI Supplement" [2]. [1] http://codescape.mips.com/components/toolchain/nanomips/2019.03-01/docs= /MIPS_nanoMIPS_p32_ABI_Porting_Guide_01_02_DN00184.pdf [2] http://codescape.mips.com/components/toolchain/nanomips/2019.03-01/docs= /MIPS_nanoMIPS_ABI_supplement_01_03_DN00179.pdf Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20211101114800.2692157-1-f4bug@amsat.org> --- linux-user/elfload.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f9b82616920..5da8c02d082 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -925,8 +925,6 @@ static void elf_core_copy_regs(target_elf_gregset_t *re= gs, const CPUPPCState *en #endif #define ELF_ARCH EM_MIPS =20 -#define elf_check_arch(x) ((x) =3D=3D EM_MIPS || (x) =3D=3D EM_NANOMIPS) - #ifdef TARGET_ABI_MIPSN32 #define elf_check_abi(x) ((x) & EF_MIPS_ABI2) #else --=20 2.31.1