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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fVhlPoABQmS8wc89+ovGDAnkicIV2MZx6WAeJyRD9lM=; b=CTrjXnePJF+Rse4Oe5iu/WPsWydGurIrp4qUSUJsm4/Dm5fIuA+DBCgWMVl6g5/RcE ySoEGTJuVyEIBpHNIosgATegdoNOd1CRRuPHu9yBdC3h1DSmBtCi9KBiDk3HjzcYFnLb o/ZdCkhVbjZ2Lol2aTs8YpLZWCyJnePK6zGjHyzyufEmfY63NUmk5mH/1J7F/srbuhai X5XLpjfvrSewphK40H58Qi5n5SBU+es7Q/IB1xoJO1kOA58QkpMYpH5K7QUXXgqezyHA 0rqRbgRbZe+xwWEmOJIwsDqgxvuvYA0TwVgxfI2GP0ixxc1l9qlSiGZFr4bQ+OBDoVN+ BZSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fVhlPoABQmS8wc89+ovGDAnkicIV2MZx6WAeJyRD9lM=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::832; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1635854775137100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/mmu_helper.c | 72 +++++++++++++++++++++++++-------------- 1 file changed, 46 insertions(+), 26 deletions(-) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 2ad47391d0..014601e701 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -502,16 +502,60 @@ static inline int ultrasparc_tag_match(SparcTLBEntry = *tlb, return 0; } =20 +static uint64_t build_sfsr(CPUSPARCState *env, int mmu_idx, int rw) +{ + uint64_t sfsr =3D SFSR_VALID_BIT; + + switch (mmu_idx) { + case MMU_PHYS_IDX: + sfsr |=3D SFSR_CT_NOTRANS; + break; + case MMU_USER_IDX: + case MMU_KERNEL_IDX: + sfsr |=3D SFSR_CT_PRIMARY; + break; + case MMU_USER_SECONDARY_IDX: + case MMU_KERNEL_SECONDARY_IDX: + sfsr |=3D SFSR_CT_SECONDARY; + break; + case MMU_NUCLEUS_IDX: + sfsr |=3D SFSR_CT_NUCLEUS; + break; + default: + g_assert_not_reached(); + } + + if (rw =3D=3D 1) { + sfsr |=3D SFSR_WRITE_BIT; + } else if (rw =3D=3D 4) { + sfsr |=3D SFSR_NF_BIT; + } + + if (env->pstate & PS_PRIV) { + sfsr |=3D SFSR_PR_BIT; + } + + if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */ + sfsr |=3D SFSR_OW_BIT; /* overflow (not read before another fault)= */ + } + + /* FIXME: ASI field in SFSR must be set */ + + return sfsr; +} + static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, int *prot, MemTxAttrs *attrs, target_ulong address, int rw, int mmu= _idx) { CPUState *cs =3D env_cpu(env); unsigned int i; + uint64_t sfsr; uint64_t context; - uint64_t sfsr =3D 0; bool is_user =3D false; =20 + sfsr =3D build_sfsr(env, mmu_idx, rw); + switch (mmu_idx) { case MMU_PHYS_IDX: g_assert_not_reached(); @@ -520,29 +564,18 @@ static int get_physical_address_data(CPUSPARCState *e= nv, hwaddr *physical, /* fallthru */ case MMU_KERNEL_IDX: context =3D env->dmmu.mmu_primary_context & 0x1fff; - sfsr |=3D SFSR_CT_PRIMARY; break; case MMU_USER_SECONDARY_IDX: is_user =3D true; /* fallthru */ case MMU_KERNEL_SECONDARY_IDX: context =3D env->dmmu.mmu_secondary_context & 0x1fff; - sfsr |=3D SFSR_CT_SECONDARY; break; - case MMU_NUCLEUS_IDX: - sfsr |=3D SFSR_CT_NUCLEUS; - /* FALLTHRU */ default: context =3D 0; break; } =20 - if (rw =3D=3D 1) { - sfsr |=3D SFSR_WRITE_BIT; - } else if (rw =3D=3D 4) { - sfsr |=3D SFSR_NF_BIT; - } - for (i =3D 0; i < 64; i++) { /* ctx match, vaddr match, valid? */ if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical= )) { @@ -592,22 +625,9 @@ static int get_physical_address_data(CPUSPARCState *en= v, hwaddr *physical, return 0; } =20 - if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status registe= r */ - sfsr |=3D SFSR_OW_BIT; /* overflow (not read before - another fault) */ - } - - if (env->pstate & PS_PRIV) { - sfsr |=3D SFSR_PR_BIT; - } - - /* FIXME: ASI field in SFSR must be set */ - env->dmmu.sfsr =3D sfsr | SFSR_VALID_BIT; - + env->dmmu.sfsr =3D sfsr; env->dmmu.sfar =3D address; /* Fault address register */ - env->dmmu.tag_access =3D (address & ~0x1fffULL) | context; - return 1; } } --=20 2.25.1