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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lCTWBHg3yAPeLZcM1I7LLlGr7M38G+m6NQblxbcjKCQ=; b=ygL+JwzcnQXrPBY2UEo3CTtFx8eia8lQsuQ3t85CspfP1A6ipne1h+0PZDMI5Np/zH yS/qYabeHL6hoIbqOw4OHcg2gSpOGshe5Hnl+1mezsnADaA6Ae16GV6BYREbXZ7/arr9 npV2GnF6E36jvrQZ6m3u4VSsykOu3pBSxlm6JVUqZMwj74Iqv0/0pOc5ohmhxpmd8uKt 7KZOlVhO3VK95WM0vG0Zvz84waoR1OPENtOC5thWrL9DtqBwxQKkey9WkbVSBuSfqeXM L5WvHcUymNQzkBxi/D548X0AJ+MOwjFHnB200B79mv6ISGqDGnoy1BhSbNc7HV0Fi19/ mY5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lCTWBHg3yAPeLZcM1I7LLlGr7M38G+m6NQblxbcjKCQ=; b=rozDFYVazA+r32ZCJAsYG+hmmfG+ftftKHo5ALfOGLI25wFNDYhy143bd8dgp7khMf i38jj7v+7UtngjJON7CqG491HT2bRj4rbIGw8gxEwLWQs+rEf9JtNJ6frF2iwtR9KLX+ Oh1kSijtYvhdP8XtGQ0Mqh3EamotFJo3qu4bBU6UQ1q0/a8lFDUWDUX3XXHDKPJI/i90 vPBZ7W/qlOlpgCXsjnOV3J0rdd8xhyIxj5Koq0/+Q9XC8OxxXp2J0rIXPZ2ttn9HZUNS U7tVozDh6DkfZHvYVBH/tHPjT7a+iLRWI8IqfPpdGglIK2PzSknezAyvgu/KMLundHUd I6Fg== X-Gm-Message-State: AOAM533ndWkKyFePu6P3OT5/l4oAP8ViZOpyci0vq9MNmeMn7+Od/uIY /KCN6cUbSUumUQoxJ6LE3VLzZwUBD+ePoA== X-Google-Smtp-Source: ABdhPJxLMZwj1Vr86ZyKeCG7BvE3i+NWvgQeoy884GKk+Ue6SofXjid8sG9h1klEbg1TEJwqEyNKMw== X-Received: by 2002:a0c:c702:: with SMTP id w2mr34490446qvi.24.1635851467919; Tue, 02 Nov 2021 04:11:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 44/60] target/alpha: Implement alpha_cpu_record_sigbus Date: Tue, 2 Nov 2021 07:07:24 -0400 Message-Id: <20211102110740.215699-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f30; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1635853413612100001 Record trap_arg{0,1,2} for the linux-user signal frame. Raise SIGBUS directly from cpu_loop_exit_sigbus, which means we can remove the code for EXCP_UNALIGN in cpu_loop. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 8 +++++--- linux-user/alpha/cpu_loop.c | 7 ------- target/alpha/cpu.c | 1 + target/alpha/mem_helper.c | 30 ++++++++++++++++++++++-------- 4 files changed, 28 insertions(+), 18 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index d49cc36d07..afd975c878 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -282,9 +282,6 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags); hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; =20 #define cpu_list alpha_cpu_list =20 @@ -451,10 +448,15 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned = reg, uint64_t val); void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, MMUAccessType access_type, bool maperr, uintptr_t retaddr); +void alpha_cpu_record_sigbus(CPUState *cs, vaddr address, + MMUAccessType access_type, uintptr_t retaddr); #else bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 4cc8e0a55c..4029849d5c 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -54,13 +54,6 @@ void cpu_loop(CPUAlphaState *env) fprintf(stderr, "External interrupt. Exit\n"); exit(EXIT_FAILURE); break; - case EXCP_UNALIGN: - info.si_signo =3D TARGET_SIGBUS; - info.si_errno =3D 0; - info.si_code =3D TARGET_BUS_ADRALN; - info._sifields._sigfault._addr =3D env->trap_arg0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_OPCDEC: do_sigill: info.si_signo =3D TARGET_SIGILL; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 69f32c3078..a8990d401b 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -221,6 +221,7 @@ static const struct TCGCPUOps alpha_tcg_ops =3D { =20 #ifdef CONFIG_USER_ONLY .record_sigsegv =3D alpha_cpu_record_sigsegv, + .record_sigbus =3D alpha_cpu_record_sigbus, #else .tlb_fill =3D alpha_cpu_tlb_fill, .cpu_exec_interrupt =3D alpha_cpu_exec_interrupt, diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 75e72bc337..47283a0612 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -23,18 +23,12 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" =20 -/* Softmmu support */ -#ifndef CONFIG_USER_ONLY -void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +static void do_unaligned_access(CPUAlphaState *env, vaddr addr, uintptr_t = retaddr) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; uint64_t pc; uint32_t insn; =20 - cpu_restore_state(cs, retaddr, true); + cpu_restore_state(env_cpu(env), retaddr, true); =20 pc =3D env->pc; insn =3D cpu_ldl_code(env, pc); @@ -42,6 +36,26 @@ void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr a= ddr, env->trap_arg0 =3D addr; env->trap_arg1 =3D insn >> 26; /* opcode */ env->trap_arg2 =3D (insn >> 21) & 31; /* dest regno */ +} + +#ifdef CONFIG_USER_ONLY +void alpha_cpu_record_sigbus(CPUState *cs, vaddr addr, + MMUAccessType access_type, uintptr_t retaddr) +{ + AlphaCPU *cpu =3D ALPHA_CPU(cs); + CPUAlphaState *env =3D &cpu->env; + + do_unaligned_access(env, addr, retaddr); +} +#else +void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + AlphaCPU *cpu =3D ALPHA_CPU(cs); + CPUAlphaState *env =3D &cpu->env; + + do_unaligned_access(env, addr, retaddr); cs->exception_index =3D EXCP_UNALIGN; env->error_code =3D 0; cpu_loop_exit(cs); --=20 2.25.1