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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.08.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:08:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OFBASZgYo/dnEXgBhwjQsgVMikt4qFVfoC5aZFh8E0o=; b=RspD3Pxth3eGJHiFoziZyuA2hRtEnZ118TfuUQX67JE+8vb4q1k3lnZeWRx5P/7Djg NFUsA4hOC8C1EIdHz10qFWzADBB4GLOTiJkR8H4CHJjoGtEVghBfdo5uivt8XVk5O3IS K+JgjqX6sy3hcuPnxyQJmZT1AiIypGUpwu7QqcUiDijXPwtFksBeFAOHf/tBrwfEkFLC bbjGoXUFhDqnLSsI1HV7p49HIhXvfbaVV2leHeO0NHOrrmmbeKy2qSVORYX3gdmE3GhW WRizh9U7dkJp2hRKeCF/51vbtMPuRko/IgOLTQnJPK0ArIjtB2QNDalquMNq7NqozrVn FLuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OFBASZgYo/dnEXgBhwjQsgVMikt4qFVfoC5aZFh8E0o=; b=NRQWvSlSOjrMdnTa8FFtAgYDbu4aJXHpGJrWxgDWuh2o4jqMScH6mAa3X6tJh7y/Ku QsfHwgFObqYcxA+X1muttrunm/mKoVOoKVgOj73hYzgi+NUrfGYkvfEDwYYbcJJoABTg GlHy8ZizS+bABUQ7B2An1M8Pjp+j7EgfGJjZRUUkTH6gNFIv3txqCV3UFXr1wVxurbhd ZCiWB4p/InKOzc3dPLHcXR1p+eC8VZzIyOQqcWQybnIpOPxtp2V1FHOZ9+XID3wwEOvM AurfS9HFVMHucNtgC/qFjPkYcBoK2EqIRjnBFSZu7P8PuklzrZAEYxgvzKz1cNfefSzw cKuw== X-Gm-Message-State: AOAM532iUs8A6k3KpMM6HrTJRYv6kkjf1k6YW2O61a0ZjvQhNhuN3Bd2 wvkqvzy1gR3qCt1wFIbOV8HsJz2IcwLfeQ== X-Google-Smtp-Source: ABdhPJzVsVPl6kw/DfF0KeHM6fg5quVzhWc1RnqEF0ZCM8CtrZ2WedQsrPsMuYWH2nboVro2avLAeQ== X-Received: by 2002:ac8:5744:: with SMTP id 4mr36840046qtx.289.1635851284563; Tue, 02 Nov 2021 04:08:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 39/60] target/sparc: Make sparc_cpu_tlb_fill sysemu only Date: Tue, 2 Nov 2021 07:07:19 -0400 Message-Id: <20211102110740.215699-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::834; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x834.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1635853063747100001 The fallback code in cpu_loop_exit_sigsegv is sufficient for sparc linux-user. This makes all of the code in mmu_helper.c sysemu only, so remove the ifdefs and move the file to sparc_softmmu_ss. Remove the code from cpu_loop that handled TT_DFAULT and TT_TFAULT. Cc: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- linux-user/sparc/cpu_loop.c | 25 ------------------------- target/sparc/cpu.c | 2 +- target/sparc/mmu_helper.c | 25 ------------------------- target/sparc/meson.build | 2 +- 4 files changed, 2 insertions(+), 52 deletions(-) diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index ad29b4eb6a..0ba65e431c 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -219,17 +219,6 @@ void cpu_loop (CPUSPARCState *env) case TT_WIN_UNF: /* window underflow */ restore_window(env); break; - case TT_TFAULT: - case TT_DFAULT: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->mmuregs[4]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; #else case TT_SPILL: /* window overflow */ save_window(env); @@ -237,20 +226,6 @@ void cpu_loop (CPUSPARCState *env) case TT_FILL: /* window underflow */ restore_window(env); break; - case TT_TFAULT: - case TT_DFAULT: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - if (trapnr =3D=3D TT_DFAULT) - info._sifields._sigfault._addr =3D env->dmmu.mmuregs[4= ]; - else - info._sifields._sigfault._addr =3D cpu_tsptr(env)->tpc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; #ifndef TARGET_ABI32 case 0x16e: flush_windows(env); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 21dd27796d..55268ed2a1 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -865,9 +865,9 @@ static const struct SysemuCPUOps sparc_sysemu_ops =3D { static const struct TCGCPUOps sparc_tcg_ops =3D { .initialize =3D sparc_tcg_init, .synchronize_from_tb =3D sparc_cpu_synchronize_from_tb, - .tlb_fill =3D sparc_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D sparc_cpu_tlb_fill, .cpu_exec_interrupt =3D sparc_cpu_exec_interrupt, .do_interrupt =3D sparc_cpu_do_interrupt, .do_transaction_failed =3D sparc_cpu_do_transaction_failed, diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index a44473a1c7..2ad47391d0 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -25,30 +25,6 @@ =20 /* Sparc MMU emulation */ =20 -#if defined(CONFIG_USER_ONLY) - -bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; - - if (access_type =3D=3D MMU_INST_FETCH) { - cs->exception_index =3D TT_TFAULT; - } else { - cs->exception_index =3D TT_DFAULT; -#ifdef TARGET_SPARC64 - env->dmmu.mmuregs[4] =3D address; -#else - env->mmuregs[4] =3D address; -#endif - } - cpu_loop_exit_restore(cs, retaddr); -} - -#else - #ifndef TARGET_SPARC64 /* * Sparc V8 Reference MMU (SRMMU) @@ -926,4 +902,3 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) } return phys_addr; } -#endif diff --git a/target/sparc/meson.build b/target/sparc/meson.build index a3638b9503..a801802ee2 100644 --- a/target/sparc/meson.build +++ b/target/sparc/meson.build @@ -6,7 +6,6 @@ sparc_ss.add(files( 'gdbstub.c', 'helper.c', 'ldst_helper.c', - 'mmu_helper.c', 'translate.c', 'win_helper.c', )) @@ -16,6 +15,7 @@ sparc_ss.add(when: 'TARGET_SPARC64', if_true: files('int6= 4_helper.c', 'vis_helpe sparc_softmmu_ss =3D ss.source_set() sparc_softmmu_ss.add(files( 'machine.c', + 'mmu_helper.c', 'monitor.c', )) =20 --=20 2.25.1