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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id t5sm6075331qkf.34.2021.11.01.10.27.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Nov 2021 10:27:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aVqSiCZ8VIDZCZNfC7lcfLdqkY20k4N+WRPXdiuKsNc=; b=A+qfkBKj6zishRfu8BOJ07T7mTZpqTd2ChOut5mEyB4VBSTtDSXdkIONUDGfK7ZzSR Q2Bpv7pBncB9HUwrPy/4puqjsXHvWnDm9zPJEXuz4D5Fvr3DMU04wg3dFJnEKLsuf+12 IjQ4/BMEHuMgu0fzx65wzeVkWSTBkgyg48ENh0AiPJe/ZCrJsRrlDxsT71JUeBLtZBRC c68TQUpsO2VCKttk1c6nl6n5vPdWPym0DlefSKdrs7fPfJYkEQgKSLTwPZtHaBIwZCiu qW2+MRcNgTFOz9MLTOvtIvV/vlwrRapx7oeXRssYQwwbu2zDDHk88m1CTYMTkFH+JKc0 fhUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aVqSiCZ8VIDZCZNfC7lcfLdqkY20k4N+WRPXdiuKsNc=; b=Xfwu7YKQF9OI8cpsRJeSs7zPHCuIgDZE0vonrFlD/U+igWWRvxQbvYu3j3vzn5+PaH SE37gJvNmQAGYZjyLSlnGFqkQKF/nFp0mVDDiwBzCG+g1EdiZfa8aUvYwH8ZoDq+PUmQ 4bXxsF8u1FJuqF3YUTAjllRXu87rWYC/cS0ANP+19vegGddpTbdeffHrih8TF/jghike Ij0B1HXJ9k5PfWqJYIBBuQAx7oWiEf8mrun514DHY96CA8oDtwHxJOWe9ZWpG8fRl7pt SP9pTcig6F3rgqVq5UxNUfTU669ai8+WBz3EjDZMQlofIOzBQPRzyUHpbzRt0Ul2NHB3 vFog== X-Gm-Message-State: AOAM531mQ+tS+R/v69+koZ9phaWK4ZfVgnGNIJMPDd6TYoZKi5X4Sxsh 4GUHvlHaNKIJb19lTW/srPT1J3TH+DX0mw== X-Google-Smtp-Source: ABdhPJzJVV3jSr5aFo8P4hu4Fc5YC5L4OUPqWCke27KHKnIcoAM1RzHamfoAujvOv1VFGXvNDBt9Ew== X-Received: by 2002:a05:620a:89e:: with SMTP id b30mr24680349qka.154.1635787660936; Mon, 01 Nov 2021 10:27:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 17/60] linux-user/host/riscv: Improve host_signal_write Date: Mon, 1 Nov 2021 13:26:46 -0400 Message-Id: <20211101172729.23149-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211101172729.23149-1-richard.henderson@linaro.org> References: <20211101172729.23149-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::729; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x729.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1635789155358100003 Content-Type: text/plain; charset="utf-8" Do not read 4 bytes before we determine the size of the insn. Simplify triple switches in favor of checking major opcodes. Include the missing cases of compact fsd and fsdsp. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/host/riscv/host-signal.h | 83 ++++++++++------------------- 1 file changed, 28 insertions(+), 55 deletions(-) diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/ho= st-signal.h index df145b1527..3b168cb58b 100644 --- a/linux-user/host/riscv/host-signal.h +++ b/linux-user/host/riscv/host-signal.h @@ -18,65 +18,38 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc) =20 static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) { - uint32_t insn =3D *(uint32_t *)host_signal_pc(uc); - /* - * Detect store by reading the instruction at the program - * counter. Note: we currently only generate 32-bit - * instructions so we thus only detect 32-bit stores + * Detect store by reading the instruction at the program counter. + * Do not read more than 16 bits, because we have not yet determined + * the size of the instruction. */ - switch (((insn >> 0) & 0b11)) { - case 3: - switch (((insn >> 2) & 0b11111)) { - case 8: - switch (((insn >> 12) & 0b111)) { - case 0: /* sb */ - case 1: /* sh */ - case 2: /* sw */ - case 3: /* sd */ - case 4: /* sq */ - return true; - default: - break; - } - break; - case 9: - switch (((insn >> 12) & 0b111)) { - case 2: /* fsw */ - case 3: /* fsd */ - case 4: /* fsq */ - return true; - default: - break; - } - break; - default: - break; - } + const uint16_t *pinsn =3D (const uint16_t *)host_signal_pc(uc); + uint16_t insn =3D pinsn[0]; + + /* 16-bit instructions */ + switch (insn & 0xe003) { + case 0xa000: /* c.fsd */ + case 0xc000: /* c.sw */ + case 0xe000: /* c.sd (rv64) / c.fsw (rv32) */ + case 0xa002: /* c.fsdsp */ + case 0xc002: /* c.swsp */ + case 0xe002: /* c.sdsp (rv64) / c.fswsp (rv32) */ + return true; } =20 - /* Check for compressed instructions */ - switch (((insn >> 13) & 0b111)) { - case 7: - switch (insn & 0b11) { - case 0: /*c.sd */ - case 2: /* c.sdsp */ - return true; - default: - break; - } - break; - case 6: - switch (insn & 0b11) { - case 0: /* c.sw */ - case 3: /* c.swsp */ - return true; - default: - break; - } - break; - default: - break; + /* 32-bit instructions, major opcodes */ + switch (insn & 0x7f) { + case 0x23: /* store */ + case 0x27: /* store-fp */ + return true; + case 0x2f: /* amo */ + /* + * The AMO function code is in bits 25-31, unread as yet. + * The AMO functions are LR (read), SC (write), and the + * rest are all read-modify-write. + */ + insn =3D pinsn[1]; + return (insn >> 11) !=3D 2; /* LR */ } =20 return false; --=20 2.25.1