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[174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.17.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:17:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b7jpFgMMciMmW9Xl8VdlfSERFh4gLfLYDvd7byDKhQQ=; b=bmggfLRWPCJlTliDYIwBF8AYW0VkvebmqgGIIqytjKXy3KZlUkUvhBwyV3DAeFF3Ux 6zZRRoW/foO7p51WiwKTvH9lv0Gq4w3desbgQDwjyv1BPkX7lPWLQw5exHwH/stxrCOg qVYym6y9m7K1ibCV12ln0gntrzj7gJPyqHd64KeDun8I8icAcMSMBOa0b+9SLTW6A+OW h/p2auyDhFj41cVZTvETvNtaaBGhwZOJY6G7N1zr8igrHRKPRywOyFDh2RxAHpIMLOJP qEfwajpBMsb2y26V6PJsRojOjL8uNB5imsn5l5wFQMu3gihQ8POZAa0QvDyFapx4UT7I uvTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b7jpFgMMciMmW9Xl8VdlfSERFh4gLfLYDvd7byDKhQQ=; b=Hbaa94Dg47HSETowMzBWQPCVNWaLmC4Djah17x8OQ2cFvgTPr9Fwmj0zFvOlta5dCj Xnd+Qo9SfpWyya7Awd8O60kBJuwbBO2m0Z28HECPZh0DNdctk4IMqacGFqKbDuAicGTP lsaJv6ixmkIu2Jb74P+NDO9UWEnsdPH+MHeLeptPnvDNRdmrtsmzASJBUUK2WWOgQjIa 045NI7ifP/GzEvGTw/qxeE0wLhzkvppDXmdOq+tm7j9WrMITcmsdUBr3RLmnKEioUMIs BbH3nzHPDGFGSMskL2axukGXwpVXUF3NMquLRrflI0wcT6yXSQYFyurTgAmHjdKAkj9T hJeg== X-Gm-Message-State: AOAM530VRkk9GZTZMTSeDdVu39ablvJhA1+R9u0aC5D/LueDQkxFVYrj WPLP8v9CLVxEHD4cVXg3LuXQBssOKpWsTw== X-Google-Smtp-Source: ABdhPJzRHoczupkHll1mbPl1t+KPExVH+zlLmGLOXS4YVz6n4UINrdIgpT3r3h82s5mi/TE0O/EBPw== X-Received: by 2002:a05:6a00:148c:b0:47c:1776:3599 with SMTP id v12-20020a056a00148c00b0047c17763599mr18320750pfu.32.1635614227940; Sat, 30 Oct 2021 10:17:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 34/66] target/ppc: Implement ppc_cpu_record_sigsegv Date: Sat, 30 Oct 2021 10:16:03 -0700 Message-Id: <20211030171635.1689530-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616370366100001 Record DAR, DSISR, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. This is exactly what the user-mode ppc_cpu_tlb_fill does, so simply rename it as ppc_cpu_record_sigsegv. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 3 --- target/ppc/internal.h | 9 +++++++++ target/ppc/cpu_init.c | 6 ++++-- target/ppc/user_only_helper.c | 15 +++++++++++---- 4 files changed, 24 insertions(+), 9 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 0472ec9154..e946da5f3a 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1302,9 +1302,6 @@ extern const VMStateDescription vmstate_ppc_cpu; =20 /*************************************************************************= ****/ void ppc_translate_init(void); -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); =20 #if !defined(CONFIG_USER_ONLY) void ppc_store_sdr1(CPUPPCState *env, target_ulong value); diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 55284369f5..339974b7d8 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -283,5 +283,14 @@ static inline void pte_invalidate(target_ulong *pte0) #define PTE_PTEM_MASK 0x7FFFFFBF #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) =20 +#ifdef CONFIG_USER_ONLY +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#endif =20 #endif /* PPC_INTERNAL_H */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 65545ba9ca..1c7a7b4b38 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -9014,9 +9014,11 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D { =20 static const struct TCGCPUOps ppc_tcg_ops =3D { .initialize =3D ppc_translate_init, - .tlb_fill =3D ppc_cpu_tlb_fill, =20 -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D ppc_cpu_record_sigsegv, +#else + .tlb_fill =3D ppc_cpu_tlb_fill, .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .do_interrupt =3D ppc_cpu_do_interrupt, .cpu_exec_enter =3D ppc_cpu_exec_enter, diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index aa3f867596..7ff76f7a06 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -21,16 +21,23 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "internal.h" =20 - -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; int exception, error_code; =20 + /* + * Both DSISR and the "trap number" (exception vector offset, + * looked up from exception_index) are present in the linux-user + * signal frame. + * FIXME: we don't actually populate the trap number properly. + * It would be easiest to fill in an env->trap value now. + */ if (access_type =3D=3D MMU_INST_FETCH) { exception =3D POWERPC_EXCP_ISI; error_code =3D 0x40000000; --=20 2.25.1