From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635615894408943.4742992647829; Sat, 30 Oct 2021 10:44:54 -0700 (PDT) Received: from localhost ([::1]:60082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsPV-0002aA-D5 for importer@patchew.org; Sat, 30 Oct 2021 13:44:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57446) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryK-0001un-Uh for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:49 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:37847) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryB-0008UZ-VA for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:48 -0400 Received: by mail-pj1-x1033.google.com with SMTP id t5-20020a17090a4e4500b001a0a284fcc2so13074203pjl.2 for ; Sat, 30 Oct 2021 10:16:39 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IKLMeO+3mWomlul9GD0bgra/twuVZxh+Vxqn0acqDpE=; b=yv/Hd+pzFAYspSSHurdxOu8V+3E5AKU4yDzRMlBFkTg0vUGtRmieo7H3kkrAEBEM3n HMi08ImSf0J1TDXp1CPitvL+zijMHvQAutB4Y+BCYUUu1HbdRFSh1HB/H3LOqXzvhf4U ibBkkzOpfV/M7wXg2l5jHUyND9Yk6xY4iUMJ2SS4gDOYlT47D6O3WtXtzC4o4Ue/tImn /t2APtK8NgbDuXA67tzW1jIZKSO4CBzL6oTD3SedqWPCreuB5DWJU2Pg2Wi1lDoc5fns N7LcRFh04GjxA/37ADd2ecMtN4sjyfxH32ioFgglV+KB1Cjg6KprbucgeXnCnZZ0IcnS 3ZSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IKLMeO+3mWomlul9GD0bgra/twuVZxh+Vxqn0acqDpE=; b=INQ3yIprm3O/R7v8PKTqBkeKnhR4V7W1r5lwprTJ/U8Kt7eBxIo7JHSrtkPUGuDO8R fNCyeRS9A5CFq6VNISbnu9fxPLFpwukDzlp99pfxE0QLzYmV0f6HIrM/Gaq8Gs9/F+zF RRqv5viN2sQudWZkEW9k+W72HfDaBOCkCocZBcXnv8Eg47jAlqJY1/ZdV3aUrgzMWdpH F4KOFVT3j4uxFPs7WfEc0szFi5CLRkDF0gE5nSQlp/briOcpyCsTqZUrEzP8YwTVwPHu vnBjufz14XME17omgxCcaodw/5x5J2NFYJsz2RifJuj2mAjSjzR7ZuPQ/diZZeP9wG4P P+oA== X-Gm-Message-State: AOAM5326x2vSpMrb6KzYcFaVVN/y3fAN+v5prW+RCO2bQFfLZ3egNG7B Knn83pYHfm7t73SojvOOM1TsM/g3A/i1IQ== X-Google-Smtp-Source: ABdhPJyGAnuear3wlZ+Aiylo5dvQQbvrbEPwqrRGd57TGsgoQ/yJGzrgw11tsnq5QuYIoqIEy9fGcQ== X-Received: by 2002:a17:902:778a:b0:13f:672c:103a with SMTP id o10-20020a170902778a00b0013f672c103amr16420218pll.55.1635614198270; Sat, 30 Oct 2021 10:16:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 01/66] accel/tcg: Split out adjust_signal_pc Date: Sat, 30 Oct 2021 10:15:30 -0700 Message-Id: <20211030171635.1689530-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635615895887100001 Split out a function to adjust the raw signal pc into a value that could be passed to cpu_restore_state. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- v2: Adjust pc in place; return MMUAccessType. --- include/exec/exec-all.h | 10 ++++++++++ accel/tcg/user-exec.c | 41 +++++++++++++++++++++++++---------------- 2 files changed, 35 insertions(+), 16 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 9d5987ba04..e54f8e5d65 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -663,6 +663,16 @@ static inline tb_page_addr_t get_page_addr_code_hostp(= CPUArchState *env, return addr; } =20 +/** + * adjust_signal_pc: + * @pc: raw pc from the host signal ucontext_t. + * @is_write: host memory operation was write, or read-modify-write. + * + * Alter @pc as required for unwinding. Return the type of the + * guest memory access -- host reads may be for guest execution. + */ +MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); + /** * cpu_signal_handler * @signum: host signal number diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e6bb29b42d..c02d509ec6 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -57,18 +57,11 @@ static void QEMU_NORETURN cpu_exit_tb_from_sighandler(C= PUState *cpu, cpu_loop_exit_noexc(cpu); } =20 -/* 'pc' is the host PC at which the exception was raised. 'address' is - the effective address of the memory exception. 'is_write' is 1 if a - write caused the exception and otherwise 0'. 'old_set' is the - signal set which should be restored */ -static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, - int is_write, sigset_t *old_set) +/* + * Adjust the pc to pass to cpu_restore_state; return the memop type. + */ +MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write) { - CPUState *cpu =3D current_cpu; - CPUClass *cc; - unsigned long address =3D (unsigned long)info->si_addr; - MMUAccessType access_type =3D is_write ? MMU_DATA_STORE : MMU_DATA_LOA= D; - switch (helper_retaddr) { default: /* @@ -77,7 +70,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo= _t *info, * pointer into the generated code that will unwind to the * correct guest pc. */ - pc =3D helper_retaddr; + *pc =3D helper_retaddr; break; =20 case 0: @@ -97,7 +90,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo= _t *info, * Therefore, adjust to compensate for what will be done later * by cpu_restore_state_from_tb. */ - pc +=3D GETPC_ADJ; + *pc +=3D GETPC_ADJ; break; =20 case 1: @@ -113,12 +106,28 @@ static inline int handle_cpu_signal(uintptr_t pc, sig= info_t *info, * * Like tb_gen_code, release the memory lock before cpu_loop_exit. */ - pc =3D 0; - access_type =3D MMU_INST_FETCH; mmap_unlock(); - break; + *pc =3D 0; + return MMU_INST_FETCH; } =20 + return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; +} + +/* + * 'pc' is the host PC at which the exception was raised. + * 'address' is the effective address of the memory exception. + * 'is_write' is 1 if a write caused the exception and otherwise 0. + * 'old_set' is the signal set which should be restored. + */ +static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, + int is_write, sigset_t *old_set) +{ + CPUState *cpu =3D current_cpu; + CPUClass *cc; + unsigned long address =3D (unsigned long)info->si_addr; + MMUAccessType access_type =3D adjust_signal_pc(&pc, is_write); + /* For synchronous signals we expect to be coming from the vCPU * thread (so current_cpu should be valid) and either from running * code or during translation which can fault as we cross pages. --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635614868267849.3277890927508; Sat, 30 Oct 2021 10:27:48 -0700 (PDT) Received: from localhost ([::1]:56332 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgs8x-0005hO-7t for importer@patchew.org; Sat, 30 Oct 2021 13:27:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57370) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryH-0001sh-Ob for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:45 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:35779) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryE-0008V1-27 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:45 -0400 Received: by mail-pj1-x1032.google.com with SMTP id n11-20020a17090a2bcb00b001a1e7a0a6a6so13109531pje.0 for ; Sat, 30 Oct 2021 10:16:40 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xXlHj7GOOQFwxbMfswRsUIWuGeJ1kP2ehgRt9eaYqEQ=; b=s0S/jWRu8Pj5oWxf7M0nEyC716sKfzTEa0Sr9mUwr2ga0dI74xTwqSGOGzXlrtrp/j BPyW3fTkyXDD7n1W/cidvNWmmVQwtj4DOpgVfjV9CHmrLBsR6YZ8NOmE5YB2pQxUjzYq 3NAB/2ElwpkuWN6QsWua8Bf59dwQ0eOlDXZvX7ys8mf6Er/TPpV2Cci99GUq0vfZVNNx jL6uNTlkm3/KMQM4sUHniTwXLIYv9LgoZmHCGxghgdJBjpVlGDYvgfLOP/8NBCx9u3DB tIkWoAZn9afHGwgR5C8nvx5OE/XGTSWgtFSV6rkiYFZvTYsEyiYba23rLDy95H8DaTK4 vx1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xXlHj7GOOQFwxbMfswRsUIWuGeJ1kP2ehgRt9eaYqEQ=; b=HaWVOaT+0DfYCUeI8h0eU7YuYUwBuqcPinyOV7V20lg0i9ZsECLkQiW1pbI2lN3GmL jE2wapn5lVG0DNv6fQrc+kIsy/I3JK0Zi+O4VOmpZbGmfGr9LNrFvxvR1g/DqqSuczAF Ht3SFp+/u8WLeKvV9udR8WP88xXcEFIepIZSfwZ/jcL8iBhtaMzaEn0UlgMAtKjXFl32 rvDeCK/os4NoYd+7jrZN4A/0mC+KCq0kEzk/Qc3rKgDSpASjV6vmgWgbbkE95ZxBPvDT fK1AqY6J06gVRPRI48b8w7fAyUgNzw+IP2RgKrrQPj39owTQyK0yUWnly/P2sIjl6Sfb dB8w== X-Gm-Message-State: AOAM53237y9GU4qXmWnH1RdersUFTHAvpK2A1R4dyjt7wL8N5tqgK+j9 Kn6SroJ7lAYBMVfIx3iqjtRnFV2RxY+czA== X-Google-Smtp-Source: ABdhPJxRcpm6ziSRKI5pcxPN7JfOfbR7x3JWMBXebUATuIiW5k53RP+SrOzmQ6jpkYexCt6p2337fQ== X-Received: by 2002:a17:90b:1c02:: with SMTP id oc2mr19358731pjb.52.1635614199066; Sat, 30 Oct 2021 10:16:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 02/66] accel/tcg: Move clear_helper_retaddr to cpu loop Date: Sat, 30 Oct 2021 10:15:31 -0700 Message-Id: <20211030171635.1689530-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635614870459100001 Content-Type: text/plain; charset="utf-8" Currently there are only two places that require we reset this value before exiting to the main loop, but that will change. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 3 ++- accel/tcg/user-exec.c | 2 -- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index c9764c1325..bba4672632 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -462,6 +462,7 @@ void cpu_exec_step_atomic(CPUState *cpu) * memory. */ #ifndef CONFIG_SOFTMMU + clear_helper_retaddr(); tcg_debug_assert(!have_mmap_lock()); #endif if (qemu_mutex_iothread_locked()) { @@ -471,7 +472,6 @@ void cpu_exec_step_atomic(CPUState *cpu) qemu_plugin_disable_mem_helpers(cpu); } =20 - /* * As we start the exclusive region before codegen we must still * be in the region if we longjump out of either the codegen or @@ -916,6 +916,7 @@ int cpu_exec(CPUState *cpu) #endif =20 #ifndef CONFIG_SOFTMMU + clear_helper_retaddr(); tcg_debug_assert(!have_mmap_lock()); #endif if (qemu_mutex_iothread_locked()) { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index c02d509ec6..3f3e793b7b 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -175,7 +175,6 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, * currently executing TB was modified and must be exited * immediately. Clear helper_retaddr for next execution. */ - clear_helper_retaddr(); cpu_exit_tb_from_sighandler(cpu, old_set); /* NORETURN */ =20 @@ -193,7 +192,6 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, * an exception. Undo signal and retaddr state prior to longjmp. */ sigprocmask(SIG_SETMASK, old_set, NULL); - clear_helper_retaddr(); =20 cc =3D CPU_GET_CLASS(cpu); cc->tcg_ops->tlb_fill(cpu, address, 0, access_type, --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163561538855058.23053309989473; Sat, 30 Oct 2021 10:36:28 -0700 (PDT) Received: from localhost ([::1]:48746 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsHL-0002sj-Gi for importer@patchew.org; Sat, 30 Oct 2021 13:36:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57444) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryK-0001um-Tv for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:49 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:38658) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryE-0008Vd-2V for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:47 -0400 Received: by mail-pf1-x42e.google.com with SMTP id l1so5876493pfu.5 for ; Sat, 30 Oct 2021 10:16:40 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=shTlPwSm/VaKjDDgx3jqfEVE3VVxFJ7ui9L4q5qHESI=; b=Coi0d3xthmiE+iv9NzwUwJVGpD5O1Xgy7udpPqCoQWU++9AsC29gZh0wIXOQyWg5J+ w6GW4TslLfVRaY83lmtMwFNOpJ/ruXQJtoF93ovk8gqcBGfioosYUQFpVS42TjNvIXLH 6xhlgMxDavygSPYaMs4LvvxGAugW+c6OJ3VQ6j221uziLWZzbr/1k0Ug3+KvJ01Y312O PBEby/ZT4OpSl3uO3Pd9KdzBzXjhFgJCWEYZmgKg5h8sTKOiOa4gQeqKSywYYExL8Hzo pNuDGTHX6+Zc7sJ/bE6CAYslnh55YLRmOGVLbufikVpHpoohmfqX6BAQA5tJfTgk1NmS Qnfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=shTlPwSm/VaKjDDgx3jqfEVE3VVxFJ7ui9L4q5qHESI=; b=EMpvaXdz1ein4E1Rnj9QP5KyJpZof524mSDxCP+clZDnIs5jS8VSMmiaNl2IbKsoF7 jIX/vAE7Z0/fG45iFe6aD1K5HYi3nI9iuOwDxoKG3KdqTGavnr/nXOr9nZjqrRwvkAQC 6oBex9vy6S6jwSydc9RCi+9s4pTtkhbpmKuO5X4bLH+PzVx8c+3nNqy2mRShlYp9CCLo C1BASDa2uwAVxUt6jIp+biLoIerisIOtn09GoyswvAcLgwbpXyFwKR4UDmShbRPsF6Uy k+wZWNi3h4tFXTy86xc1gry6RfHIIjxPKBP3eAQ36NYl4JR6cCyGifvdgxabMZMxir4I MYOg== X-Gm-Message-State: AOAM532433KvaLluhxMWWUfybhT+5BBbMOC+VH9rC1xKQ51kfvC+2Vnh Lq/yxm+KiBMmZwk0SPPB81kUIqFZltd9Kw== X-Google-Smtp-Source: ABdhPJzPnmBKHC3itavyHOwiIvMnmiNlLew7FuSy0A+JLgWZ4VZqUBsjeKENBO4rwCfNRI8emjtf7Q== X-Received: by 2002:a05:6a00:23d5:b0:47c:236d:65b4 with SMTP id g21-20020a056a0023d500b0047c236d65b4mr18050991pfc.52.1635614199757; Sat, 30 Oct 2021 10:16:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 03/66] accel/tcg: Split out handle_sigsegv_accerr_write Date: Sat, 30 Oct 2021 10:15:32 -0700 Message-Id: <20211030171635.1689530-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635615390526100001 This is the major portion of handle_cpu_signal which is specific to tcg, handling the page protections for the translations. Most of the rest will migrate to linux-user/ shortly. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- v2: Pass guest address to handle_sigsegv_accerr_write. --- include/exec/exec-all.h | 12 +++++ accel/tcg/user-exec.c | 101 ++++++++++++++++++++++++---------------- 2 files changed, 72 insertions(+), 41 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index e54f8e5d65..5f94d799aa 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -673,6 +673,18 @@ static inline tb_page_addr_t get_page_addr_code_hostp(= CPUArchState *env, */ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); =20 +/** + * handle_sigsegv_accerr_write: + * @cpu: the cpu context + * @old_set: the sigset_t from the signal ucontext_t + * @host_pc: the host pc, adjusted for the signal + * @host_addr: the host address of the fault + * + * Return true if the write fault has been handled, and should be re-tried. + */ +bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, + uintptr_t host_pc, abi_ptr guest_addr); + /** * cpu_signal_handler * @signum: host signal number diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 3f3e793b7b..b83f8d12f4 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -114,6 +114,52 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_= write) return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; } =20 +/** + * handle_sigsegv_accerr_write: + * @cpu: the cpu context + * @old_set: the sigset_t from the signal ucontext_t + * @host_pc: the host pc, adjusted for the signal + * @guest_addr: the guest address of the fault + * + * Return true if the write fault has been handled, and should be re-tried. + * + * Note that it is important that we don't call page_unprotect() unless + * this is really a "write to nonwriteable page" fault, because + * page_unprotect() assumes that if it is called for an access to + * a page that's writeable this means we had two threads racing and + * another thread got there first and already made the page writeable; + * so we will retry the access. If we were to call page_unprotect() + * for some other kind of fault that should really be passed to the + * guest, we'd end up in an infinite loop of retrying the faulting access. + */ +bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, + uintptr_t host_pc, abi_ptr guest_addr) +{ + switch (page_unprotect(guest_addr, host_pc)) { + case 0: + /* + * Fault not caused by a page marked unwritable to protect + * cached translations, must be the guest binary's problem. + */ + return false; + case 1: + /* + * Fault caused by protection of cached translation; TBs + * invalidated, so resume execution. + */ + return true; + case 2: + /* + * Fault caused by protection of cached translation, and the + * currently executing TB was modified and must be exited immediat= ely. + */ + cpu_exit_tb_from_sighandler(cpu, old_set); + /* NORETURN */ + default: + g_assert_not_reached(); + } +} + /* * 'pc' is the host PC at which the exception was raised. * 'address' is the effective address of the memory exception. @@ -125,8 +171,9 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, { CPUState *cpu =3D current_cpu; CPUClass *cc; - unsigned long address =3D (unsigned long)info->si_addr; + unsigned long host_addr =3D (unsigned long)info->si_addr; MMUAccessType access_type =3D adjust_signal_pc(&pc, is_write); + abi_ptr guest_addr; =20 /* For synchronous signals we expect to be coming from the vCPU * thread (so current_cpu should be valid) and either from running @@ -143,49 +190,21 @@ static inline int handle_cpu_signal(uintptr_t pc, sig= info_t *info, =20 #if defined(DEBUG_SIGNAL) printf("qemu: SIGSEGV pc=3D0x%08lx address=3D%08lx w=3D%d oldset=3D0x%= 08lx\n", - pc, address, is_write, *(unsigned long *)old_set); + pc, host_addr, is_write, *(unsigned long *)old_set); #endif - /* XXX: locking issue */ - /* Note that it is important that we don't call page_unprotect() unless - * this is really a "write to nonwriteable page" fault, because - * page_unprotect() assumes that if it is called for an access to - * a page that's writeable this means we had two threads racing and - * another thread got there first and already made the page writeable; - * so we will retry the access. If we were to call page_unprotect() - * for some other kind of fault that should really be passed to the - * guest, we'd end up in an infinite loop of retrying the faulting - * access. - */ - if (is_write && info->si_signo =3D=3D SIGSEGV && info->si_code =3D=3D = SEGV_ACCERR && - h2g_valid(address)) { - switch (page_unprotect(h2g(address), pc)) { - case 0: - /* Fault not caused by a page marked unwritable to protect - * cached translations, must be the guest binary's problem. - */ - break; - case 1: - /* Fault caused by protection of cached translation; TBs - * invalidated, so resume execution. Retain helper_retaddr - * for a possible second fault. - */ - return 1; - case 2: - /* Fault caused by protection of cached translation, and the - * currently executing TB was modified and must be exited - * immediately. Clear helper_retaddr for next execution. - */ - cpu_exit_tb_from_sighandler(cpu, old_set); - /* NORETURN */ - - default: - g_assert_not_reached(); - } - } =20 /* Convert forcefully to guest address space, invalid addresses are still valid segv ones */ - address =3D h2g_nocheck(address); + guest_addr =3D h2g_nocheck(host_addr); + + /* XXX: locking issue */ + if (is_write && + info->si_signo =3D=3D SIGSEGV && + info->si_code =3D=3D SEGV_ACCERR && + h2g_valid(host_addr) && + handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) { + return 1; + } =20 /* * There is no way the target can handle this other than raising @@ -194,7 +213,7 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, sigprocmask(SIG_SETMASK, old_set, NULL); =20 cc =3D CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, address, 0, access_type, + cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, MMU_USER_IDX, false, pc); g_assert_not_reached(); } --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635615040420366.07437272688253; Sat, 30 Oct 2021 10:30:40 -0700 (PDT) Received: from localhost ([::1]:36526 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsBj-0002us-C1 for importer@patchew.org; Sat, 30 Oct 2021 13:30:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57450) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryL-0001up-0I for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:49 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:38561) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryF-0008W7-6r for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:47 -0400 Received: by mail-pl1-x62a.google.com with SMTP id i5so8917642pla.5 for ; Sat, 30 Oct 2021 10:16:41 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jNnLCcJOHvXqFRNx4ivHlyFLW3vo/pqpN29drgRbLjE=; b=H0fxuFGpgVWcUx9iQQkKPj7piDpF4Jhp9gytm8HLCStyqB+c7r0iX7adtQgeNGCU9P XcqVxOb9j3nMhEqu/WYUNpW02fGgw3ot0M8nVDu4/hWyd8BxIGIghoQdGpyfYH27aT8S AH1K5XxKa5vVggwVElCOl/AKHsXxomwkieryZQteUMESgNRCB7pP4ubSy4CaiEc+IuP1 W3W7P5fs5A5phx5C0hpKwa4c/z7xrdFRO4Ye3NmQGSyRgixPMAxQKEVU00czOEtkYSF+ kv92AlyMkKSjr/w4P1Wdh0V6tnC+4K4TUC6HcEdpgx7vIi91p4DsVSmo6AQWxUXIWl24 b7vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jNnLCcJOHvXqFRNx4ivHlyFLW3vo/pqpN29drgRbLjE=; b=vQZcCYEULqV1XMujSebug6g0glv2aLgGHkRP2xCabqkzgMqtZBT3FASkJTMzGOr5n7 6JKuc9ResBZEV6FA7e0Iv+pZCYuAdKi2hwF+PlKiG+eWHczCa0wnWQaWzoqL7NDaTwlv RtxVUitsOgSnG+KXZ99gO6FQh09MhqxuMO+foD01KwPEJXoBk8qilQl9xDOMGPe4VppW DiiWJO+Yb39BtZcOW+gPHxnygg4f1ccdc7/+XoOoT0EUo4fg/lrFmbCOr7ogm8tphSiL ZAB/9L9xeguLwK7zOPOldzsnMgU7PKq8MyOHMmGRnC3wBwo53RSfd5Rru910mKNmc/II PDyw== X-Gm-Message-State: AOAM533vOkGj0lEB4dom95/eA6BZA/cZsJ2CygjHFx4rorVT1AsDqKx3 GPmTn2twaDb5WogX+mIerKxgLneARhXsKw== X-Google-Smtp-Source: ABdhPJxNIH4DlJrFvtfu5JlW3UgT0d6JcydDjxh6JVc4DayAZZqjIgMCtPgp1kVDCPGMHzER1PZNMQ== X-Received: by 2002:a17:90b:128d:: with SMTP id fw13mr2413609pjb.50.1635614200832; Sat, 30 Oct 2021 10:16:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 04/66] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Date: Sat, 30 Oct 2021 10:15:33 -0700 Message-Id: <20211030171635.1689530-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635615041205100001 Content-Type: text/plain; charset="utf-8" Remove the comment about siglongjmp. We do use sigsetjmp in the main cpu loop, but we do not save the signal mask as most exits from the cpu loop do not require them. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index b83f8d12f4..b1183aa4b3 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -46,17 +46,6 @@ __thread uintptr_t helper_retaddr; =20 //#define DEBUG_SIGNAL =20 -/* exit the current TB from a signal handler. The host registers are - restored in a state compatible with the CPU emulator - */ -static void QEMU_NORETURN cpu_exit_tb_from_sighandler(CPUState *cpu, - sigset_t *old_set) -{ - /* XXX: use siglongjmp ? */ - sigprocmask(SIG_SETMASK, old_set, NULL); - cpu_loop_exit_noexc(cpu); -} - /* * Adjust the pc to pass to cpu_restore_state; return the memop type. */ @@ -153,7 +142,8 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_= t *old_set, * Fault caused by protection of cached translation, and the * currently executing TB was modified and must be exited immediat= ely. */ - cpu_exit_tb_from_sighandler(cpu, old_set); + sigprocmask(SIG_SETMASK, old_set, NULL); + cpu_loop_exit_noexc(cpu); /* NORETURN */ default: g_assert_not_reached(); --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635616346802497.25869506692413; Sat, 30 Oct 2021 10:52:26 -0700 (PDT) Received: from localhost ([::1]:48820 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsWn-00061n-N9 for importer@patchew.org; Sat, 30 Oct 2021 13:52:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57484) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryL-0001vc-OI for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:50 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:39796) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryF-00005m-7B for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:49 -0400 Received: by mail-pg1-x532.google.com with SMTP id g184so12991458pgc.6 for ; Sat, 30 Oct 2021 10:16:42 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dyOAbtDEe2hsdPtG2fphhVCPp8pp4Epcy5WbMT+mT+o=; b=UMBzhAOKiFhR5sShCZxGxtjwH2dabVRQDzgUja23CUN6uIGKg8G3t+8Z/Vzj44UyjV 98u+h13DGcLF+z7TcpuwRdj0RJaGcmGXKzoRK1Lf3xNntPdImJRKBPJcq70xiYcI3q6/ QZiCn8Z/jqbgE2aMaR2i+JEBca3aE7g7hV2CWW0O9wNDanGpLModoG2heOdR1+h2fjVg l0FFcobXdtX5jyZ2YD3EwNivn5NctgJZ7CQ2w2n5DO8aiqasc0m405NG17jU+vwpQ6h3 PeO5pf1sFqwec3tbBvslPdMOajSavYPYWNSYSsrI0w+Y7Yv6vpaTmPSrSztbf3Vwd9Xo y2JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dyOAbtDEe2hsdPtG2fphhVCPp8pp4Epcy5WbMT+mT+o=; b=XF4MMw7FeiI3NUwrepDk0XXAWJPDEfEU7Y8BczmXPf9o7XZINEd2q2tY5+2Lui8uWq p7vvZ2/FFTZX2EtDMqRs44bHaHBemuWZne2oDjKQkaqBdETb12DIEixAKz+NgQXHmi8c Ztq5al5c3cwBLUZfW3nRiPYSYlL7wGi6nOUmFedGArN7/7LWxDLMju2ADAokpqAOWJY1 zYclaIAXTBqmjNjnJzjbcXWzyH15gr9+zYCJCh50G992pUJrXlEpOohEdMJ2jXFOtsBN 5wyzGZISVz7CCurpkHvOekNs3sc3DhkmqQEqrF2SbIGKzI2CAbeYfrbvc2zxt2RDk0h8 lBcg== X-Gm-Message-State: AOAM533SfrJWi5vnMmYRQ5r8W5GrFmzERkx8bIrxYPOIZoZlruqIHiCI y5Fp1aoYyjLHQhQmCxh/9htSuFpf1fmKhA== X-Google-Smtp-Source: ABdhPJxAegXJJDYQbbJUCLKQ4pQjBHDucyxWBD6bix9O4ASuIZ9gNJn0/1uF/LQNWAhggL6qlFFroQ== X-Received: by 2002:a05:6a00:1ac9:b0:47c:236d:65f1 with SMTP id f9-20020a056a001ac900b0047c236d65f1mr18552662pfv.3.1635614201790; Sat, 30 Oct 2021 10:16:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 05/66] configure: Merge riscv32 and riscv64 host architectures Date: Sat, 30 Oct 2021 10:15:34 -0700 Message-Id: <20211030171635.1689530-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616347583100001 The existing code for safe-syscall.inc.S will compile without change for riscv32 and riscv64. We may also drop the meson.build stanza that merges them for tcg/. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- configure | 8 ++------ meson.build | 4 +--- linux-user/host/{riscv64 =3D> riscv}/hostdep.h | 4 ++-- linux-user/host/riscv32/hostdep.h | 11 ----------- linux-user/host/{riscv64 =3D> riscv}/safe-syscall.inc.S | 0 5 files changed, 5 insertions(+), 22 deletions(-) rename linux-user/host/{riscv64 =3D> riscv}/hostdep.h (94%) delete mode 100644 linux-user/host/riscv32/hostdep.h rename linux-user/host/{riscv64 =3D> riscv}/safe-syscall.inc.S (100%) diff --git a/configure b/configure index 039467c04b..d57ad58342 100755 --- a/configure +++ b/configure @@ -570,11 +570,7 @@ elif check_define __s390__ ; then cpu=3D"s390" fi elif check_define __riscv ; then - if check_define _LP64 ; then - cpu=3D"riscv64" - else - cpu=3D"riscv32" - fi + cpu=3D"riscv" elif check_define __arm__ ; then cpu=3D"arm" elif check_define __aarch64__ ; then @@ -587,7 +583,7 @@ ARCH=3D # Normalise host CPU name and set ARCH. # Note that this case should only have supported host CPUs, not guests. case "$cpu" in - ppc|ppc64|s390x|sparc64|x32|riscv32|riscv64) + ppc|ppc64|s390x|sparc64|x32|riscv) ;; ppc64le) ARCH=3D"ppc64" diff --git a/meson.build b/meson.build index 2c5b53cbe2..90e3e85f20 100644 --- a/meson.build +++ b/meson.build @@ -55,7 +55,7 @@ have_block =3D have_system or have_tools python =3D import('python').find_installation() =20 supported_oses =3D ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', '= sunos', 'linux'] -supported_cpus =3D ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', = 'x86_64', +supported_cpus =3D ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64', 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] =20 cpu =3D host_machine.cpu_family() @@ -351,8 +351,6 @@ if not get_option('tcg').disabled() tcg_arch =3D 'i386' elif config_host['ARCH'] =3D=3D 'ppc64' tcg_arch =3D 'ppc' - elif config_host['ARCH'] in ['riscv32', 'riscv64'] - tcg_arch =3D 'riscv' endif add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' / tc= g_arch, language: ['c', 'cpp', 'objc']) diff --git a/linux-user/host/riscv64/hostdep.h b/linux-user/host/riscv/host= dep.h similarity index 94% rename from linux-user/host/riscv64/hostdep.h rename to linux-user/host/riscv/hostdep.h index 865f0fb9ff..2ba07456ae 100644 --- a/linux-user/host/riscv64/hostdep.h +++ b/linux-user/host/riscv/hostdep.h @@ -5,8 +5,8 @@ * See the COPYING file in the top-level directory. */ =20 -#ifndef RISCV64_HOSTDEP_H -#define RISCV64_HOSTDEP_H +#ifndef RISCV_HOSTDEP_H +#define RISCV_HOSTDEP_H =20 /* We have a safe-syscall.inc.S */ #define HAVE_SAFE_SYSCALL diff --git a/linux-user/host/riscv32/hostdep.h b/linux-user/host/riscv32/ho= stdep.h deleted file mode 100644 index adf9edbf2d..0000000000 --- a/linux-user/host/riscv32/hostdep.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - */ - -#ifndef RISCV32_HOSTDEP_H -#define RISCV32_HOSTDEP_H - -#endif diff --git a/linux-user/host/riscv64/safe-syscall.inc.S b/linux-user/host/r= iscv/safe-syscall.inc.S similarity index 100% rename from linux-user/host/riscv64/safe-syscall.inc.S rename to linux-user/host/riscv/safe-syscall.inc.S --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635615769650662.6319826174966; Sat, 30 Oct 2021 10:42:49 -0700 (PDT) Received: from localhost ([::1]:57166 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsNU-0000Lg-Cw for importer@patchew.org; Sat, 30 Oct 2021 13:42:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57514) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryN-0001wN-Dj for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:51 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:33755) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryH-000062-Gr for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:51 -0400 Received: by mail-pj1-x1033.google.com with SMTP id x1-20020a17090a530100b001a1efa4ebe6so9058025pjh.0 for ; Sat, 30 Oct 2021 10:16:43 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A9mkVrBs8KkxTXk1PYgQKfRHS5p1nm/1r22NtGvkuhs=; b=jJAIlxa9NtETcDg0nognJseQVbKUnHUR+EtritS5mmpggeecsXHrv/jxOTWAbCvs7v Zk7KqH6DURCNybSgHk07AKCANL7neveYz5Q8XtnKQFc4I4r93AlNQjkvAw7x00PjOmEG D4R2P5jXXyO/F+fX490pOYhU1v55ojcjE6Uijdu6X9usmkie+cMhU3lNAS1EC0lSrANS dbsxsyDpwKbaL8lJ22ssK5DvA59hpwSns8XPwdf7Cs1pv9UGx3J6RtxIlkXSg5fG5CgZ bLOBgUZofS1Dqd6GtDta72RJT1xxTrrojhghbOyN0QFYI90Mo+3CTP8iOS6chQme99l3 zVLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A9mkVrBs8KkxTXk1PYgQKfRHS5p1nm/1r22NtGvkuhs=; b=Eu893p7NqcqD4d5u/KSXOYt9K2ZYU1nr7wdjDxRHkGMR41g7bRYEogWoZLyycwMiVi RsAw8r5mDWoPXfsesejDteIWMolqohYulsFM4pB5nZYS2vNaeA9yBusLMHnoqWaGOU5T b9uH+dE36m+z+UPqVrz+F5a4RrwquKKr3pa+96UDGJXgdHr4XPXBQcqEaTP0J4kHYmmH 6OYXotPPBiWWilHyQb0P7WQVuT+QCRN9fHHOg3hd6pv4kcekt6cRU8N5G5/H6QQY51c/ sDnhnsF2Ficq5ds3mEKZrWUQZUv3Gi9hjgAaWo9OLagQLcXtPPON9tvUQQCW8HJfOlYg 7zKQ== X-Gm-Message-State: AOAM530l4Qxh4b0jwOUX9IEGYUwP3KqRI+thtvySBeQR84DBHogb3M2J 8f6jgchGhSUGp2pM/5YZRSuXgxPSpk8+Yg== X-Google-Smtp-Source: ABdhPJw9xK7xEvWdrX5U/H2xBbeUQ+gBhA3RsnM7buHb9YdidJOraBj5Znh6eB6X9Iv8Ms0BirJ9Mw== X-Received: by 2002:a17:90a:f182:: with SMTP id bv2mr1874678pjb.139.1635614203057; Sat, 30 Oct 2021 10:16:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 06/66] linux-user: Reorg handling for SIGSEGV Date: Sat, 30 Oct 2021 10:15:35 -0700 Message-Id: <20211030171635.1689530-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635615771471100001 Add stub host-signal.h for all linux-user hosts. Add new code replacing cpu_signal_handler. Full migration will happen one host at a time. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/host/aarch64/host-signal.h | 1 + linux-user/host/arm/host-signal.h | 1 + linux-user/host/i386/host-signal.h | 1 + linux-user/host/mips/host-signal.h | 1 + linux-user/host/ppc/host-signal.h | 1 + linux-user/host/ppc64/host-signal.h | 1 + linux-user/host/riscv/host-signal.h | 1 + linux-user/host/s390/host-signal.h | 1 + linux-user/host/s390x/host-signal.h | 1 + linux-user/host/sparc/host-signal.h | 1 + linux-user/host/sparc64/host-signal.h | 1 + linux-user/host/x32/host-signal.h | 1 + linux-user/host/x86_64/host-signal.h | 1 + linux-user/signal.c | 109 ++++++++++++++++++++++---- 14 files changed, 106 insertions(+), 16 deletions(-) create mode 100644 linux-user/host/aarch64/host-signal.h create mode 100644 linux-user/host/arm/host-signal.h create mode 100644 linux-user/host/i386/host-signal.h create mode 100644 linux-user/host/mips/host-signal.h create mode 100644 linux-user/host/ppc/host-signal.h create mode 100644 linux-user/host/ppc64/host-signal.h create mode 100644 linux-user/host/riscv/host-signal.h create mode 100644 linux-user/host/s390/host-signal.h create mode 100644 linux-user/host/s390x/host-signal.h create mode 100644 linux-user/host/sparc/host-signal.h create mode 100644 linux-user/host/sparc64/host-signal.h create mode 100644 linux-user/host/x32/host-signal.h create mode 100644 linux-user/host/x86_64/host-signal.h diff --git a/linux-user/host/aarch64/host-signal.h b/linux-user/host/aarch6= 4/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/aarch64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-s= ignal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/arm/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/i386/host-signal.h b/linux-user/host/i386/host= -signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/i386/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host= -signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/mips/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/ppc/host-signal.h b/linux-user/host/ppc/host-s= ignal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/ppc/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/ppc64/host-signal.h b/linux-user/host/ppc64/ho= st-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/ppc64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/ho= st-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/riscv/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/s390/host-signal.h b/linux-user/host/s390/host= -signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/s390/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/s390x/host-signal.h b/linux-user/host/s390x/ho= st-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/s390x/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/sparc/host-signal.h b/linux-user/host/sparc/ho= st-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/sparc/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/sparc64/host-signal.h b/linux-user/host/sparc6= 4/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/sparc64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/x32/host-signal.h b/linux-user/host/x32/host-s= ignal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/x32/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/x86_64/host-signal.h b/linux-user/host/x86_64/= host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/x86_64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/signal.c b/linux-user/signal.c index 14d8fdfde1..6900acb122 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/bitops.h" #include "exec/gdbstub.h" +#include "hw/core/tcg-cpu-ops.h" =20 #include #include @@ -29,6 +30,7 @@ #include "loader.h" #include "trace.h" #include "signal-common.h" +#include "host-signal.h" =20 static struct target_sigaction sigact_table[TARGET_NSIG]; =20 @@ -769,41 +771,116 @@ static inline void rewind_if_in_safe_syscall(void *p= uc) } #endif =20 -static void host_signal_handler(int host_signum, siginfo_t *info, - void *puc) +static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) { CPUArchState *env =3D thread_cpu->env_ptr; CPUState *cpu =3D env_cpu(env); TaskState *ts =3D cpu->opaque; - - int sig; target_siginfo_t tinfo; ucontext_t *uc =3D puc; struct emulated_sigtable *k; + int guest_sig; =20 +#ifdef HOST_SIGNAL_PLACEHOLDER /* the CPU emulator uses some host signals to detect exceptions, we forward to it some signals */ - if ((host_signum =3D=3D SIGSEGV || host_signum =3D=3D SIGBUS) + if ((host_sig =3D=3D SIGSEGV || host_sig =3D=3D SIGBUS) && info->si_code > 0) { - if (cpu_signal_handler(host_signum, info, puc)) + if (cpu_signal_handler(host_sig, info, puc)) { return; + } } +#else + uintptr_t pc =3D 0; + bool sync_sig =3D false; + + /* + * Non-spoofed SIGSEGV and SIGBUS are synchronous, and need special + * handling wrt signal blocking and unwinding. + */ + if ((host_sig =3D=3D SIGSEGV || host_sig =3D=3D SIGBUS) && info->si_co= de > 0) { + MMUAccessType access_type; + uintptr_t host_addr; + abi_ptr guest_addr; + bool is_write; + + host_addr =3D (uintptr_t)info->si_addr; + + /* + * Convert forcefully to guest address space: addresses outside + * reserved_va are still valid to report via SEGV_MAPERR. + */ + guest_addr =3D h2g_nocheck(host_addr); + + pc =3D host_signal_pc(uc); + is_write =3D host_signal_write(info, uc); + access_type =3D adjust_signal_pc(&pc, is_write); + + if (host_sig =3D=3D SIGSEGV) { + const struct TCGCPUOps *tcg_ops; + + if (info->si_code =3D=3D SEGV_ACCERR && h2g_valid(host_addr)) { + /* If this was a write to a TB protected page, restart. */ + if (is_write && + handle_sigsegv_accerr_write(cpu, &uc->uc_sigmask, + pc, guest_addr)) { + return; + } + + /* + * With reserved_va, the whole address space is PROT_NONE, + * which means that we may get ACCERR when we want MAPERR. + */ + if (page_get_flags(guest_addr) & PAGE_VALID) { + /* maperr =3D false; */ + } else { + info->si_code =3D SEGV_MAPERR; + } + } + + sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + + tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; + tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, + MMU_USER_IDX, false, pc); + g_assert_not_reached(); + } else { + sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + } + + sync_sig =3D true; + } +#endif =20 /* get target signal number */ - sig =3D host_to_target_signal(host_signum); - if (sig < 1 || sig > TARGET_NSIG) + guest_sig =3D host_to_target_signal(host_sig); + if (guest_sig < 1 || guest_sig > TARGET_NSIG) { return; - trace_user_host_signal(env, host_signum, sig); + } + trace_user_host_signal(env, host_sig, guest_sig); + + host_to_target_siginfo_noswap(&tinfo, info); + k =3D &ts->sigtab[guest_sig - 1]; + k->info =3D tinfo; + k->pending =3D guest_sig; + ts->signal_pending =3D 1; + +#ifndef HOST_SIGNAL_PLACEHOLDER + /* + * For synchronous signals, unwind the cpu state to the faulting + * insn and then exit back to the main loop so that the signal + * is delivered immediately. + */ + if (sync_sig) { + cpu->exception_index =3D EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, pc); + } +#endif =20 rewind_if_in_safe_syscall(puc); =20 - host_to_target_siginfo_noswap(&tinfo, info); - k =3D &ts->sigtab[sig - 1]; - k->info =3D tinfo; - k->pending =3D sig; - ts->signal_pending =3D 1; - - /* Block host signals until target signal handler entered. We + /* + * Block host signals until target signal handler entered. We * can't block SIGSEGV or SIGBUS while we're executing guest * code in case the guest code provokes one in the window between * now and it getting out to the main loop. Signals will be --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635616481041985.1246511740076; Sat, 30 Oct 2021 10:54:41 -0700 (PDT) Received: from localhost ([::1]:57296 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsYx-0003VW-Qf for importer@patchew.org; Sat, 30 Oct 2021 13:54:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57498) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryM-0001vi-FJ for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:51 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:38776) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryH-00006V-H3 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:50 -0400 Received: by mail-pj1-x102e.google.com with SMTP id x33-20020a17090a6c2400b001a63ef25836so3498688pjj.3 for ; Sat, 30 Oct 2021 10:16:44 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E6n//irve723zxybfqo4L7rJ55SyGC7a9CDIm84ZpuM=; b=OBwy0jHau0hLuTfkfVAvKKM6+9j/eSSEBzYhC6d2twJau2gTEhqeSlsdqj9Zw+BP/o PS/KY3LRPOf8toq4cKN0MauDi1VqU8Zz/1zFZI+7vGMNwwy7B0XJMJAH+mYxlHo/JmrY JO8kIEPLl7SjX4y+5wOSZbxtIyIZKaJMQwHG7FsH/zQpVjNsL+Os43cGLfgzhDeTf1HV pGZlokvbyOOzMhsisJCOoVkE89c9TZxE1tDj0/LjpmJhPi7Y6YpqEEpTfb1OJ2jMSD0i uNglfvOtpKp7Gf4BnwXy04z601z8UbesqbdnruwCYE+F00b693UkFSyfrjMalWJDMZdt yblA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E6n//irve723zxybfqo4L7rJ55SyGC7a9CDIm84ZpuM=; b=0+HuDo/AGCagrar+5AjH0w3iSbPyr+XV9SnzUNqQqDRwxgsIt3hl998l/Q6PJSKZPg +T3ExB1IPjMpz/S0lJdBmaIf8Jfh49vA91yFZR61aj0hl0TuEaUIkDvR3KY2gtC8loMz RqXKu7jkGI61CezF584x9n8mrWoMKMLPIXhIrKYpDB3zKfmKhv0orIeMM0WPjKyG6wSE t49L99POMZoX20In6cifaIkKnHrmMcHJERQF/H/5/j0WGXy2o0A4qcJ8gi74sGu6QOf3 4JY/iX0GA5+V/na6i0C/bNun3SMi4AauE+tTLHWhAHXJ19U3tPUzI+8oAYWoJbZDp7F4 ZQxA== X-Gm-Message-State: AOAM530cRlKIo5LjaqZwdJ8bOkWLqyUSsR2lekFHXVG3/BB7aVde2JWQ wAyMZr4G9sDr69BhPTyDnb64Wn8mP6LS0g== X-Google-Smtp-Source: ABdhPJycVM/HXP+QS5umCq6BTGYhPyGdcGnmc+Kgj/uMHYp6W2CJqPaHFXGsWrsgtr5WFP5Snp0uxQ== X-Received: by 2002:a17:902:848c:b0:13f:e969:3c26 with SMTP id c12-20020a170902848c00b0013fe9693c26mr16453553plo.34.1635614203861; Sat, 30 Oct 2021 10:16:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 07/66] linux-user/host/x86: Populate host_signal.h Date: Sat, 30 Oct 2021 10:15:36 -0700 Message-Id: <20211030171635.1689530-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616482644100001 Content-Type: text/plain; charset="utf-8" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- linux-user/host/i386/host-signal.h | 25 ++++- linux-user/host/x32/host-signal.h | 2 +- linux-user/host/x86_64/host-signal.h | 25 ++++- accel/tcg/user-exec.c | 136 +-------------------------- 4 files changed, 50 insertions(+), 138 deletions(-) diff --git a/linux-user/host/i386/host-signal.h b/linux-user/host/i386/host= -signal.h index f4b4d65031..ccbbee5082 100644 --- a/linux-user/host/i386/host-signal.h +++ b/linux-user/host/i386/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef I386_HOST_SIGNAL_H +#define I386_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_EIP]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_TRAPNO] =3D=3D 0xe + && (uc->uc_mcontext.gregs[REG_ERR] & 0x2); +} + +#endif diff --git a/linux-user/host/x32/host-signal.h b/linux-user/host/x32/host-s= ignal.h index f4b4d65031..26800591d3 100644 --- a/linux-user/host/x32/host-signal.h +++ b/linux-user/host/x32/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../x86_64/host-signal.h" diff --git a/linux-user/host/x86_64/host-signal.h b/linux-user/host/x86_64/= host-signal.h index f4b4d65031..883d2fcf65 100644 --- a/linux-user/host/x86_64/host-signal.h +++ b/linux-user/host/x86_64/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef X86_64_HOST_SIGNAL_H +#define X86_64_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_RIP]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_TRAPNO] =3D=3D 0xe + && (uc->uc_mcontext.gregs[REG_ERR] & 0x2); +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index b1183aa4b3..b121e6c2e9 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -29,19 +29,6 @@ #include "trace/trace-root.h" #include "internal.h" =20 -#undef EAX -#undef ECX -#undef EDX -#undef EBX -#undef ESP -#undef EBP -#undef ESI -#undef EDI -#undef EIP -#ifdef __linux__ -#include -#endif - __thread uintptr_t helper_retaddr; =20 //#define DEBUG_SIGNAL @@ -266,123 +253,7 @@ void *probe_access(CPUArchState *env, target_ulong ad= dr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__i386__) - -#if defined(__NetBSD__) -#include -#include - -#define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__FreeBSD__) || defined(__DragonFly__) -#include -#include - -#define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_e= ip)) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) -#define ERROR_sig(context) ((context)->uc_mcontext.mc_err) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__OpenBSD__) -#include -#define EIP_sig(context) ((context)->sc_eip) -#define TRAP_sig(context) ((context)->sc_trapno) -#define ERROR_sig(context) ((context)->sc_err) -#define MASK_sig(context) ((context)->sc_mask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#else -#define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP 0xe -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; -#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) - ucontext_t *uc =3D puc; -#elif defined(__OpenBSD__) - struct sigcontext *uc =3D puc; -#else - ucontext_t *uc =3D puc; -#endif - unsigned long pc; - int trapno; - -#ifndef REG_EIP -/* for glibc 2.1 */ -#define REG_EIP EIP -#define REG_ERR ERR -#define REG_TRAPNO TRAPNO -#endif - pc =3D EIP_sig(uc); - trapno =3D TRAP_sig(uc); - return handle_cpu_signal(pc, info, - trapno =3D=3D PAGE_FAULT_TRAP ? - (ERROR_sig(uc) >> 1) & 1 : 0, - &MASK_sig(uc)); -} - -#elif defined(__x86_64__) - -#ifdef __NetBSD__ -#include -#define PC_sig(context) _UC_MACHINE_PC(context) -#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__OpenBSD__) -#include -#define PC_sig(context) ((context)->sc_rip) -#define TRAP_sig(context) ((context)->sc_trapno) -#define ERROR_sig(context) ((context)->sc_err) -#define MASK_sig(context) ((context)->sc_mask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__FreeBSD__) || defined(__DragonFly__) -#include -#include - -#define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_ri= p)) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) -#define ERROR_sig(context) ((context)->uc_mcontext.mc_err) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#else -#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP 0xe -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; - unsigned long pc; -#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) - ucontext_t *uc =3D puc; -#elif defined(__OpenBSD__) - struct sigcontext *uc =3D puc; -#else - ucontext_t *uc =3D puc; -#endif - - pc =3D PC_sig(uc); - return handle_cpu_signal(pc, info, - TRAP_sig(uc) =3D=3D PAGE_FAULT_TRAP ? - (ERROR_sig(uc) >> 1) & 1 : 0, - &MASK_sig(uc)); -} - -#elif defined(_ARCH_PPC) +#if defined(_ARCH_PPC) =20 /*********************************************************************** * signal context platform-specific definitions @@ -893,11 +764,6 @@ int cpu_signal_handler(int host_signum, void *pinfo, =20 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } - -#else - -#error host CPU specific signal handler needed - #endif =20 /* The softmmu versions of these helpers are in cputlb.c. */ --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635616226240260.9391243011104; Sat, 30 Oct 2021 10:50:26 -0700 (PDT) Received: from localhost ([::1]:40410 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsUr-0000D8-8n for importer@patchew.org; Sat, 30 Oct 2021 13:50:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57504) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryM-0001vj-KU for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:50 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:44691) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryI-00006e-MI for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:50 -0400 Received: by mail-pf1-x432.google.com with SMTP id a26so12273030pfr.11 for ; Sat, 30 Oct 2021 10:16:45 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qWN//AyY/lFeO+8nhrHfQce9wJbciGA36USPrX71ozE=; b=PnuY2R+6ufrnwIo+2rtBro3sCbCH4iZLFbLXhqn3c8eUC+Lzw/eorJ1yEu9sC5UgsB CKXPuNn+xB7sz8UFuhkWW0xrrR0A2XmX2kxciO0MZcEaDIJvKSFaX6yCNmh7GXNc2D8X 7jaixfWIl+ZJdPUig88gTog9pp3KB9JEEYNEJwIDC25/5pRimfUsnh8EADc3Fr1LQOOd NoUAn0R+KqQ+m4nhNi2jngQ8RAAfYM1ajrHwbL8GRm6sAnTmnbnzhRD0WgJW+8drFy9P qiHmYu9ofdmbuVcivSmG82JeBA5wefC8Ep1EXTBhz+6OJ+nRJj6KuDFr8MAO7qa+0gSU 6lcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qWN//AyY/lFeO+8nhrHfQce9wJbciGA36USPrX71ozE=; b=KPtnlCz6+hEtGr+69xFSnNoyIr25L/HFMKetoiixqYIsPaI0uJKrnlyB6cYdDo0up3 SA1cU52tSaOTwIcEtQuOSbUQ99hvuJXlz6AoIb2IWpANAV06ti7NulhkCANw7JRrP0su uzVWlY99NCRlTjlEhkof/ZuL2qKOo0cfsL35scxCKc1zuPKxuQ3WT3ts5DQSNChq4C4d FPxheN1HvNmAA67CPwHiCa/AmaCMSFTZkZG9KZJ1OON/a6R0lWP8Oc2qrbxt4dR25Z92 8RKEOxTSnp/ht5tcYEW5OSbhcqNZ7N7OfYCfGHyF+16mD4iBi/aeYbXpT64L5LS6wdXf 7cjA== X-Gm-Message-State: AOAM533ag1719WQ1xXECgZMZ7izu9Wl9AB9AJFuH3m8daE8BhpNGs/2a Mr6DVcWQ7Y+TOdfHMvafyZiyYQpypF04Rg== X-Google-Smtp-Source: ABdhPJxRtg62dt2YLEtPCKmhgBS3BkeRLwgZPyxTAPI0t0mhgyZdqa86hztOKCqnNjYhiMiOAkUVig== X-Received: by 2002:a05:6a00:1a01:b0:47b:ae61:9bd1 with SMTP id g1-20020a056a001a0100b0047bae619bd1mr18000820pfv.0.1635614204617; Sat, 30 Oct 2021 10:16:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 08/66] linux-user/host/ppc: Populate host_signal.h Date: Sat, 30 Oct 2021 10:15:37 -0700 Message-Id: <20211030171635.1689530-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616226750100001 Content-Type: text/plain; charset="utf-8" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- linux-user/host/ppc/host-signal.h | 25 ++++++++- linux-user/host/ppc64/host-signal.h | 2 +- accel/tcg/user-exec.c | 79 +---------------------------- 3 files changed, 26 insertions(+), 80 deletions(-) diff --git a/linux-user/host/ppc/host-signal.h b/linux-user/host/ppc/host-s= ignal.h index f4b4d65031..e09756c691 100644 --- a/linux-user/host/ppc/host-signal.h +++ b/linux-user/host/ppc/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef PPC_HOST_SIGNAL_H +#define PPC_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.regs->nip; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.regs->trap !=3D 0x400 + && (uc->uc_mcontext.regs->dsisr & 0x02000000); +} + +#endif diff --git a/linux-user/host/ppc64/host-signal.h b/linux-user/host/ppc64/ho= st-signal.h index f4b4d65031..a353c22a90 100644 --- a/linux-user/host/ppc64/host-signal.h +++ b/linux-user/host/ppc64/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../ppc/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index b121e6c2e9..5a0a65fa46 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -253,84 +253,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(_ARCH_PPC) - -/*********************************************************************** - * signal context platform-specific definitions - * From Wine - */ -#ifdef linux -/* All Registers access - only for local access */ -#define REG_sig(reg_name, context) \ - ((context)->uc_mcontext.regs->reg_name) -/* Gpr Registers access */ -#define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], conte= xt) -/* Program counter */ -#define IAR_sig(context) REG_sig(nip, context) -/* Machine State Register (Supervisor) */ -#define MSR_sig(context) REG_sig(msr, context) -/* Count register */ -#define CTR_sig(context) REG_sig(ctr, context) -/* User's integer exception register */ -#define XER_sig(context) REG_sig(xer, context) -/* Link register */ -#define LR_sig(context) REG_sig(link, context) -/* Condition register */ -#define CR_sig(context) REG_sig(ccr, context) - -/* Float Registers access */ -#define FLOAT_sig(reg_num, context) \ - (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num]) -#define FPSCR_sig(context) \ - (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4))) -/* Exception Registers access */ -#define DAR_sig(context) REG_sig(dar, context) -#define DSISR_sig(context) REG_sig(dsisr, context) -#define TRAP_sig(context) REG_sig(trap, context) -#endif /* linux */ - -#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) -#include -#define IAR_sig(context) ((context)->uc_mcontext.mc_srr0) -#define MSR_sig(context) ((context)->uc_mcontext.mc_srr1) -#define CTR_sig(context) ((context)->uc_mcontext.mc_ctr) -#define XER_sig(context) ((context)->uc_mcontext.mc_xer) -#define LR_sig(context) ((context)->uc_mcontext.mc_lr) -#define CR_sig(context) ((context)->uc_mcontext.mc_cr) -/* Exception Registers access */ -#define DAR_sig(context) ((context)->uc_mcontext.mc_dar) -#define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_exc) -#endif /* __FreeBSD__|| __FreeBSD_kernel__ */ - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; -#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) - ucontext_t *uc =3D puc; -#else - ucontext_t *uc =3D puc; -#endif - unsigned long pc; - int is_write; - - pc =3D IAR_sig(uc); - is_write =3D 0; -#if 0 - /* ppc 4xx case */ - if (DSISR_sig(uc) & 0x00800000) { - is_write =3D 1; - } -#else - if (TRAP_sig(uc) !=3D 0x400 && (DSISR_sig(uc) & 0x02000000)) { - is_write =3D 1; - } -#endif - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__alpha__) +#if defined(__alpha__) =20 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163561656145855.46765583628314; Sat, 30 Oct 2021 10:56:01 -0700 (PDT) Received: from localhost ([::1]:33920 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsaG-0006iu-BP for importer@patchew.org; Sat, 30 Oct 2021 13:56:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57618) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryQ-000260-U1 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:54 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:41788) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryJ-00006t-C0 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:54 -0400 Received: by mail-pg1-x532.google.com with SMTP id n23so2348756pgh.8 for ; Sat, 30 Oct 2021 10:16:46 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tI14VBzrVDI2miPE7O8+ompmGRlpfh5I41U9LPaIFUg=; b=RD7LDgdj1d7DwWEZaHLMOUbRw80sZZsl4jfQ9OT88mlS00ZjjS2y3Vmm7fPk+uiVJP 6WESARsqsYzWF74IivB2zh14eFzdEHo7TBOWr87RVgrRt5b1txA/XTV1/Dwpv2M0pJtd 0x9HB9viqdHyBEz1VSEXYERGPeQ41vgqpVbMjVQ6jQv5qy4bIG6ozMJiZSE1L6YutbI0 ks4fbKJtyugGMLribgbQWv6KkfcdKfDjmgokuoOWRLsTXgz3f06jLZBA+TIEVNWDZhDR qiFB7azLEqUpRvcHKMfmB1eKs80QPAdeem72gxUC6iaGZOobA1ZN/tmQSVsLatDfUqK3 HpJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tI14VBzrVDI2miPE7O8+ompmGRlpfh5I41U9LPaIFUg=; b=Oi46hssX0GngTxOZkxoK3G8KN6vL8JM7X5q14+vRZfvcU31rN5jiQAwd7rG6hBPswF sRmIu8SQqRkvIYfxM42DG+d4G5Gs2XMrp9KhvCxk4yle1/BbiPJ1iXVgOMWMxsRgnf1H DkIMLd/sRj8VapZpGMZXIn821JoBv/+IELtP2Sbw38JTi1n2k+C7ipSh/piNoGxjjoMq MF6+7No7lFz9vC+F2sWe9PKT8kHm1Z7SQRO7+225manHzx+MKy3EDeLzwJ/O+YPnIz// IFqLXOZ/IvJgoMpMg7ZFGWu073sCrU55hKjCFyPX9btALubux91MfiaxwQ5pj16rgyL0 Irtw== X-Gm-Message-State: AOAM530+bvNRrCdycuIY4TWcaNqZ4FbVS6PBRjt0UHEfjBFPCKkcSwia hPkAst9h3heUnQT9N8BwsFIuWQoA48dZCA== X-Google-Smtp-Source: ABdhPJz0wb1zkQEVjW4KIXp61Qy4zckyptCIEf5GBWg4nTysweeMVF7E1NdTrs/9JveDA3rIBs94Dg== X-Received: by 2002:a63:201:: with SMTP id 1mr13628385pgc.22.1635614205640; Sat, 30 Oct 2021 10:16:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 09/66] linux-user/host/alpha: Populate host_signal.h Date: Sat, 30 Oct 2021 10:15:38 -0700 Message-Id: <20211030171635.1689530-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616561820100001 Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- linux-user/host/alpha/host-signal.h | 41 +++++++++++++++++++++++++++++ accel/tcg/user-exec.c | 31 +--------------------- 2 files changed, 42 insertions(+), 30 deletions(-) create mode 100644 linux-user/host/alpha/host-signal.h diff --git a/linux-user/host/alpha/host-signal.h b/linux-user/host/alpha/ho= st-signal.h new file mode 100644 index 0000000000..e27704d832 --- /dev/null +++ b/linux-user/host/alpha/host-signal.h @@ -0,0 +1,41 @@ +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef ALPHA_HOST_SIGNAL_H +#define ALPHA_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.sc_pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t *pc =3D (uint32_t *)host_signal_pc(uc); + uint32_t insn =3D *pc; + + /* XXX: need kernel patch to get write flag faster */ + switch (insn >> 26) { + case 0x0d: /* stw */ + case 0x0e: /* stb */ + case 0x0f: /* stq_u */ + case 0x24: /* stf */ + case 0x25: /* stg */ + case 0x26: /* sts */ + case 0x27: /* stt */ + case 0x2c: /* stl */ + case 0x2d: /* stq */ + case 0x2e: /* stl_c */ + case 0x2f: /* stq_c */ + return true; + } + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 5a0a65fa46..e9b6eb696f 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -253,36 +253,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__alpha__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; - ucontext_t *uc =3D puc; - uint32_t *pc =3D uc->uc_mcontext.sc_pc; - uint32_t insn =3D *pc; - int is_write =3D 0; - - /* XXX: need kernel patch to get write flag faster */ - switch (insn >> 26) { - case 0x0d: /* stw */ - case 0x0e: /* stb */ - case 0x0f: /* stq_u */ - case 0x24: /* stf */ - case 0x25: /* stg */ - case 0x26: /* sts */ - case 0x27: /* stt */ - case 0x2c: /* stl */ - case 0x2d: /* stq */ - case 0x2e: /* stl_c */ - case 0x2f: /* stq_c */ - is_write =3D 1; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#elif defined(__sparc__) +#if defined(__sparc__) =20 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635616105222576.9811560270559; Sat, 30 Oct 2021 10:48:25 -0700 (PDT) Received: from localhost ([::1]:36704 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsSt-00060O-M4 for importer@patchew.org; Sat, 30 Oct 2021 13:48:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57528) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryN-0001xB-LH for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:51 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:42832) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryK-00007E-Ll for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:51 -0400 Received: by mail-pf1-x432.google.com with SMTP id m14so12286299pfc.9 for ; Sat, 30 Oct 2021 10:16:47 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JRfWyXLb4RxsKriS/H5VXElUeDZuAf/HaA29wXvInaU=; b=ogGNEduXUMHDHm7DuuLgv8UXo6KxBLa8rfTsFF0BQxogHuivClzGgpAqCz1/0wNf2/ jhi5Jd9En3eF621J9eJ1BK2gXGswGM3/TEXPraN8tZkyjLy9XbAqAXW+/SKYY3cWwoBd uo4q6E9jdTWM43rvkAW9NSGXToekdUWaA9RiKC7t81czWz8m0ZC9+YXWTRVw/Esbdo1B Dxce9LJNPRfxDGg69YdvZ5FQ9AdJlA6P/QogAMt7Mf23ENwLV4RME2ertQjIGFM8olT5 HH0B8mWt8kNjmVDxVRLSHtqdGL2CfZRyju6dgmCEqAdgofAMX0MQWJw0/f8Pauw33J8y giKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JRfWyXLb4RxsKriS/H5VXElUeDZuAf/HaA29wXvInaU=; b=8J4X/PoJ9lVTVZ9tUldc4ZzeGxSFDLNCjUL1io862Cgs6koxAcesHowQE9CqIdwoRd W/C/vFh2TUdAz6XH+ldV06V3x4WSTcTPaM5cc4BIhzTCB3nOq2MmniEfOUnaWzcMCwfp +OzP9X1j1hQr32p19F5+yODR3TtxBK5IyZuxggzISfrRgZ5VvFtxL9tM7dRniMEAMQqX CCDJRVGVoGF/K6FogPApkrfwHdnyJjHtJwLodaQyYskGWB3pjHgn5DsAyHAJ1xr3BHTv sfVpRjWCimr4V/QpXiP7Sv/TRcSbokFX3yaOI0nOkQAgwFFk5JYZ5ZSTuOwIk7+eJfc8 g+/g== X-Gm-Message-State: AOAM533CKCo34H3i8bDXfrqZRKBugwMGcnhK5ssrgfDbnkLip61TOW71 91ZUwdQie0e02VzirrpqfxvCP9dpqlQ97w== X-Google-Smtp-Source: ABdhPJzESBbWRyhX+RlP4kVUTyjsy0murKNt5pX1DnXfe89vC56KMWH5KFjcT2by7MowZn9QmvEF7g== X-Received: by 2002:a63:af07:: with SMTP id w7mr13761650pge.202.1635614206481; Sat, 30 Oct 2021 10:16:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 10/66] linux-user/host/sparc: Populate host_signal.h Date: Sat, 30 Oct 2021 10:15:39 -0700 Message-Id: <20211030171635.1689530-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616105835100001 Content-Type: text/plain; charset="utf-8" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Drop the Solaris code as completely unused. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- linux-user/host/sparc/host-signal.h | 54 ++++++++++++++++++++++- linux-user/host/sparc64/host-signal.h | 2 +- accel/tcg/user-exec.c | 62 +-------------------------- 3 files changed, 55 insertions(+), 63 deletions(-) diff --git a/linux-user/host/sparc/host-signal.h b/linux-user/host/sparc/ho= st-signal.h index f4b4d65031..232943a1db 100644 --- a/linux-user/host/sparc/host-signal.h +++ b/linux-user/host/sparc/host-signal.h @@ -1 +1,53 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef SPARC_HOST_SIGNAL_H +#define SPARC_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ +#ifdef __arch64__ + return uc->uc_mcontext.mc_gregs[MC_PC]; +#else + return uc->uc_mcontext.gregs[REG_PC]; +#endif +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn =3D *(uint32_t *)host_signal_pc(uc); + + if ((insn >> 30) =3D=3D 3) { + switch ((insn >> 19) & 0x3f) { + case 0x05: /* stb */ + case 0x15: /* stba */ + case 0x06: /* sth */ + case 0x16: /* stha */ + case 0x04: /* st */ + case 0x14: /* sta */ + case 0x07: /* std */ + case 0x17: /* stda */ + case 0x0e: /* stx */ + case 0x1e: /* stxa */ + case 0x24: /* stf */ + case 0x34: /* stfa */ + case 0x27: /* stdf */ + case 0x37: /* stdfa */ + case 0x26: /* stqf */ + case 0x36: /* stqfa */ + case 0x25: /* stfsr */ + case 0x3c: /* casa */ + case 0x3e: /* casxa */ + return true; + } + } + return false; +} + +#endif diff --git a/linux-user/host/sparc64/host-signal.h b/linux-user/host/sparc6= 4/host-signal.h index f4b4d65031..1191fe2d40 100644 --- a/linux-user/host/sparc64/host-signal.h +++ b/linux-user/host/sparc64/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../sparc/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e9b6eb696f..694eff7f04 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -253,67 +253,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__sparc__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; - int is_write; - uint32_t insn; -#if !defined(__arch64__) || defined(CONFIG_SOLARIS) - uint32_t *regs =3D (uint32_t *)(info + 1); - void *sigmask =3D (regs + 20); - /* XXX: is there a standard glibc define ? */ - unsigned long pc =3D regs[1]; -#else -#ifdef __linux__ - struct sigcontext *sc =3D puc; - unsigned long pc =3D sc->sigc_regs.tpc; - void *sigmask =3D (void *)sc->sigc_mask; -#elif defined(__OpenBSD__) - struct sigcontext *uc =3D puc; - unsigned long pc =3D uc->sc_pc; - void *sigmask =3D (void *)(long)uc->sc_mask; -#elif defined(__NetBSD__) - ucontext_t *uc =3D puc; - unsigned long pc =3D _UC_MACHINE_PC(uc); - void *sigmask =3D (void *)&uc->uc_sigmask; -#endif -#endif - - /* XXX: need kernel patch to get write flag faster */ - is_write =3D 0; - insn =3D *(uint32_t *)pc; - if ((insn >> 30) =3D=3D 3) { - switch ((insn >> 19) & 0x3f) { - case 0x05: /* stb */ - case 0x15: /* stba */ - case 0x06: /* sth */ - case 0x16: /* stha */ - case 0x04: /* st */ - case 0x14: /* sta */ - case 0x07: /* std */ - case 0x17: /* stda */ - case 0x0e: /* stx */ - case 0x1e: /* stxa */ - case 0x24: /* stf */ - case 0x34: /* stfa */ - case 0x27: /* stdf */ - case 0x37: /* stdfa */ - case 0x26: /* stqf */ - case 0x36: /* stqfa */ - case 0x25: /* stfsr */ - case 0x3c: /* casa */ - case 0x3e: /* casxa */ - is_write =3D 1; - break; - } - } - return handle_cpu_signal(pc, info, is_write, sigmask); -} - -#elif defined(__arm__) +#if defined(__arm__) =20 #if defined(__NetBSD__) #include --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635616290396145.92121391593435; Sat, 30 Oct 2021 10:51:30 -0700 (PDT) Received: from localhost ([::1]:44996 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsVs-0003KE-Cm for importer@patchew.org; Sat, 30 Oct 2021 13:51:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57572) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryO-00020S-P7 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:52 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:41792) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryK-00007T-ME for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:52 -0400 Received: by mail-pg1-x536.google.com with SMTP id n23so2348787pgh.8 for ; Sat, 30 Oct 2021 10:16:48 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M+c0oxO/KqkWahATCsn/ry8zft6rVGU+nYtnuTkgrVg=; b=EC7dLdOfmVdUrgDhCF7NCut2nPF9drNieXhjzbdmwjJtMSUhyHk6wBgilcaRgLz26k Sqnl4BHPnCjXc6wxraxYeC6FO1VcCXbHs9/O3z1z5l9fZSOI/q1+3ZdI8kUyEzFiUMW1 cqj9eq4wU3m3EOYMc8pdQRKPFSbcpzDQxZr7bhNLMFUG5r/QVkp13yrinF46aP7EkUVu tgMiGejv7oAD5216lse38mQfVGptBhF5dBla0EVaRUXJVxeZPSpSEjRrTbRcLiaKBLjU bEQFFZ7FOqj1fr9Sw9XQrrjvy2LUee2A1C/4AqZPD7pPUCBpGnPs64keX1KraMFKfr1h GTUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M+c0oxO/KqkWahATCsn/ry8zft6rVGU+nYtnuTkgrVg=; b=UaiOYfZNLZLeoNPgTCMw8reRj5ZoH+EPsGuZ/V+oofwNFzHLL/1hIrYXDLmoMD1dBS bfDNoCauvg64GJTi/+tv1snLQ33gy4ilz53kdz+VKONtci/gWKpD3QTmTiegnsBwa0yM SQa9N0mv53JWYqq59txygJGDptTNZtOH8unQoZ0gwcF3SuVMYef7bWy9ONb85oKw84hb hqGJrI7SXBeMpXfyXEusyT82mZsS7ylQkYC250F3V+zzQ+QzLqBzOnWqulnc5pm2gotU j24p2qI4Ia7zAFvRcxE8QWI1aikyJXRhR2CKeUiQ5Vnl4J94+4AOUkv7uLe5QsGULZXW WYnA== X-Gm-Message-State: AOAM531hXQS3Yf95JjKnYECL1/dW5ADa9gmCpmr4Uc9ltlZHUbsjiHZj oIC3Vq76+RzouoS1kD7yLAvh/qYrWm8hlQ== X-Google-Smtp-Source: ABdhPJwJVQVE83PLrjWmfdNxq8BdKRXH+VsC3XT2JDGlaL7k3/Ta+D+BtG3gBgPYE7kI0PBgZ2Ne0g== X-Received: by 2002:a65:4942:: with SMTP id q2mr10938836pgs.405.1635614207305; Sat, 30 Oct 2021 10:16:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 11/66] linux-user/host/arm: Populate host_signal.h Date: Sat, 30 Oct 2021 10:15:40 -0700 Message-Id: <20211030171635.1689530-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616291155100001 Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- linux-user/host/arm/host-signal.h | 30 ++++++++++++++++++++- accel/tcg/user-exec.c | 45 +------------------------------ 2 files changed, 30 insertions(+), 45 deletions(-) diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-s= ignal.h index f4b4d65031..6932224c1c 100644 --- a/linux-user/host/arm/host-signal.h +++ b/linux-user/host/arm/host-signal.h @@ -1 +1,29 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef ARM_HOST_SIGNAL_H +#define ARM_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.arm_pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + /* + * In the FSR, bit 11 is WnR, assuming a v6 or + * later processor. On v5 we will always report + * this as a read, which will fail later. + */ + uint32_t fsr =3D uc->uc_mcontext.error_code; + return extract32(fsr, 11, 1); +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 694eff7f04..fabc8855a9 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -253,50 +253,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__arm__) - -#if defined(__NetBSD__) -#include -#include -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; -#if defined(__NetBSD__) - ucontext_t *uc =3D puc; - siginfo_t *si =3D pinfo; -#else - ucontext_t *uc =3D puc; -#endif - unsigned long pc; - uint32_t fsr; - int is_write; - -#if defined(__NetBSD__) - pc =3D uc->uc_mcontext.__gregs[_REG_R15]; -#elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ =3D=3D 2 && __GLI= BC_MINOR__ <=3D 3)) - pc =3D uc->uc_mcontext.gregs[R15]; -#else - pc =3D uc->uc_mcontext.arm_pc; -#endif - -#ifdef __NetBSD__ - fsr =3D si->si_trap; -#else - fsr =3D uc->uc_mcontext.error_code; -#endif - /* - * In the FSR, bit 11 is WnR, assuming a v6 or - * later processor. On v5 we will always report - * this as a read, which will fail later. - */ - is_write =3D extract32(fsr, 11, 1); - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__aarch64__) +#if defined(__aarch64__) =20 #if defined(__NetBSD__) =20 --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635616622479814.7470257880901; Sat, 30 Oct 2021 10:57:02 -0700 (PDT) Received: from localhost ([::1]:37940 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsbB-00011u-9O for importer@patchew.org; Sat, 30 Oct 2021 13:57:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57582) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryP-00023D-Er for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:53 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:43944) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryL-00007Z-E8 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:53 -0400 Received: by mail-pg1-x534.google.com with SMTP id b4so5941439pgh.10 for ; Sat, 30 Oct 2021 10:16:49 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WZfPkApX7GQIdrTB2+yDQhiedYg/15bSgoP00suGbdM=; b=lVNj91QBt9fbwdXWtMhFehMspm3tlAOws5IIR8kwc5yjEoVCwkhhOs24euZEL5YJ21 1Qm6FlLI9Z47rVhryOOuOo3Zn5h9XTNo9owc97lsbocRwiyfrh/67sTiavfwYU/cOWBg qptynpSz/hdNucy5ROoyC/tX06BnojCn5lXxnpamf9UvaKtj+UTM3O/rnXaph15vB5iK 9tRUlimYuVtZK63cwnFmjh7chvNHYkSp/NBxhS6nzHj6XXo/l9OkebkPeEPB5FMLwYYl Jrr55J1PVhRoyiZb2cv/JPJI5uVANLp+EJCjvCmUMu+Pq7lc9r7bIQOyJ0GF06s7/RgF FCGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WZfPkApX7GQIdrTB2+yDQhiedYg/15bSgoP00suGbdM=; b=cOsiWHoo+mxODEtRzorc2fDVuJVqxFZBmMfexgfG45DU+HZDxe+jvM5lgyT58IHHrC HMq8JvpvXwmHHdO4KWJs2Qx0KQFu/oImXi5KXNgeD+9hjMwTmtySd09pT/52OVu+29mf ILm9FExPlRRWznKxBzh1aImePNMFTQB3OOJi/108u8aLDBzMaTJK2UWlYM3VgPIEhY7N UWth1WyTChUrEi0eyxugSKTleiu0qptttih1pNrmu39I1yK2uKxeED5QAmnNnisuEX4j 7DL5LLKPCIeU0Ib+OdQfkiBuh4BEtpU0/5cqOMVSDDbBEQxbAG/nkbmr+FnLfgCxDvEP r/Gg== X-Gm-Message-State: AOAM531/4tPmvcYBLDbUdsrWzNJj0JouUWDZCNKd1uW0vmqBz9v4EEa2 JUFu27zH6MRthA3BL1QbyH8lNT60eUvIhg== X-Google-Smtp-Source: ABdhPJzE5HHyO5OTokrcqMgXQ16NT685oEexN441VpbIWNt8hiczpBmSPnWzd/xLkRDy5FrUi8pKNg== X-Received: by 2002:a63:374b:: with SMTP id g11mr13326104pgn.459.1635614208110; Sat, 30 Oct 2021 10:16:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 12/66] linux-user/host/aarch64: Populate host_signal.h Date: Sat, 30 Oct 2021 10:15:41 -0700 Message-Id: <20211030171635.1689530-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616623253100001 Content-Type: text/plain; charset="utf-8" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- linux-user/host/aarch64/host-signal.h | 74 ++++++++++++++++++++- accel/tcg/user-exec.c | 94 +-------------------------- 2 files changed, 74 insertions(+), 94 deletions(-) diff --git a/linux-user/host/aarch64/host-signal.h b/linux-user/host/aarch6= 4/host-signal.h index f4b4d65031..02a55c3372 100644 --- a/linux-user/host/aarch64/host-signal.h +++ b/linux-user/host/aarch64/host-signal.h @@ -1 +1,73 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef AARCH64_HOST_SIGNAL_H +#define AARCH64_HOST_SIGNAL_H + +/* Pre-3.16 kernel headers don't have these, so provide fallback definitio= ns */ +#ifndef ESR_MAGIC +#define ESR_MAGIC 0x45535201 +struct esr_context { + struct _aarch64_ctx head; + uint64_t esr; +}; +#endif + +static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) +{ + return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; +} + +static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) +{ + return (struct _aarch64_ctx *)((char *)hdr + hdr->size); +} + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + struct _aarch64_ctx *hdr; + uint32_t insn; + + /* Find the esr_context, which has the WnR bit in it */ + for (hdr =3D first_ctx(uc); hdr->magic; hdr =3D next_ctx(hdr)) { + if (hdr->magic =3D=3D ESR_MAGIC) { + struct esr_context const *ec =3D (struct esr_context const *)h= dr; + uint64_t esr =3D ec->esr; + + /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR b= it */ + return extract32(esr, 27, 5) =3D=3D 0x12 && extract32(esr, 6, = 1) =3D=3D 1; + } + } + + /* + * Fall back to parsing instructions; will only be needed + * for really ancient (pre-3.16) kernels. + */ + insn =3D *(uint32_t *)host_signal_pc(uc); + + return (insn & 0xbfff0000) =3D=3D 0x0c000000 /* C3.3.1 */ + || (insn & 0xbfe00000) =3D=3D 0x0c800000 /* C3.3.2 */ + || (insn & 0xbfdf0000) =3D=3D 0x0d000000 /* C3.3.3 */ + || (insn & 0xbfc00000) =3D=3D 0x0d800000 /* C3.3.4 */ + || (insn & 0x3f400000) =3D=3D 0x08000000 /* C3.3.6 */ + || (insn & 0x3bc00000) =3D=3D 0x39000000 /* C3.3.13 */ + || (insn & 0x3fc00000) =3D=3D 0x3d800000 /* ... 128bit */ + /* Ignore bits 10, 11 & 21, controlling indexing. */ + || (insn & 0x3bc00000) =3D=3D 0x38000000 /* C3.3.8-12 */ + || (insn & 0x3fe00000) =3D=3D 0x3c800000 /* ... 128bit */ + /* Ignore bits 23 & 24, controlling indexing. */ + || (insn & 0x3a400000) =3D=3D 0x28000000; /* C3.3.7,14-16 */ +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index fabc8855a9..5cdbfab35b 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -253,99 +253,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__aarch64__) - -#if defined(__NetBSD__) - -#include -#include - -int cpu_signal_handler(int host_signum, void *pinfo, void *puc) -{ - ucontext_t *uc =3D puc; - siginfo_t *si =3D pinfo; - unsigned long pc; - int is_write; - uint32_t esr; - - pc =3D uc->uc_mcontext.__gregs[_REG_PC]; - esr =3D si->si_trap; - - /* - * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC - * is 0b10010x: then bit 6 is the WnR bit - */ - is_write =3D extract32(esr, 27, 5) =3D=3D 0x12 && extract32(esr, 6, 1)= =3D=3D 1; - return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask); -} - -#else - -#ifndef ESR_MAGIC -/* Pre-3.16 kernel headers don't have these, so provide fallback definitio= ns */ -#define ESR_MAGIC 0x45535201 -struct esr_context { - struct _aarch64_ctx head; - uint64_t esr; -}; -#endif - -static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) -{ - return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; -} - -static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) -{ - return (struct _aarch64_ctx *)((char *)hdr + hdr->size); -} - -int cpu_signal_handler(int host_signum, void *pinfo, void *puc) -{ - siginfo_t *info =3D pinfo; - ucontext_t *uc =3D puc; - uintptr_t pc =3D uc->uc_mcontext.pc; - bool is_write; - struct _aarch64_ctx *hdr; - struct esr_context const *esrctx =3D NULL; - - /* Find the esr_context, which has the WnR bit in it */ - for (hdr =3D first_ctx(uc); hdr->magic; hdr =3D next_ctx(hdr)) { - if (hdr->magic =3D=3D ESR_MAGIC) { - esrctx =3D (struct esr_context const *)hdr; - break; - } - } - - if (esrctx) { - /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ - uint64_t esr =3D esrctx->esr; - is_write =3D extract32(esr, 27, 5) =3D=3D 0x12 && extract32(esr, 6= , 1) =3D=3D 1; - } else { - /* - * Fall back to parsing instructions; will only be needed - * for really ancient (pre-3.16) kernels. - */ - uint32_t insn =3D *(uint32_t *)pc; - - is_write =3D ((insn & 0xbfff0000) =3D=3D 0x0c000000 /* C3.3.1 */ - || (insn & 0xbfe00000) =3D=3D 0x0c800000 /* C3.3.2 */ - || (insn & 0xbfdf0000) =3D=3D 0x0d000000 /* C3.3.3 */ - || (insn & 0xbfc00000) =3D=3D 0x0d800000 /* C3.3.4 */ - || (insn & 0x3f400000) =3D=3D 0x08000000 /* C3.3.6 */ - || (insn & 0x3bc00000) =3D=3D 0x39000000 /* C3.3.13 = */ - || (insn & 0x3fc00000) =3D=3D 0x3d800000 /* ... 128b= it */ - /* Ignore bits 10, 11 & 21, controlling indexing. */ - || (insn & 0x3bc00000) =3D=3D 0x38000000 /* C3.3.8-1= 2 */ - || (insn & 0x3fe00000) =3D=3D 0x3c800000 /* ... 128b= it */ - /* Ignore bits 23 & 24, controlling indexing. */ - || (insn & 0x3a400000) =3D=3D 0x28000000); /* C3.3.7,1= 4-16 */ - } - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#endif - -#elif defined(__s390__) +#if defined(__s390__) =20 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635616416129722.7832107272283; Sat, 30 Oct 2021 10:53:36 -0700 (PDT) Received: from localhost ([::1]:53444 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsXt-0000tJ-Sg for importer@patchew.org; Sat, 30 Oct 2021 13:53:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57616) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryQ-00025z-QP for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:54 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:46793) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryM-000081-Bf for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:53 -0400 Received: by mail-pg1-x52d.google.com with SMTP id m21so12952478pgu.13 for ; Sat, 30 Oct 2021 10:16:49 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=62zfa97eDd8IjxitzdW43+81lSbg3lzSCBc6OjWVN/U=; b=oF93bzObM114dEqJFd6nS5BRumvf7TS3Td+hzbYvWHUvObkRYNypwebLIoAmWh4aPN EL/IYWENRe/fUcNjGw+JyZ3KyhmKkTYmUZqADSxOGa0QYhbHUeAAI3jUQvgXCqJg7aDt I86tfSF+clyXRHkNEYWoASnsJYZWUvr8Q4hbPeI5tqfeYw+v5BuVDpZLWnmQlsfaIUau aBzblc8Na/xJe5NlAw7QY4qMrZtv96968paDxJB08l2rpY6QPLlYmyEr544Y6S8vVag7 47uq3H+9YSOPEAvYExyQColbJPLp8rHmmIYgXXNxqbxmpgwSrTlVxWDODWvq/dljTGtf 04yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=62zfa97eDd8IjxitzdW43+81lSbg3lzSCBc6OjWVN/U=; b=uQKSNeO9NHJAsfbOOdDNBZ163h+Gk6bvZaCc7Sxg7FnTpj9MJftSaDaesK9GAC+4P/ jHPywx98YHPr3M33pcxPTRpjP1tXzMdpXTeQx7+Icst7qac8z/z3j2HuEVTfU4OXVBuH oDZrEV9I7xy0hRsexx6zosx+VWp0RWsvcnqdyGCIqbCFpwYhW3zvnhaaEPzfyromhrXh 1WDDQv6WVqeRD1WzX/n0HbYr6WoN/ZSkO+cfktsVmwwzi4nk83b+uAwDFaNlGmynLv0t g5snp8N9rvpiIzKYZrf9O9BZkKBCO2uynhBC6BxRAhmy+MBjpj/YHorEk9pikM2RlaaK nV1g== X-Gm-Message-State: AOAM5315+iZUlaeo4zDj0d2EIcW/uHamDudPHpKQ1zvYPCIfgFwAJzEm iOu+RRoRL9MoGRwRrnsSEMLS6HHDaHVQBA== X-Google-Smtp-Source: ABdhPJwhpbIVRjwmxw/EUEEEyZwoC4U1bJkOleclhf89ylvlPM8AYB/O01UUig4DTo1BUDLBv1veAg== X-Received: by 2002:aa7:8059:0:b0:47e:5de6:5bc7 with SMTP id y25-20020aa78059000000b0047e5de65bc7mr14397718pfm.78.1635614209037; Sat, 30 Oct 2021 10:16:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 13/66] linux-user/host/s390: Populate host_signal.h Date: Sat, 30 Oct 2021 10:15:42 -0700 Message-Id: <20211030171635.1689530-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616418334100001 Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- linux-user/host/s390/host-signal.h | 93 ++++++++++++++++++++++++++++- linux-user/host/s390x/host-signal.h | 2 +- accel/tcg/user-exec.c | 88 +-------------------------- 3 files changed, 94 insertions(+), 89 deletions(-) diff --git a/linux-user/host/s390/host-signal.h b/linux-user/host/s390/host= -signal.h index f4b4d65031..21f59b612a 100644 --- a/linux-user/host/s390/host-signal.h +++ b/linux-user/host/s390/host-signal.h @@ -1 +1,92 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef S390_HOST_SIGNAL_H +#define S390_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.psw.addr; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint16_t *pinsn =3D (uint16_t *)host_signal_pc(uc); + + /* + * ??? On linux, the non-rt signal handler has 4 (!) arguments instead + * of the normal 2 arguments. The 4th argument contains the "Translat= ion- + * Exception Identification for DAT Exceptions" from the hardware (aka + * "int_parm_long"), which does in fact contain the is_write value. + * The rt signal handler, as far as I can tell, does not give this val= ue + * at all. Not that we could get to it from here even if it were. + * So fall back to parsing instructions. Treat read-modify-write ones= as + * writes, which is not fully correct, but for tracking self-modifying= code + * this is better than treating them as reads. Checking si_addr page = flags + * might be a viable improvement, albeit a racy one. + */ + /* ??? This is not even close to complete. */ + switch (pinsn[0] >> 8) { + case 0x50: /* ST */ + case 0x42: /* STC */ + case 0x40: /* STH */ + case 0xba: /* CS */ + case 0xbb: /* CDS */ + return true; + case 0xc4: /* RIL format insns */ + switch (pinsn[0] & 0xf) { + case 0xf: /* STRL */ + case 0xb: /* STGRL */ + case 0x7: /* STHRL */ + return true; + } + break; + case 0xc8: /* SSF format insns */ + switch (pinsn[0] & 0xf) { + case 0x2: /* CSST */ + return true; + } + break; + case 0xe3: /* RXY format insns */ + switch (pinsn[2] & 0xff) { + case 0x50: /* STY */ + case 0x24: /* STG */ + case 0x72: /* STCY */ + case 0x70: /* STHY */ + case 0x8e: /* STPQ */ + case 0x3f: /* STRVH */ + case 0x3e: /* STRV */ + case 0x2f: /* STRVG */ + return true; + } + break; + case 0xeb: /* RSY format insns */ + switch (pinsn[2] & 0xff) { + case 0x14: /* CSY */ + case 0x30: /* CSG */ + case 0x31: /* CDSY */ + case 0x3e: /* CDSG */ + case 0xe4: /* LANG */ + case 0xe6: /* LAOG */ + case 0xe7: /* LAXG */ + case 0xe8: /* LAAG */ + case 0xea: /* LAALG */ + case 0xf4: /* LAN */ + case 0xf6: /* LAO */ + case 0xf7: /* LAX */ + case 0xfa: /* LAAL */ + case 0xf8: /* LAA */ + return true; + } + break; + } + return false; +} + +#endif diff --git a/linux-user/host/s390x/host-signal.h b/linux-user/host/s390x/ho= st-signal.h index f4b4d65031..0e83f9358d 100644 --- a/linux-user/host/s390x/host-signal.h +++ b/linux-user/host/s390x/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../s390/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 5cdbfab35b..f18f3b2a5c 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -253,93 +253,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__s390__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; - ucontext_t *uc =3D puc; - unsigned long pc; - uint16_t *pinsn; - int is_write =3D 0; - - pc =3D uc->uc_mcontext.psw.addr; - - /* - * ??? On linux, the non-rt signal handler has 4 (!) arguments instead - * of the normal 2 arguments. The 4th argument contains the "Translat= ion- - * Exception Identification for DAT Exceptions" from the hardware (aka - * "int_parm_long"), which does in fact contain the is_write value. - * The rt signal handler, as far as I can tell, does not give this val= ue - * at all. Not that we could get to it from here even if it were. - * So fall back to parsing instructions. Treat read-modify-write ones= as - * writes, which is not fully correct, but for tracking self-modifying= code - * this is better than treating them as reads. Checking si_addr page = flags - * might be a viable improvement, albeit a racy one. - */ - /* ??? This is not even close to complete. */ - pinsn =3D (uint16_t *)pc; - switch (pinsn[0] >> 8) { - case 0x50: /* ST */ - case 0x42: /* STC */ - case 0x40: /* STH */ - case 0xba: /* CS */ - case 0xbb: /* CDS */ - is_write =3D 1; - break; - case 0xc4: /* RIL format insns */ - switch (pinsn[0] & 0xf) { - case 0xf: /* STRL */ - case 0xb: /* STGRL */ - case 0x7: /* STHRL */ - is_write =3D 1; - } - break; - case 0xc8: /* SSF format insns */ - switch (pinsn[0] & 0xf) { - case 0x2: /* CSST */ - is_write =3D 1; - } - break; - case 0xe3: /* RXY format insns */ - switch (pinsn[2] & 0xff) { - case 0x50: /* STY */ - case 0x24: /* STG */ - case 0x72: /* STCY */ - case 0x70: /* STHY */ - case 0x8e: /* STPQ */ - case 0x3f: /* STRVH */ - case 0x3e: /* STRV */ - case 0x2f: /* STRVG */ - is_write =3D 1; - } - break; - case 0xeb: /* RSY format insns */ - switch (pinsn[2] & 0xff) { - case 0x14: /* CSY */ - case 0x30: /* CSG */ - case 0x31: /* CDSY */ - case 0x3e: /* CDSG */ - case 0xe4: /* LANG */ - case 0xe6: /* LAOG */ - case 0xe7: /* LAXG */ - case 0xe8: /* LAAG */ - case 0xea: /* LAALG */ - case 0xf4: /* LAN */ - case 0xf6: /* LAO */ - case 0xf7: /* LAX */ - case 0xfa: /* LAAL */ - case 0xf8: /* LAA */ - is_write =3D 1; - } - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__mips__) +#if defined(__mips__) =20 #if defined(__misp16) || defined(__mips_micromips) #error "Unsupported encoding" --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16356161370191013.63662228281; Sat, 30 Oct 2021 10:48:57 -0700 (PDT) Received: from localhost ([::1]:37444 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsTP-0006Xh-Re for importer@patchew.org; Sat, 30 Oct 2021 13:48:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57620) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryR-00026K-1K for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:55 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:50847) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryN-00008Y-K2 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:54 -0400 Received: by mail-pj1-x1033.google.com with SMTP id gn3so9424847pjb.0 for ; Sat, 30 Oct 2021 10:16:50 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GVyuVfBLUsP48XbipgJRPRSFYM8xv0AU+cHAMBmvhxg=; b=qisFtjq3ErDK/nRONF2XhUAEhT2cuUHtffyhBTCNFwYVcJJouDYH5u34r+FI8NMPxQ WjsYbXxWU5g94isQIbCbna6F5PVBNrjKWQNx8r03nMdLGOVcwBTFx70OT/XkxT6Dq9/C DZ5l4W7Va0boTeukR3T4ucX8fLP0rVTFyibD+WuQ0tBOjxWeYl0v6l90w7IPJMcakcAz HJB+LyFui4R91SiLEXqyHQHaCbqBZVFUS1WVgHbyqoXTfdv1lkpQJN4tfrcOkT0XH0fa /D04/S02rED2feYksMeWg/FiE2p72PsYBEgIqmT/UUO5DBNIht3RsnJ+E/bp2co8Xsk/ 3HXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GVyuVfBLUsP48XbipgJRPRSFYM8xv0AU+cHAMBmvhxg=; b=qtec8aNQvSp4x2LDNs4SdhG/UoUynTb+ro/XrlxK2K6qa4lqqdmTaB6N8tnBtDgiCX G/WduYfivo7Cizh5sMYTjiwHPnYoTaUt/RwJs8HUnllX37d8vqf5Uz8Ps2Ais6lCVn1y UnIBoq6Z+BZJ7tiqkuvSwLBp+XZPw5VF7BZFoo6TNLkwju8f9roaKGh44UCLbFy6juxx cQ5vqFlOTUB1cg2QrMge6+S1HI3lL3AAylvdzZdSK8VpTysobTgWZ3l8qSPHnoo2Y7AE 1FWo56XDBOz4SRMoBMUoBmLFap30v+Ks4OsWGrMoWBLojvOPo81E9f44xg36ER91ktvi izag== X-Gm-Message-State: AOAM5326ZAraRZRAPMcnRdC8+sU1YvIcKPChd5dO+ZCZQqcUHl3kaooJ gYDYn5ps3c3BgDFneZ07kDxuORM1Y5z7BQ== X-Google-Smtp-Source: ABdhPJzQqygyJlEl3plYknmRoL/MbKPgSdfpwdUT4BrbyFucQgnw5cMjqQDmkRoDklTg/B9Iu9mfzg== X-Received: by 2002:a17:90b:92:: with SMTP id bb18mr9230080pjb.133.1635614210085; Sat, 30 Oct 2021 10:16:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 14/66] linux-user/host/mips: Populate host_signal.h Date: Sat, 30 Oct 2021 10:15:43 -0700 Message-Id: <20211030171635.1689530-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616138985100001 Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- linux-user/host/mips/host-signal.h | 62 +++++++++++++++++++++++++++++- accel/tcg/user-exec.c | 52 +------------------------ 2 files changed, 62 insertions(+), 52 deletions(-) diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host= -signal.h index f4b4d65031..9c83e51130 100644 --- a/linux-user/host/mips/host-signal.h +++ b/linux-user/host/mips/host-signal.h @@ -1 +1,61 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef MIPS_HOST_SIGNAL_H +#define MIPS_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.pc; +} + +#if defined(__misp16) || defined(__mips_micromips) +#error "Unsupported encoding" +#endif + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn =3D *(uint32_t *)host_signal_pc(uc); + + /* Detect all store instructions at program counter. */ + switch ((insn >> 26) & 077) { + case 050: /* SB */ + case 051: /* SH */ + case 052: /* SWL */ + case 053: /* SW */ + case 054: /* SDL */ + case 055: /* SDR */ + case 056: /* SWR */ + case 070: /* SC */ + case 071: /* SWC1 */ + case 074: /* SCD */ + case 075: /* SDC1 */ + case 077: /* SD */ +#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 + case 072: /* SWC2 */ + case 076: /* SDC2 */ +#endif + return true; + case 023: /* COP1X */ + /* + * Required in all versions of MIPS64 since + * MIPS64r1 and subsequent versions of MIPS32r2. + */ + switch (insn & 077) { + case 010: /* SWXC1 */ + case 011: /* SDXC1 */ + case 015: /* SUXC1 */ + return true; + } + break; + } + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index f18f3b2a5c..44c83acba5 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -253,57 +253,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__mips__) - -#if defined(__misp16) || defined(__mips_micromips) -#error "Unsupported encoding" -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; - ucontext_t *uc =3D puc; - uintptr_t pc =3D uc->uc_mcontext.pc; - uint32_t insn =3D *(uint32_t *)pc; - int is_write =3D 0; - - /* Detect all store instructions at program counter. */ - switch((insn >> 26) & 077) { - case 050: /* SB */ - case 051: /* SH */ - case 052: /* SWL */ - case 053: /* SW */ - case 054: /* SDL */ - case 055: /* SDR */ - case 056: /* SWR */ - case 070: /* SC */ - case 071: /* SWC1 */ - case 074: /* SCD */ - case 075: /* SDC1 */ - case 077: /* SD */ -#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 - case 072: /* SWC2 */ - case 076: /* SDC2 */ -#endif - is_write =3D 1; - break; - case 023: /* COP1X */ - /* Required in all versions of MIPS64 since - MIPS64r1 and subsequent versions of MIPS32r2. */ - switch (insn & 077) { - case 010: /* SWXC1 */ - case 011: /* SDXC1 */ - case 015: /* SUXC1 */ - is_write =3D 1; - } - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__riscv) +#if defined(__riscv) =20 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635616344882921.385223098165; Sat, 30 Oct 2021 10:52:24 -0700 (PDT) Received: from localhost ([::1]:48572 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsWl-0005qj-Ox for importer@patchew.org; Sat, 30 Oct 2021 13:52:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57678) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryS-0002C3-Un for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:58 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:35328) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryO-00008u-Cu for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:56 -0400 Received: by mail-pg1-x534.google.com with SMTP id q187so13053378pgq.2 for ; Sat, 30 Oct 2021 10:16:51 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JRZ2W+REhExzE7Xzq9uZafkG/y3VEUNUJDLWbd/Xczw=; b=UZ6ES7rwSR4pyFiyD/EOl1Kz17EipWv+kwdRNJtZB6US/EyNnenE1xRIjAVHLtOEjq ck+3vQ5AXXWZ6/Wo9e9bexcZC6owsc9ihtQ12NTyi1Qaa6eLh+Xcl1fL7zajl6AMJiNs P8kWmEnliUYjGGpCy2ekoWrZqK8nwmqTG12mofGXNy7YqrA1sizj2xWRo4rP6fo/4wzg LzzYbX5yIJ5CDP4OAIh+AhrBJKjehyA+cJPjG/WMS0OaN9j1ba3LeLUfzlHMKmrVzN7b DxDVaRj2yUxiHOq9DejIW6l2x+zH1OjNkC/VskINBGdhDumeL4eZ1jOYM+YzZ0YYrLr9 t5Eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JRZ2W+REhExzE7Xzq9uZafkG/y3VEUNUJDLWbd/Xczw=; b=YB3I7SlK8KXDLYKDaQNkyxCPEJ7y1DI9WU7/4vP0/AK5AQFJAAvUXY2iFKc0Ooib0h ImYmWb3nTRniZpoAJaesAzNrsYkpPSk6oGOOvcr1wqN038R8kCMGzSZ75NyvroQ5ggy3 pWMpnBRVQkeNSzSZri3+0EloHwQ/KiAiP3n4fcYBF25GkxFJWq/ZaSb9/2YANSQ5SOZ2 CoT3T69DcjHbGzFPHKEhO+jz1VRO2RPGmmecOKXHRygvnH7iCbN9ZBc+uKQUwdXJngOH zn2gmn8Ei9bfwJFd0+j6Z+ycVHxlNwgsXfYhgJSq0mhUP8VTvefY6VmV3LvXNJPSVrLh PhQg== X-Gm-Message-State: AOAM532qZbQvailTAXWFs4zUFbvEH9sI5Cbi/VxLqOc6i7Ql7Yj0k3f+ Aq1o9Ag9D9nosByV8bDdsRPF5JtHkUyOoA== X-Google-Smtp-Source: ABdhPJxAsGHktzEhl3NfCgsqVjop0TEcXzKAgwSZkaVffyFKxZ4NDoCqeaLWCz/ih5I4dmt5OY/0EQ== X-Received: by 2002:a05:6a00:2309:b0:47c:fb3:f127 with SMTP id h9-20020a056a00230900b0047c0fb3f127mr18294177pfh.78.1635614210851; Sat, 30 Oct 2021 10:16:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 15/66] linux-user/host/riscv: Populate host_signal.h Date: Sat, 30 Oct 2021 10:15:44 -0700 Message-Id: <20211030171635.1689530-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616345508100001 Content-Type: text/plain; charset="utf-8" Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Warner Losh Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/host/riscv/host-signal.h | 85 +++++++++++++++++- accel/tcg/user-exec.c | 134 ---------------------------- 2 files changed, 84 insertions(+), 135 deletions(-) diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/ho= st-signal.h index f4b4d65031..5860dce7d7 100644 --- a/linux-user/host/riscv/host-signal.h +++ b/linux-user/host/riscv/host-signal.h @@ -1 +1,84 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef RISCV_HOST_SIGNAL_H +#define RISCV_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.__gregs[REG_PC]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn =3D *(uint32_t *)host_signal_pc(uc); + + /* + * Detect store by reading the instruction at the program + * counter. Note: we currently only generate 32-bit + * instructions so we thus only detect 32-bit stores + */ + switch (((insn >> 0) & 0b11)) { + case 3: + switch (((insn >> 2) & 0b11111)) { + case 8: + switch (((insn >> 12) & 0b111)) { + case 0: /* sb */ + case 1: /* sh */ + case 2: /* sw */ + case 3: /* sd */ + case 4: /* sq */ + return true; + default: + break; + } + break; + case 9: + switch (((insn >> 12) & 0b111)) { + case 2: /* fsw */ + case 3: /* fsd */ + case 4: /* fsq */ + return true; + default: + break; + } + break; + default: + break; + } + } + + /* Check for compressed instructions */ + switch (((insn >> 13) & 0b111)) { + case 7: + switch (insn & 0b11) { + case 0: /*c.sd */ + case 2: /* c.sdsp */ + return true; + default: + break; + } + break; + case 6: + switch (insn & 0b11) { + case 0: /* c.sw */ + case 3: /* c.swsp */ + return true; + default: + break; + } + break; + default: + break; + } + + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 44c83acba5..a0cba61e83 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -137,64 +137,6 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset= _t *old_set, } } =20 -/* - * 'pc' is the host PC at which the exception was raised. - * 'address' is the effective address of the memory exception. - * 'is_write' is 1 if a write caused the exception and otherwise 0. - * 'old_set' is the signal set which should be restored. - */ -static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, - int is_write, sigset_t *old_set) -{ - CPUState *cpu =3D current_cpu; - CPUClass *cc; - unsigned long host_addr =3D (unsigned long)info->si_addr; - MMUAccessType access_type =3D adjust_signal_pc(&pc, is_write); - abi_ptr guest_addr; - - /* For synchronous signals we expect to be coming from the vCPU - * thread (so current_cpu should be valid) and either from running - * code or during translation which can fault as we cross pages. - * - * If neither is true then something has gone wrong and we should - * abort rather than try and restart the vCPU execution. - */ - if (!cpu || !cpu->running) { - printf("qemu:%s received signal outside vCPU context @ pc=3D0x%" - PRIxPTR "\n", __func__, pc); - abort(); - } - -#if defined(DEBUG_SIGNAL) - printf("qemu: SIGSEGV pc=3D0x%08lx address=3D%08lx w=3D%d oldset=3D0x%= 08lx\n", - pc, host_addr, is_write, *(unsigned long *)old_set); -#endif - - /* Convert forcefully to guest address space, invalid addresses - are still valid segv ones */ - guest_addr =3D h2g_nocheck(host_addr); - - /* XXX: locking issue */ - if (is_write && - info->si_signo =3D=3D SIGSEGV && - info->si_code =3D=3D SEGV_ACCERR && - h2g_valid(host_addr) && - handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) { - return 1; - } - - /* - * There is no way the target can handle this other than raising - * an exception. Undo signal and retaddr state prior to longjmp. - */ - sigprocmask(SIG_SETMASK, old_set, NULL); - - cc =3D CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, - MMU_USER_IDX, false, pc); - g_assert_not_reached(); -} - static int probe_access_internal(CPUArchState *env, target_ulong addr, int fault_size, MMUAccessType access_type, bool nonfault, uintptr_t ra) @@ -253,82 +195,6 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__riscv) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; - ucontext_t *uc =3D puc; - greg_t pc =3D uc->uc_mcontext.__gregs[REG_PC]; - uint32_t insn =3D *(uint32_t *)pc; - int is_write =3D 0; - - /* Detect store by reading the instruction at the program - counter. Note: we currently only generate 32-bit - instructions so we thus only detect 32-bit stores */ - switch (((insn >> 0) & 0b11)) { - case 3: - switch (((insn >> 2) & 0b11111)) { - case 8: - switch (((insn >> 12) & 0b111)) { - case 0: /* sb */ - case 1: /* sh */ - case 2: /* sw */ - case 3: /* sd */ - case 4: /* sq */ - is_write =3D 1; - break; - default: - break; - } - break; - case 9: - switch (((insn >> 12) & 0b111)) { - case 2: /* fsw */ - case 3: /* fsd */ - case 4: /* fsq */ - is_write =3D 1; - break; - default: - break; - } - break; - default: - break; - } - } - - /* Check for compressed instructions */ - switch (((insn >> 13) & 0b111)) { - case 7: - switch (insn & 0b11) { - case 0: /*c.sd */ - case 2: /* c.sdsp */ - is_write =3D 1; - break; - default: - break; - } - break; - case 6: - switch (insn & 0b11) { - case 0: /* c.sw */ - case 3: /* c.swsp */ - is_write =3D 1; - break; - default: - break; - } - break; - default: - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#endif - /* The softmmu versions of these helpers are in cputlb.c. */ =20 /* --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635616989955843.1295171033476; Sat, 30 Oct 2021 11:03:09 -0700 (PDT) Received: from localhost ([::1]:55356 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgshA-0004G6-RN for importer@patchew.org; Sat, 30 Oct 2021 14:03:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57708) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryU-0002DY-RG for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:00 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:37628) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryO-000095-Sh for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:58 -0400 Received: by mail-pf1-x42b.google.com with SMTP id y20so1544404pfi.4 for ; Sat, 30 Oct 2021 10:16:52 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gSr02Sd1ztBN32tTKGrZscSunLegESBnCl09IIG3Qgg=; b=hdvxRhN9/MmKPfvGfh1+/FXOKxtpLNrLFFuwTDTPwDY7Nh8MS0TnLMpv7zBjd0gwGU 9Ks7LQF3Mzvx+Mwckf2v4CPQMtAl6JOvcR2HW+YelQ8Em0T57MHBoYY1SIlO9t0NGbWf LD+6HJnQvjNEjhaiA8Ya7W2hgCKMf3Kw3q55WzFST4fiY7Ei+D/XAudzH4zB2LU3SUUm 3wbK2z/7x9+zWX6aHgex33o6OTaWUBdpVrRzVILXHGgJUhHIJSTZzfq8A3NuaEhXrsi/ d63CDCaUTFMWHK5S2o/GZ5DqAOHK74v5jkedLDctl/7IEsDcSa4MKVnfXLnwH9Cqr6D9 2bOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gSr02Sd1ztBN32tTKGrZscSunLegESBnCl09IIG3Qgg=; b=wdHsU4u6epNsS+BTuhgCoi1bMKhQdAi4yR9OqHyWCkBqJoYvWrqoSkYgwzSuUkyxhp XfcwtUpAXDix/12HDNDVBtheCVpNMR7mB72Bs8GEibuworto5tD5raDpiT8vK97R54gN f+KPXK7ThLBc1tWjIUkuBrnMPoLSB8OPz0XNIKVJNDB0Ym1j58RwkVOv+SFFRVRa/QHL IfHSDMhUaVmAX52I3Mh3PYKutSRurniIoF2/psroY64aZPCZk3KLtnQqQWua9qyXdAe6 Ko4O5Az0br6M3Ekxi/LwMPeaJi5YHLSbJFYU9l68/93o/BMBHwjAb54KvLR2m5DEv+OV npug== X-Gm-Message-State: AOAM5322QKH9Cl3VNJ3WFSZJs9/a/Zl80nDmKW1OQLLBGrHx+gZqpmya WWWLxgzAROE1NvaHvK0cdrTIRfpdyAsBQg== X-Google-Smtp-Source: ABdhPJyIE9YerlcY4WIyYo6zOqsS/d2QxCa8wYVmwccZqiAoLw5NDkJwSZ4VJBdZSePJewAFfkAiYQ== X-Received: by 2002:a65:6ab0:: with SMTP id x16mr13890226pgu.181.1635614211619; Sat, 30 Oct 2021 10:16:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 16/66] target/arm: Fixup comment re handle_cpu_signal Date: Sat, 30 Oct 2021 10:15:45 -0700 Message-Id: <20211030171635.1689530-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616990597100001 The named function no longer exists. Refer to host_signal_handler instead. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index dab5f1d1cd..07be55b7e1 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -6118,7 +6118,7 @@ DO_LDN_2(4, dd, MO_64) * linux-user/ in its get_user/put_user macros. * * TODO: Construct some helpers, written in assembly, that interact with - * handle_cpu_signal to produce memory ops which can properly report errors + * host_signal_handler to produce memory ops which can properly report err= ors * without racing. */ =20 --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163561529392460.14218093195234; Sat, 30 Oct 2021 10:34:53 -0700 (PDT) Received: from localhost ([::1]:45084 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsFo-0000P8-Qy for importer@patchew.org; Sat, 30 Oct 2021 13:34:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57710) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryU-0002DZ-RB for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:00 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:41657) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryQ-00009N-HV for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:57 -0400 Received: by mail-pf1-x429.google.com with SMTP id u33so277848pfg.8 for ; Sat, 30 Oct 2021 10:16:53 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T6s+8p22L/kJt7ysU37rV/HmGCKRECxNpTVVs5PRRQU=; b=UFUe2cSHFQOsLrAKfKi0PhzDP/ZvDEZzljnGgNOEbHypVEACTSHShkND+gQMkHOnpB QKE4wxJSGBWX2bKvJy50wb0ikK1Q57b/ZOtGQTuwDuJ6EBoVFLEo1z45YchGb7SjeJw7 9uvtcAZVWGbf8M20sE6R+jha0mpYOsQOGHgEwCzTCyX/nmWdb/CpkzbwrDCCx9z+PFMv VF+LnocNKE0WbPOKRNQWK+kPc9nMAEzyOE1keL7t3ZbOKzRAUYLZJ761h5JKOmnshbYd plWVqwzTvpwEJ3nmZzGm3YKqQnCdWodoQM5pxefydThui3pureaALjr7eojlhDTy+TJX JNNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T6s+8p22L/kJt7ysU37rV/HmGCKRECxNpTVVs5PRRQU=; b=aRVkrzcVKMWCR9xbBJHe2gSz9NZ/ARRLC7vZ/Mjh99/QewDJeTbjThkyyirZqPBn58 OrWQn9S131buIukIzpIen1STHWVTgoeoGskt6Ibgw9aafgR5MVkPT2U9V+Ulz7+1YMC9 cCbbrjkuWjIg1/IWNlAuie0HET85AUteVe16/bp+TYcgSlzcr1vtvZYH7p9dap2XRM38 o0YRObfWoyxu/dA2cIIOPbzmQOmxYfFCIpC0878RffJrL2NBBtJqSpYNmXvIiqd0NTDk KbruFbYSB4AQLnetXLeRuXAKaN8tvhLwXzfkVHKzQiYfuCgaHD4Bju2CrAknxs0W0F4f pSbw== X-Gm-Message-State: AOAM532S0QJztvp6h1HnT3D4o4RTE4U7MYwf2y2S9Homa9zH2MUkKe3c qFX32i4sSrdOFq0Fkn3YOCTFbRYQP9r5nA== X-Google-Smtp-Source: ABdhPJy3arkeFnxYZuqwNE0zVbLxkP63bwxqmhTlujwAh1AmeIx0qJBRLBM57Bxewt3NfOu+qMCv3w== X-Received: by 2002:a62:3306:0:b0:480:f89c:c251 with SMTP id z6-20020a623306000000b00480f89cc251mr1531825pfz.74.1635614212876; Sat, 30 Oct 2021 10:16:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 17/66] linux-user/host/riscv: Improve host_signal_write Date: Sat, 30 Oct 2021 10:15:46 -0700 Message-Id: <20211030171635.1689530-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635615295576100003 Content-Type: text/plain; charset="utf-8" Do not read 4 bytes before we determine the size of the insn. Simplify triple switches in favor of checking major opcodes. Include the missing cases of compact fsd and fsdsp. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/host/riscv/host-signal.h | 83 ++++++++++------------------- 1 file changed, 28 insertions(+), 55 deletions(-) diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/ho= st-signal.h index 5860dce7d7..ab06d70964 100644 --- a/linux-user/host/riscv/host-signal.h +++ b/linux-user/host/riscv/host-signal.h @@ -17,65 +17,38 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc) =20 static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) { - uint32_t insn =3D *(uint32_t *)host_signal_pc(uc); - /* - * Detect store by reading the instruction at the program - * counter. Note: we currently only generate 32-bit - * instructions so we thus only detect 32-bit stores + * Detect store by reading the instruction at the program counter. + * Do not read more than 16 bits, because we have not yet determined + * the size of the instruction. */ - switch (((insn >> 0) & 0b11)) { - case 3: - switch (((insn >> 2) & 0b11111)) { - case 8: - switch (((insn >> 12) & 0b111)) { - case 0: /* sb */ - case 1: /* sh */ - case 2: /* sw */ - case 3: /* sd */ - case 4: /* sq */ - return true; - default: - break; - } - break; - case 9: - switch (((insn >> 12) & 0b111)) { - case 2: /* fsw */ - case 3: /* fsd */ - case 4: /* fsq */ - return true; - default: - break; - } - break; - default: - break; - } + const uint16_t *pinsn =3D (const uint16_t *)host_signal_pc(uc); + uint16_t insn =3D pinsn[0]; + + /* 16-bit instructions */ + switch (insn & 0xe003) { + case 0xa000: /* c.fsd */ + case 0xc000: /* c.sw */ + case 0xe000: /* c.sd (rv64) / c.fsw (rv32) */ + case 0xa002: /* c.fsdsp */ + case 0xc002: /* c.swsp */ + case 0xe002: /* c.sdsp (rv64) / c.fswsp (rv32) */ + return true; } =20 - /* Check for compressed instructions */ - switch (((insn >> 13) & 0b111)) { - case 7: - switch (insn & 0b11) { - case 0: /*c.sd */ - case 2: /* c.sdsp */ - return true; - default: - break; - } - break; - case 6: - switch (insn & 0b11) { - case 0: /* c.sw */ - case 3: /* c.swsp */ - return true; - default: - break; - } - break; - default: - break; + /* 32-bit instructions, major opcodes */ + switch (insn & 0x7f) { + case 0x23: /* store */ + case 0x27: /* store-fp */ + return true; + case 0x2f: /* amo */ + /* + * The AMO function code is in bits 25-31, unread as yet. + * The AMO functions are LR (read), SC (write), and the + * rest are all read-modify-write. + */ + insn =3D pinsn[1]; + return (insn >> 11) !=3D 2; /* LR */ } =20 return false; --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635616477815899.1117190147069; Sat, 30 Oct 2021 10:54:37 -0700 (PDT) Received: from localhost ([::1]:57032 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsYu-0003L4-M0 for importer@patchew.org; Sat, 30 Oct 2021 13:54:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57712) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryV-0002De-4z for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:00 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:39614) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryR-00009U-27 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:58 -0400 Received: by mail-pf1-x42a.google.com with SMTP id b1so8788181pfm.6 for ; Sat, 30 Oct 2021 10:16:54 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BEoOYfyvrRlliP3CVpcV5+AEGq6qhapGY3bb4mVGTHg=; b=pXc5aelQRjCX3AXjADbdUa8FmuaEUSfgXyeEzLQfdVXjET8TDDDqTwdE5pe3qPlHXe gjMTvg8xZVCEPOfMv0ZB3dNyOaYXpDmxteqK15rCD1Unv5w5oJ6/bLb6PjNNR4XI1x+v NQX7ZEzKVNpNw/eo1y7pdGKB1NxHfNOQmz5rZV+YwaAcJGuds/tw5zzE73g/bfRNMAfi TaGAS/KR3+zHPN6M0ztiskk1Zh69oxeAteGjVyKXLucSk/0z+srmrl49yW32jxU+Gk5D M3S6VWix8TWajcD8Wr+4YYnxiDSbZJifqrePYsBeI2aEZkuHZ6ui1J9cBahAIsph51+Q MNSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BEoOYfyvrRlliP3CVpcV5+AEGq6qhapGY3bb4mVGTHg=; b=qP016JlrWrZFChp0a2DlXT782oHOjg+ke5GPVnRBlZZe36IBM6N+mNS3eiARAobKBL fo/H1mFjsHgdHCuhyf8HEezIsfh/8EM7l/a5deqEkmQQoQE6ocAmL2fLHipk/h7uPqFu Nn3eaSG/E+H2YiKYC+3ikKRage6u0uh7TELj4ORPEWq2P1Hn5o2i/guUNYXFb7fKiA4S sOftF/oku3VpRE2MFpS+JHeiJVHWjcNgVfnfyPA0zkmkKyOXCg37xXhrYDluFkAPik8+ ULeIiLS2u0LvghmmFZSiESyc1LWowFtg7PCOUuIunoKlyX7ELGxFk9qY4LWCYCjpPJaJ /Lxw== X-Gm-Message-State: AOAM533rqFdo2rum14AqqyqcyJgo7I0vHIXsnj4DceGg2CDxRxVHQLp4 cD1GPbKtexvsY15lZvea+rgwEgTmhMP/fg== X-Google-Smtp-Source: ABdhPJykUDIkGBcroN/4GWSu+ZXzlvEMSPXFzT+uuemrima/GEdvjQeCdGBHjRvDuKQI2VdvkII0cQ== X-Received: by 2002:a05:6a00:c81:b029:30e:21bf:4c15 with SMTP id a1-20020a056a000c81b029030e21bf4c15mr18131490pfv.70.1635614213710; Sat, 30 Oct 2021 10:16:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 18/66] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Date: Sat, 30 Oct 2021 10:15:47 -0700 Message-Id: <20211030171635.1689530-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616478496100001 Now that all of the linux-user hosts have been converted to host-signal.h, drop the compatibility code. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 12 ------------ linux-user/signal.c | 14 -------------- 2 files changed, 26 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5f94d799aa..5dd663c153 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -685,18 +685,6 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_= write); bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, uintptr_t host_pc, abi_ptr guest_addr); =20 -/** - * cpu_signal_handler - * @signum: host signal number - * @pinfo: host siginfo_t - * @puc: host ucontext_t - * - * To be called from the SIGBUS and SIGSEGV signal handler to inform the - * virtual cpu of exceptions. Returns true if the signal was handled by - * the virtual CPU. - */ -int cpu_signal_handler(int signum, void *pinfo, void *puc); - #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/linux-user/signal.c b/linux-user/signal.c index 6900acb122..b816678ba5 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -780,17 +780,6 @@ static void host_signal_handler(int host_sig, siginfo_= t *info, void *puc) ucontext_t *uc =3D puc; struct emulated_sigtable *k; int guest_sig; - -#ifdef HOST_SIGNAL_PLACEHOLDER - /* the CPU emulator uses some host signals to detect exceptions, - we forward to it some signals */ - if ((host_sig =3D=3D SIGSEGV || host_sig =3D=3D SIGBUS) - && info->si_code > 0) { - if (cpu_signal_handler(host_sig, info, puc)) { - return; - } - } -#else uintptr_t pc =3D 0; bool sync_sig =3D false; =20 @@ -850,7 +839,6 @@ static void host_signal_handler(int host_sig, siginfo_t= *info, void *puc) =20 sync_sig =3D true; } -#endif =20 /* get target signal number */ guest_sig =3D host_to_target_signal(host_sig); @@ -865,7 +853,6 @@ static void host_signal_handler(int host_sig, siginfo_t= *info, void *puc) k->pending =3D guest_sig; ts->signal_pending =3D 1; =20 -#ifndef HOST_SIGNAL_PLACEHOLDER /* * For synchronous signals, unwind the cpu state to the faulting * insn and then exit back to the main loop so that the signal @@ -875,7 +862,6 @@ static void host_signal_handler(int host_sig, siginfo_t= *info, void *puc) cpu->exception_index =3D EXCP_INTERRUPT; cpu_loop_exit_restore(cpu, pc); } -#endif =20 rewind_if_in_safe_syscall(puc); =20 --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635616813054270.82338864003384; Sat, 30 Oct 2021 11:00:13 -0700 (PDT) Received: from localhost ([::1]:46844 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgseJ-0006ue-P2 for importer@patchew.org; Sat, 30 Oct 2021 14:00:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57718) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryV-0002Dg-Ak for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:00 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:42669) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryS-00009u-Af for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:16:59 -0400 Received: by mail-pg1-x533.google.com with SMTP id t7so12991214pgl.9 for ; Sat, 30 Oct 2021 10:16:55 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=p8GaNWW3vnRejpH0QBiQY2hh87QfB4bhIFphc+bCE2U=; b=tFHQGAzBSohwn8NtlCyzQcv+8qj2sS17Vbg+fqXl5pidyxn5rtIzOB9bWfIgoSJ7bY NXMzasflqC4s4W1ECEuuKzDLaQROZI70iECFPf/vT+U7s/FoDpSaUWZs97SVtqmxcWuS q2zyNMUYCWOxC+OxS31uUaZthr8LrPcxNV1x2dLvUSuSpEX23EuC5qYkzO8ux2b3E0Cu AorVuFG+mFoxdrEbCI85s0aywvA3FOCBAiWBQtGV9++pmQF/7L+fQ9aBN88MY2qXFJcb 1hb6lZ/02w8M+sKLh7kktiYwVTXAMaK/toY1LutaT2UObd/voMcKeIcbpSplJwGU6IUU iAGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=p8GaNWW3vnRejpH0QBiQY2hh87QfB4bhIFphc+bCE2U=; b=XIm1SSLJ2eHPXnMRFinwn0xw5LNgAPjADPud9eeONB1a56wiWHy4LbJc7XmwO29CXI 1CxV1iTvi+LaMjwZYGdJGhi8A4zXypdjToqd/y6+5pVVVWZ+70YLjwGCU/iM5bsMSQ6O MMVM6WM9/bjKE+85ZLxp9iCJaA4aARAnmqpQMvfHqY0Q1BPN1SNWf5prY2rFgC9wsu9c kjwofluhOKVlktsmkkkNn5ZVQW3PugHkaQYq+5coYes4/O0HoF1bvPjilHNskOB4v3tJ opr02zPFJ+bCPjcwKR+bgWgdPRkUVJDcEpO4rePDUbWPkuA2P433dQa9zXFE6Qnd7eOt YQqQ== X-Gm-Message-State: AOAM530v3k4B+qcjuvuybpMOJwPcINgbcmlHRAT5r4IDsVjQn7RihlfX BGK9h4UXeLxXe3ELcxrLWh09/wHpNMUh4A== X-Google-Smtp-Source: ABdhPJwSGCMK51l8bSst9hVE4c3Iy8ahY+SJoBhRG9IVaLcPKOrGAtAGvB6YghOvl0Yx9Or2UXAnJg== X-Received: by 2002:a63:b145:: with SMTP id g5mr13514504pgp.355.1635614215080; Sat, 30 Oct 2021 10:16:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 19/66] hw/core: Add TCGCPUOps.record_sigsegv Date: Sat, 30 Oct 2021 10:15:48 -0700 Message-Id: <20211030171635.1689530-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616814486100001 Add a new user-only interface for updating cpu state before raising a signal. This will replace tlb_fill for user-only and should result in less boilerplate for each guest. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 6cbe17f2e6..41718b695b 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -111,6 +111,32 @@ struct TCGCPUOps { */ bool (*io_recompile_replay_branch)(CPUState *cpu, const TranslationBlock *tb); +#else + /** + * record_sigsegv: + * @cpu: cpu context + * @addr: faulting guest address + * @access_type: access was read/write/execute + * @maperr: true for invalid page, false for permission fault + * @ra: host pc for unwinding + * + * We are about to raise SIGSEGV with si_code set for @maperr, + * and si_addr set for @addr. Record anything further needed + * for the signal ucontext_t. + * + * If the emulated kernel does not provide anything to the signal + * handler with anything besides the user context registers, and + * the siginfo_t, then this hook need do nothing and may be omitted. + * Otherwise, record the data and return; the caller will raise + * the signal, unwind the cpu state, and return to the main loop. + * + * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided + * so that a "normal" cpu exception can be raised. In this case, + * the signal must be raised by the architecture cpu_loop. + */ + void (*record_sigsegv)(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); #endif /* CONFIG_SOFTMMU */ #endif /* NEED_CPU_H */ =20 --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635616915710525.4359147362097; Sat, 30 Oct 2021 11:01:55 -0700 (PDT) Received: from localhost ([::1]:51376 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsfx-0001Va-I1 for importer@patchew.org; Sat, 30 Oct 2021 14:01:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryY-0002Es-9X for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:02 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:38774) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryU-0000A1-Cg for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:01 -0400 Received: by mail-pj1-x102b.google.com with SMTP id x33-20020a17090a6c2400b001a63ef25836so3498918pjj.3 for ; Sat, 30 Oct 2021 10:16:56 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h74jAt7hxYWJ8vb//ZptaTN1DfaIP6MJ1JsKHfl8Ic0=; b=lIpgKte63/KhxkAmFf9MqF5uMUr5zrAMBdQ/dymnWQ4CcZt4XpfPtuTbQP2MZvthFs uhj591FWmvMXSNwtg5rTWSvLKETXa7RZdlWeoJhYCo2HD0rtNi7AXSSmWbItlOtJuRJt DUdUH70K+4kQhg3Q1AUKS0HUdrwG8T7mWf1DvLSFRGY0bSinpamEk8Sya8WSrWhD7C44 93P43hcfigBmAbx1zs2KG0rzyeD8x/KV6UvFvBXEIHBWNOiUtznbnovTdbNgSwuB45vd OWa4/EAQtDyhJuVdd9GMPWCoAaR7An3T+gkdy7QKLLps/luOGdWT/6yfvBd4GSj+kUDC lIFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h74jAt7hxYWJ8vb//ZptaTN1DfaIP6MJ1JsKHfl8Ic0=; b=xlLwgTNAHnDkQ6zCGQ9FcTvg8OCmWNUOMME6E5gtPH0aAT0HLq7QeP1nSSeYq+j+UZ kDx/68mqQsVBCB5CGI5Iou3fYdqhbhLOZuZR59cF283IzJoaX5BTw4QDIoAg0/AQ6SxF S4pjzsD5F9t3X63WTXvM9Ps5EmP+Ev+wwUzlIdtZJUrGPlGfyJyUFDgxWWMnqixPWRra KaG3k+AePROrpMIDvApsMeW6piXU6kJUn2bhYt5samM4BJhcT8+dtUxPPPwWuN/6cZLY BYiJYYkrv5G+fA3Wprg/zCgdRZYho7CH314e8qTQi5q+qI6/ML7yEKWlIAz3cgRZ12Ej +Psg== X-Gm-Message-State: AOAM533ZwOsttmWbyyJnsiaNIc730jiI98cd5yblOaMsP0yaDSAjnc51 KP30fLwfi5uZLMuDGkVT8d2CXekrWFc1Iw== X-Google-Smtp-Source: ABdhPJzEp334gs5aTkoAICe0YwsBAWwerHJbQ0frSKGaquE1eNxwcHZlse3b5TfVmTUw6cjqGgsA2A== X-Received: by 2002:a17:90b:3a82:: with SMTP id om2mr10784976pjb.228.1635614215994; Sat, 30 Oct 2021 10:16:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 20/66] linux-user: Add cpu_loop_exit_sigsegv Date: Sat, 30 Oct 2021 10:15:49 -0700 Message-Id: <20211030171635.1689530-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616917220100001 This is a new interface to be provided by the os emulator for raising SIGSEGV on fault. Use the new record_sigsegv target hook. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 15 +++++++++++++++ accel/tcg/user-exec.c | 33 ++++++++++++++++++--------------- linux-user/signal.c | 30 ++++++++++++++++++++++-------- 3 files changed, 55 insertions(+), 23 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5dd663c153..f74578500c 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -685,6 +685,21 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_= write); bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, uintptr_t host_pc, abi_ptr guest_addr); =20 +/** + * cpu_loop_exit_sigsegv: + * @cpu: the cpu context + * @addr: the guest address of the fault + * @access_type: access was read/write/execute + * @maperr: true for invalid page, false for permission fault + * @ra: host pc for unwinding + * + * Use the TCGCPUOps hook to record cpu state, do guest operating system + * specific things to raise SIGSEGV, and jump to the main cpu loop. + */ +void QEMU_NORETURN cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); + #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index a0cba61e83..c4f69908e9 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -141,35 +141,38 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, int fault_size, MMUAccessType access_type, bool nonfault, uintptr_t ra) { - int flags; + int acc_flag; + bool maperr; =20 switch (access_type) { case MMU_DATA_STORE: - flags =3D PAGE_WRITE; + acc_flag =3D PAGE_WRITE_ORG; break; case MMU_DATA_LOAD: - flags =3D PAGE_READ; + acc_flag =3D PAGE_READ; break; case MMU_INST_FETCH: - flags =3D PAGE_EXEC; + acc_flag =3D PAGE_EXEC; break; default: g_assert_not_reached(); } =20 - if (!guest_addr_valid_untagged(addr) || - page_check_range(addr, 1, flags) < 0) { - if (nonfault) { - return TLB_INVALID_MASK; - } else { - CPUState *cpu =3D env_cpu(env); - CPUClass *cc =3D CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_type, - MMU_USER_IDX, false, ra); - g_assert_not_reached(); + if (guest_addr_valid_untagged(addr)) { + int page_flags =3D page_get_flags(addr); + if (page_flags & acc_flag) { + return 0; /* success */ } + maperr =3D !(page_flags & PAGE_VALID); + } else { + maperr =3D true; } - return 0; + + if (nonfault) { + return TLB_INVALID_MASK; + } + + cpu_loop_exit_sigsegv(env_cpu(env), addr, access_type, maperr, ra); } =20 int probe_access_flags(CPUArchState *env, target_ulong addr, diff --git a/linux-user/signal.c b/linux-user/signal.c index b816678ba5..135983747d 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -688,9 +688,27 @@ void force_sigsegv(int oldsig) } force_sig(TARGET_SIGSEGV); } - #endif =20 +void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, bool maperr, uintptr= _t ra) +{ + const struct TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; + + if (tcg_ops->record_sigsegv) { + tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); + } else if (tcg_ops->tlb_fill) { + tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, = ra); + g_assert_not_reached(); + } + + force_sig_fault(TARGET_SIGSEGV, + maperr ? TARGET_SEGV_MAPERR : TARGET_SEGV_ACCERR, + addr); + cpu->exception_index =3D EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, ra); +} + /* abort execution with signal */ static void QEMU_NORETURN dump_core_and_abort(int target_sig) { @@ -806,7 +824,7 @@ static void host_signal_handler(int host_sig, siginfo_t= *info, void *puc) access_type =3D adjust_signal_pc(&pc, is_write); =20 if (host_sig =3D=3D SIGSEGV) { - const struct TCGCPUOps *tcg_ops; + bool maperr =3D true; =20 if (info->si_code =3D=3D SEGV_ACCERR && h2g_valid(host_addr)) { /* If this was a write to a TB protected page, restart. */ @@ -821,18 +839,14 @@ static void host_signal_handler(int host_sig, siginfo= _t *info, void *puc) * which means that we may get ACCERR when we want MAPERR. */ if (page_get_flags(guest_addr) & PAGE_VALID) { - /* maperr =3D false; */ + maperr =3D false; } else { info->si_code =3D SEGV_MAPERR; } } =20 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); - - tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; - tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, - MMU_USER_IDX, false, pc); - g_assert_not_reached(); + cpu_loop_exit_sigsegv(cpu, guest_addr, access_type, maperr, pc= ); } else { sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); } --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635617097137970.6415176705807; Sat, 30 Oct 2021 11:04:57 -0700 (PDT) Received: from localhost ([::1]:59940 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsiu-0007Hq-0c for importer@patchew.org; Sat, 30 Oct 2021 14:04:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryW-0002EM-R7 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:02 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:41645) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryU-0000AE-IT for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:00 -0400 Received: by mail-pl1-x635.google.com with SMTP id z11so8908402plg.8 for ; Sat, 30 Oct 2021 10:16:57 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v0FpA57qaJCc2VnO4R+7jKC7WxQwlNYWwLwncqceS+8=; b=ajxdSNDCMeYUdzmn6edXW8Kr7ql2ueVnjF0vHllrdybeZO0yi1aYUxeBb/O2WNx0TI E0NDZQZ99NFr6jbGjGnoPkSLI3vyDHDp2yNoy9Tfh0dxBT7pgwrxSg6JitwhD45aUd8H KKNbj/ccHq/3YBuAlBQCzB8rjTKlkPjZxRXladW/e6VSPX56Wp0iQ6qJ65GLJHPHluht RFRTEmxHfrIBItFDGc5YA9PK5sgf7taNqZlL2VddUAq+EaJqSa4G6vu0pW7mPuaOBq2m a6unUznDe7tVzmYdDoWpuWZrVY7VttN2tSldYebOvq3AxGwCDMftmtKnRPBUFMy0eSUc DVlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v0FpA57qaJCc2VnO4R+7jKC7WxQwlNYWwLwncqceS+8=; b=5D9eMOJ6cA/3j4XeGWXcF37q1jUt8jrdbd9yadeLZerhSlVNtxgeX7Jry/KwYwjjVX zbuu03CGtNcTdZbBQJozym4lZMW7+AOYOdgH8Yi0czOBln0Ecqli7RuiGSquPmPKpVl1 7oiqaE5tNtG+0tAPQ6qk4tYVaaKkjaZJhqk9QRx9LDvx+4yD2IeE78TGL7kc/L2HwUoL R6jSNX0Yej+HnlcH7bKc2EtEwUHyF6BjXBgWxF53es9A+de4414o1SzjK6NLJaQ7J6OY ahbA5gMTtyx3jxmQTGa1KL5U6OT79OSPgWkc5gOYhZevq8ByDS5fI+BJqAXD98R416rH l9xQ== X-Gm-Message-State: AOAM530lR8uYsEuApbRdRv7016IRJiNhJKaNRU+9C0X4L7fM4iUe2IZ8 bgvicOp6LwgAIbSDHGdYonxw/mxDGd2lww== X-Google-Smtp-Source: ABdhPJxNIgOxBS5Q8NVUgKpc7Gc6Yl5E/gOwda9+jVSQghH9Y4xYih4ahv09r2mMWexMEsalIU71wg== X-Received: by 2002:a17:90a:5303:: with SMTP id x3mr25134289pjh.226.1635614216814; Sat, 30 Oct 2021 10:16:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 21/66] target/alpha: Implement alpha_cpu_record_sigsegv Date: Sat, 30 Oct 2021 10:15:50 -0700 Message-Id: <20211030171635.1689530-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635617099001100001 Content-Type: text/plain; charset="utf-8" Record trap_arg{0,1,2} for the linux-user signal frame. Fill in the stores to trap_arg{1,2} that were missing from the previous user-only alpha_cpu_tlb_fill function. Use maperr to simplify computation of trap_arg1. Remove the code for EXCP_MMFAULT from cpu_loop, as that part is now handled by cpu_loop_exit_sigsegv. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/cpu.h | 13 +++++++++---- linux-user/alpha/cpu_loop.c | 8 -------- target/alpha/cpu.c | 6 ++++-- target/alpha/helper.c | 39 ++++++++++++++++++++++++++++++++----- 4 files changed, 47 insertions(+), 19 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 772828cc26..d49cc36d07 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -439,9 +439,6 @@ void alpha_translate_init(void); #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU =20 void alpha_cpu_list(void); -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int); void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); =20 @@ -449,7 +446,15 @@ uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env); void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val); uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg); void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val); -#ifndef CONFIG_USER_ONLY + +#ifdef CONFIG_USER_ONLY +void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr); +#else +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 1b00a81385..4cc8e0a55c 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -54,14 +54,6 @@ void cpu_loop(CPUAlphaState *env) fprintf(stderr, "External interrupt. Exit\n"); exit(EXIT_FAILURE); break; - case EXCP_MMFAULT: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D (page_get_flags(env->trap_arg0) & PAGE_VALID - ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); - info._sifields._sigfault._addr =3D env->trap_arg0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_UNALIGN: info.si_signo =3D TARGET_SIGBUS; info.si_errno =3D 0; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 93e16a2ffb..69f32c3078 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -218,9 +218,11 @@ static const struct SysemuCPUOps alpha_sysemu_ops =3D { =20 static const struct TCGCPUOps alpha_tcg_ops =3D { .initialize =3D alpha_translate_init, - .tlb_fill =3D alpha_cpu_tlb_fill, =20 -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D alpha_cpu_record_sigsegv, +#else + .tlb_fill =3D alpha_cpu_tlb_fill, .cpu_exec_interrupt =3D alpha_cpu_exec_interrupt, .do_interrupt =3D alpha_cpu_do_interrupt, .do_transaction_failed =3D alpha_cpu_do_transaction_failed, diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 81550d9e2f..b7e7f73b15 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -120,15 +120,44 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned = reg, uint64_t val) } =20 #if defined(CONFIG_USER_ONLY) -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { AlphaCPU *cpu =3D ALPHA_CPU(cs); + target_ulong mmcsr, cause; =20 - cs->exception_index =3D EXCP_MMFAULT; + /* Assuming !maperr, infer the missing protection. */ + switch (access_type) { + case MMU_DATA_LOAD: + mmcsr =3D MM_K_FOR; + cause =3D 0; + break; + case MMU_DATA_STORE: + mmcsr =3D MM_K_FOW; + cause =3D 1; + break; + case MMU_INST_FETCH: + mmcsr =3D MM_K_FOE; + cause =3D -1; + break; + default: + g_assert_not_reached(); + } + if (maperr) { + if (address < BIT_ULL(TARGET_VIRT_ADDR_SPACE_BITS - 1)) { + /* Userspace address, therefore page not mapped. */ + mmcsr =3D MM_K_TNV; + } else { + /* Kernel or invalid address. */ + mmcsr =3D MM_K_ACV; + } + } + + /* Record the arguments that PALcode would give to the kernel. */ cpu->env.trap_arg0 =3D address; - cpu_loop_exit_restore(cs, retaddr); + cpu->env.trap_arg1 =3D mmcsr; + cpu->env.trap_arg2 =3D cause; } #else /* Returns the OSF/1 entMM failure indication, or -1 on success. */ --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635615481362336.16058330223143; Sat, 30 Oct 2021 10:38:01 -0700 (PDT) Received: from localhost ([::1]:53534 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsIq-0006Ba-4B for importer@patchew.org; Sat, 30 Oct 2021 13:38:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57756) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryX-0002Ee-7Q for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:02 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:50844) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryV-0000AJ-8J for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:00 -0400 Received: by mail-pj1-x102f.google.com with SMTP id gn3so9425018pjb.0 for ; Sat, 30 Oct 2021 10:16:58 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fofFGJJJzbXM7L3Ibz3JhPAmpo8LElJ1YWB6iIwHWsU=; b=fm7voBt4LmR1MWoGh7sSn58zbwlF2SC5pppux4q31e1/8qO6MYm8s5PzzMFE3gkqvz JpnmG8HMRw60SDiZJEm9EdScJij5PvV9m0IsHl29uNCUVnii7g6eyi8StxY4+3N0azn8 9CGQwegZFX5ECo8mTyKshzzCXnetZo9DKAFSpifaO/qYlNHy0h/4BZUeuM+rlaAhNR0w 3l/tUbb6CN/bMUU478CxJ+MsN0O65cuyKbMFFY1Roegb2Wf8UyoVMtKzujtOdyDTe7U2 Mh8MxtM9vHNJ3+ydHjzIQX/VKfioNuYXyavdtV1uZCbSYibIa7IF7prDJbULt9JDbdTV jXzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fofFGJJJzbXM7L3Ibz3JhPAmpo8LElJ1YWB6iIwHWsU=; b=21gZgq2h1DwrzIwbcm2ZpFN9DUG2odIaZaAz4Ry1VF4py8jFF6kGhnEcNIVeI0bayO AlcJQaW/K7ckvROy4ocatinvqjPbO/oXTp7buI9hwGJweiVQBGToH7Zfc70tteqs5Hzb xsr2OrgFblvPZb0xKxKCOK+qLbVP12JszGtnjT1jEjLblHQHgctNzpXygucAad2Zev1c TG7OYi5JhTf7m46+BmBT/x0WHwdHFTEmfGDUfq4Uqmw8ytoYiS3IVuEqdDOG40/rGVHb kDEjqr0qdu3XmpGJyERAV1lXeMIJvsuSPFQW7zsaPQqVY4IFtDOLlcyO6Cy0Q4kn1Z+D /qbQ== X-Gm-Message-State: AOAM533/RcKYZ5bLNd0+hkAWSdWTMRzdESoEVunAIkCS9XII598e/yQv wiqBVIjltJsohUiXMbpqzwoBRghulkqe2A== X-Google-Smtp-Source: ABdhPJyPCqnXbcvT4LTlb5RbMTg1y3FWQpOGVZT2SMa+l5P19FpjnMX+BwgvnkXP6AsMH+GTGloXww== X-Received: by 2002:a17:90b:fd3:: with SMTP id gd19mr2649234pjb.218.1635614217944; Sat, 30 Oct 2021 10:16:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 22/66] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup Date: Sat, 30 Oct 2021 10:15:51 -0700 Message-Id: <20211030171635.1689530-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635615482401100001 Use the new os interface for raising the exception, rather than calling arm_cpu_tlb_fill directly. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 724175210b..e09b7e46a2 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -84,10 +84,8 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int= ptr_mmu_idx, uintptr_t index; =20 if (!(flags & (ptr_access =3D=3D MMU_DATA_STORE ? PAGE_WRITE_ORG : PAG= E_READ))) { - /* SIGSEGV */ - arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access, - ptr_mmu_idx, false, ra); - g_assert_not_reached(); + cpu_loop_exit_sigsegv(env_cpu(env), ptr, ptr_access, + !(flags & PAGE_VALID), ra); } =20 /* Require both MAP_ANON and PROT_MTE for the page. */ --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635617416760319.4519440763171; Sat, 30 Oct 2021 11:10:16 -0700 (PDT) Received: from localhost ([::1]:40502 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgso3-0004pV-1z for importer@patchew.org; Sat, 30 Oct 2021 14:10:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57816) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryZ-0002GK-Gc for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:04 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:36685) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryV-0000Ad-UN for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:03 -0400 Received: by mail-pj1-x102f.google.com with SMTP id o10-20020a17090a3d4a00b001a6555878a8so1587366pjf.1 for ; Sat, 30 Oct 2021 10:16:59 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1wBL44wFnTfFr75B1K0GW+FHLyxttBDILq0ZVE67hOM=; b=OG3zrhz0UehGCyVvm7AX8lNez8YH9R8/uXDqQW3e5GVZQRQsOBL0V+5RpI6zZ/eE3o 47vq4Ya5xqjK2RkPZon/R4NpK/w4zflzz+kjD7lNr929jxYeQgS03oyIi23NlmN/vvcJ isLP1TUf30tvza8EgLHw+2gZ0aNrByYblVAkBXnSuh385kpTKur8hQ+jBv1NBpvX1qbT lVX5NHEb+1wHJSzt1HVBgg8g1ozTQJYKbXY/TR2zZhY/fFLlBAF6ijF9jCYO5OFADInQ gEFNu/YLTeaA13pEqcrP7Tp8HxsWT06+npJEeIIKjU3PiduIWasOy5w6LeYHsb4/pDjq XG2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1wBL44wFnTfFr75B1K0GW+FHLyxttBDILq0ZVE67hOM=; b=5kHoIxmo0SqXcMtbJrCm7WGpdrahwXHZYlww8V38MV8pT4QBtH+p9KtoxSn6Q6sJIU pswdr+81cFdIwxsICz7RzN02fgkS+30n+A+YKFiIfrJ98vu0M8YtMTQb6kvfz0l7/EkU IEyJKO+xCxnpsQdJeU6BJQ7K2dalYU6m7k3AYC0dsZt4JbENHJRZUxSbRUrb8ErPvMoP pIHInwp0bo0JlvaUfQj926wWkKwIuT4QiEJiKwUUMPprzNKLTwtuPydY1wRDRH4Udu4X U+gQRMeKJkA7utKLBD5Yyb0iMgSEpCFD8dpaa6IGHzAX7WWzl/QeLRsfqzGmp+SKBAqy z/yA== X-Gm-Message-State: AOAM5329TEq3+u+fH+8c2UsxHCZS9nX9NYMO9KFyhnA6L4sBdIhsBIy0 TlcFjzqbgwIvcmvuvZwkUV+IVkAENb0bsQ== X-Google-Smtp-Source: ABdhPJzsJLX4u/TwVcpMNyg3w1lzN1pFoeDzauJOXXXQvYzk6ePnS5I4ja2bmbw8+R5EhsEy1/NLCg== X-Received: by 2002:a17:90a:c85:: with SMTP id v5mr27626756pja.47.1635614218781; Sat, 30 Oct 2021 10:16:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 23/66] target/arm: Implement arm_cpu_record_sigsegv Date: Sat, 30 Oct 2021 10:15:52 -0700 Message-Id: <20211030171635.1689530-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635617418018100001 Content-Type: text/plain; charset="utf-8" Because of the complexity of setting ESR, continue to use arm_deliver_fault. This means we cannot remove the code within cpu_loop that decodes EXCP_DATA_ABORT and EXCP_PREFETCH_ABORT. But using the new hook means that we don't have to do the page_get_flags check manually, and we'll be able to restrict the tlb_fill hook to sysemu later. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 6 ++++++ target/arm/cpu.c | 6 ++++-- target/arm/cpu_tcg.c | 6 ++++-- target/arm/tlb_helper.c | 36 +++++++++++++++++++----------------- 4 files changed, 33 insertions(+), 21 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 3612107ab2..5a7aaf0f51 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -544,9 +544,15 @@ static inline bool arm_extabort_type(MemTxResult resul= t) return result !=3D MEMTX_DECODE_ERROR; } =20 +#ifdef CONFIG_USER_ONLY +void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif =20 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 641a8c2d3d..7a18a58ca0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2031,10 +2031,12 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D= { static const struct TCGCPUOps arm_tcg_ops =3D { .initialize =3D arm_translate_init, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, - .tlb_fill =3D arm_cpu_tlb_fill, .debug_excp_handler =3D arm_debug_excp_handler, =20 -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D arm_cpu_record_sigsegv, +#else + .tlb_fill =3D arm_cpu_tlb_fill, .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, .do_interrupt =3D arm_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 0d5adccf1a..7b3bea2fbb 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -898,10 +898,12 @@ static void pxa270c5_initfn(Object *obj) static const struct TCGCPUOps arm_v7m_tcg_ops =3D { .initialize =3D arm_translate_init, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, - .tlb_fill =3D arm_cpu_tlb_fill, .debug_excp_handler =3D arm_debug_excp_handler, =20 -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D arm_cpu_record_sigsegv, +#else + .tlb_fill =3D arm_cpu_tlb_fill, .cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt, .do_interrupt =3D arm_v7m_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 3107f9823e..dc5860180f 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -147,28 +147,12 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } =20 -#endif /* !defined(CONFIG_USER_ONLY) */ - bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { ARMCPU *cpu =3D ARM_CPU(cs); ARMMMUFaultInfo fi =3D {}; - -#ifdef CONFIG_USER_ONLY - int flags =3D page_get_flags(useronly_clean_ptr(address)); - if (flags & PAGE_VALID) { - fi.type =3D ARMFault_Permission; - } else { - fi.type =3D ARMFault_Translation; - } - fi.level =3D 3; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); -#else hwaddr phys_addr; target_ulong page_size; int prot, ret; @@ -210,5 +194,23 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, cpu_restore_state(cs, retaddr, true); arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); } -#endif } +#else +void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra) +{ + ARMMMUFaultInfo fi =3D { + .type =3D maperr ? ARMFault_Translation : ARMFault_Permission, + .level =3D 3, + }; + ARMCPU *cpu =3D ARM_CPU(cs); + + /* + * We report both ESR and FAR to signal handlers. + * For now, it's easiest to deliver the fault normally. + */ + cpu_restore_state(cs, ra, true); + arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi); +} +#endif /* !defined(CONFIG_USER_ONLY) */ --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635616716642578.3722155390851; Sat, 30 Oct 2021 10:58:36 -0700 (PDT) Received: from localhost ([::1]:42466 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgscl-00040y-Fs for importer@patchew.org; Sat, 30 Oct 2021 13:58:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57790) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryY-0002Eu-GE for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:02 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:39622) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryW-0000Aj-Mc for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:02 -0400 Received: by mail-pf1-x432.google.com with SMTP id b1so8788297pfm.6 for ; Sat, 30 Oct 2021 10:17:00 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LvK67GkX13tDj2L9Y8ql/Gd7bbn2JZgBQ3dF7lXKOxQ=; b=pNymeQbgGb2R9VEmTueam33jv1xHOlvbQplfIeSGzzzpm5Bqh6Qx/ONQUkTzwEBidz VMr3tzm4IDZkegRyXMDD4FUk2RWSvu8pP50ymbU+X4bmfDxVKkdj9PLUeWyFi5NHUaJI RKtFs5c5dfR1wY/6I5mceNx+JWj7XYffQu7tZ9XYUcmobE20r3Qll447of0Fi9VBMvPr rWnESXFLNH3f63ECuIg3GEN/RnKod6YN1/VF6AQWroxOVObgL3QAc7jW0QS0s4wWbf5L 6dYLJHjiVZxCZ6XQuzW40q1fgaTLPwRCNtheu0Umh+X6UsjrbvMxjX1ucWIsas3yYDfw 6inQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LvK67GkX13tDj2L9Y8ql/Gd7bbn2JZgBQ3dF7lXKOxQ=; b=8I/y/PRH6D153FbLTP6cEI15oK3zDGk8SSlXkuUc8IwgKWiDKUu/NmiRPz/5tQQXMR iyYZFs7feGnutLHmZJISyBGZxwLcRawLs+wq27sFU9AauXPMVxG6V83BRbfs1HxbLBtv ETJc+1Nw35hRWS16p51JBXiEqTue5wAy8z7gEWLJK3bvgzrdCp7yzqtFMzQgJ3U1dS5H A2d8HRMDgU0R8SACAXGAtSKxSWigymJJtd5suyMDr2RDTP5w/zu721rK8KAMx8AP/KVN xYX6mNXbcMWrYJGMc5dQvhqTWMsCq2nS/xkK/nq/QdgmYVzRpkaQlhukzkGQ6YbaEYgj Yzow== X-Gm-Message-State: AOAM532EHOVgBqVrgVVZKiCo8CSh1zEWmQDedSsLMZW9eOV5U39kH0pe eP71yDHtZ1gGBeZqBBP3853+LEFQbGuhQQ== X-Google-Smtp-Source: ABdhPJx+9uvUAQKkWwk14WSK7uCeAUOoSmJRRXYEMLnvzGxu/T2ppFCr0NriPs9MUKNLqIPTojEKUQ== X-Received: by 2002:a05:6a00:16d4:b0:44c:22c4:eb88 with SMTP id l20-20020a056a0016d400b0044c22c4eb88mr18348590pfc.75.1635614219448; Sat, 30 Oct 2021 10:16:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 24/66] target/cris: Make cris_cpu_tlb_fill sysemu only Date: Sat, 30 Oct 2021 10:15:53 -0700 Message-Id: <20211030171635.1689530-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616718247100001 The fallback code in cpu_loop_exit_sigsegv is sufficient for cris linux-user. Remove the code from cpu_loop that handled the unnamed 0xaa exception. This makes all of the code in helper.c sysemu only, so remove the ifdefs and move the file to cris_softmmu_ss. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/cris/cpu.h | 8 ++++---- linux-user/cris/cpu_loop.c | 10 ---------- target/cris/cpu.c | 4 ++-- target/cris/helper.c | 18 ------------------ target/cris/meson.build | 7 +++++-- 5 files changed, 11 insertions(+), 36 deletions(-) diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 6603565f83..b445b194ea 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -189,6 +189,10 @@ extern const VMStateDescription vmstate_cris_cpu; void cris_cpu_do_interrupt(CPUState *cpu); void crisv10_cpu_do_interrupt(CPUState *cpu); bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req); + +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #endif =20 void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags); @@ -251,10 +255,6 @@ static inline int cpu_mmu_index (CPUCRISState *env, bo= ol ifetch) return !!(env->pregs[PR_CCS] & U_FLAG); } =20 -bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); - /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0 diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c index b9085619c4..0d5d268609 100644 --- a/linux-user/cris/cpu_loop.c +++ b/linux-user/cris/cpu_loop.c @@ -37,16 +37,6 @@ void cpu_loop(CPUCRISState *env) process_queued_cpu_work(cs); =20 switch (trapnr) { - case 0xaa: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->pregs[PR_EDA]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index c2e7483f5b..ed6c781342 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -205,9 +205,9 @@ static const struct SysemuCPUOps cris_sysemu_ops =3D { =20 static const struct TCGCPUOps crisv10_tcg_ops =3D { .initialize =3D cris_initialize_crisv10_tcg, - .tlb_fill =3D cris_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D cris_cpu_tlb_fill, .cpu_exec_interrupt =3D cris_cpu_exec_interrupt, .do_interrupt =3D crisv10_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ @@ -215,9 +215,9 @@ static const struct TCGCPUOps crisv10_tcg_ops =3D { =20 static const struct TCGCPUOps crisv32_tcg_ops =3D { .initialize =3D cris_initialize_tcg, - .tlb_fill =3D cris_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D cris_cpu_tlb_fill, .cpu_exec_interrupt =3D cris_cpu_exec_interrupt, .do_interrupt =3D cris_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/cris/helper.c b/target/cris/helper.c index 36926faf32..a0d6ecdcd3 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -39,22 +39,6 @@ #define D_LOG(...) do { } while (0) #endif =20 -#if defined(CONFIG_USER_ONLY) - -bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - CRISCPU *cpu =3D CRIS_CPU(cs); - - cs->exception_index =3D 0xaa; - cpu->env.pregs[PR_EDA] =3D address; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - - static void cris_shift_ccs(CPUCRISState *env) { uint32_t ccs; @@ -304,5 +288,3 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) =20 return ret; } - -#endif /* !CONFIG_USER_ONLY */ diff --git a/target/cris/meson.build b/target/cris/meson.build index 67c3793c85..c1e326d950 100644 --- a/target/cris/meson.build +++ b/target/cris/meson.build @@ -2,13 +2,16 @@ cris_ss =3D ss.source_set() cris_ss.add(files( 'cpu.c', 'gdbstub.c', - 'helper.c', 'op_helper.c', 'translate.c', )) =20 cris_softmmu_ss =3D ss.source_set() -cris_softmmu_ss.add(files('mmu.c', 'machine.c')) +cris_softmmu_ss.add(files( + 'helper.c', + 'machine.c', + 'mmu.c', +)) =20 target_arch +=3D {'cris': cris_ss} target_softmmu_arch +=3D {'cris': cris_softmmu_ss} --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.16.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:16:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z8ecs4LTwGjkTaIMjFwaDU18rjRNxTTeFlYdhpfOXR8=; b=LAMJRfu4dQi3C1J44DOR9pDRtXrzeGIGxMVyg2LssK1eCdDLsXhtawTVC6rzzHD35h pgZoc06LIIzAb7WvuRI+jfCT7OM9JTRULe6n7dep3IBhBZByDcc4rTgssCcqhKtMKZdz w4GMHwjJAP0/73KCQZCtmQwtsP90PPMn/3NOLzJJnNcJmKScLVaRVFWEHFSR12820jcq iBDvsaOg8mmg23s7RqFTfb1cTAAs9w31rg9CP52p90zRSiBsZx/qRzaDr9WIafZ+h5an 5bzVKBC5/hXc1iGjl8SfoSAgZvwtIjIcnfmILcDAREzVmoDHo53draGn36njIrZLz3os d6qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z8ecs4LTwGjkTaIMjFwaDU18rjRNxTTeFlYdhpfOXR8=; b=2wmZCyHrZDxbynvbyFl6zJ3v6xQZ5GavSTmvxrcyy2vPYpXYRgYegqv9RFEVcasKhd GebJExW0vLPqgLvU/mTH7xmVy7+zcIGVZksQdeREAId/Z7Eu2srwsRT3/755KV3oFs2q oCeIeBu76QZdU0I0B+IDnCmUN17jtmbxxq8xnXOqle138AIT0H6hlq79oUQvo1SF7ocP 601uSdip8oVaKF9i3TYJJkxym+sGJdTssRj8/Ar7sHlRCuL6nSqsyn4cDP6nN3O+/lzP p6+DruoQdBgoCvR5OqTWjrZG9+8lIRfJkKKPayXdICVDkSpy//0on+kZuVkFYU+W0lgV wyUg== X-Gm-Message-State: AOAM533a8vFcAOQFU8mYiqa4ez/00y4e5pTPGFV+rz2aytTKHwlL60OU 6U46m21nu5oVpv/+baYBkklKLuAzfxPgHg== X-Google-Smtp-Source: ABdhPJwNn7FG60VPLxqW+W6qPffoG/5mAhJAqPU5cRXZ49L8SAT4o8fYbktzUuy3E0fpsU/zq84eVg== X-Received: by 2002:a17:903:1111:b0:13f:d1d7:fb5c with SMTP id n17-20020a170903111100b0013fd1d7fb5cmr16057481plh.47.1635614220318; Sat, 30 Oct 2021 10:17:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 25/66] target/hexagon: Remove hexagon_cpu_tlb_fill Date: Sat, 30 Oct 2021 10:15:54 -0700 Message-Id: <20211030171635.1689530-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Taylor Simpson , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635617683644100001 Content-Type: text/plain; charset="utf-8" The fallback code in cpu_loop_exit_sigsegv is sufficient for hexagon linux-user. Remove the code from cpu_loop that raises SIGSEGV. Reviewed-by: Taylor Simpson Signed-off-by: Richard Henderson --- linux-user/hexagon/cpu_loop.c | 24 +----------------------- target/hexagon/cpu.c | 23 ----------------------- 2 files changed, 1 insertion(+), 46 deletions(-) diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index bee2a9e4ea..6b24cbaba9 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -28,8 +28,7 @@ void cpu_loop(CPUHexagonState *env) { CPUState *cs =3D env_cpu(env); - int trapnr, signum, sigcode; - target_ulong sigaddr; + int trapnr; target_ulong syscallnum; target_ulong ret; =20 @@ -39,10 +38,6 @@ void cpu_loop(CPUHexagonState *env) cpu_exec_end(cs); process_queued_cpu_work(cs); =20 - signum =3D 0; - sigcode =3D 0; - sigaddr =3D 0; - switch (trapnr) { case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ @@ -65,12 +60,6 @@ void cpu_loop(CPUHexagonState *env) env->gpr[0] =3D ret; } break; - case HEX_EXCP_FETCH_NO_UPAGE: - case HEX_EXCP_PRIV_NO_UREAD: - case HEX_EXCP_PRIV_NO_UWRITE: - signum =3D TARGET_SIGSEGV; - sigcode =3D TARGET_SEGV_MAPERR; - break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); break; @@ -79,17 +68,6 @@ void cpu_loop(CPUHexagonState *env) trapnr); exit(EXIT_FAILURE); } - - if (signum) { - target_siginfo_t info =3D { - .si_signo =3D signum, - .si_errno =3D 0, - .si_code =3D sigcode, - ._sifields._sigfault._addr =3D sigaddr - }; - queue_signal(env, info.si_signo, QEMU_SI_KILL, &info); - } - process_pending_signals(env); } } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 3338365c16..160a46a3d5 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -245,34 +245,11 @@ static void hexagon_cpu_init(Object *obj) qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_prope= rty); } =20 -static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ -#ifdef CONFIG_USER_ONLY - switch (access_type) { - case MMU_INST_FETCH: - cs->exception_index =3D HEX_EXCP_FETCH_NO_UPAGE; - break; - case MMU_DATA_LOAD: - cs->exception_index =3D HEX_EXCP_PRIV_NO_UREAD; - break; - case MMU_DATA_STORE: - cs->exception_index =3D HEX_EXCP_PRIV_NO_UWRITE; - break; - } - cpu_loop_exit_restore(cs, retaddr); -#else -#error System mode not implemented for Hexagon -#endif -} - #include "hw/core/tcg-cpu-ops.h" =20 static const struct TCGCPUOps hexagon_tcg_ops =3D { .initialize =3D hexagon_translate_init, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, - .tlb_fill =3D hexagon_tlb_fill, }; =20 static void hexagon_cpu_class_init(ObjectClass *c, void *data) --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635615986053603.7622284623266; Sat, 30 Oct 2021 10:46:26 -0700 (PDT) Received: from localhost ([::1]:33798 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsQy-0003tR-DT for importer@patchew.org; Sat, 30 Oct 2021 13:46:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57834) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgrya-0002GR-S1 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:06 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:33339) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryY-0000BA-CW for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:04 -0400 Received: by mail-pg1-x533.google.com with SMTP id r28so13081721pga.0 for ; Sat, 30 Oct 2021 10:17:01 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.17.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:17:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xDn64Ar0c4NUi8qPBLq+7M9+nijncdxsp88/28xGJnw=; b=f/0whUDhibYy17K8bcV8+efL7HaddSqzK1/4y84g/pcPZiopPaBR+udMzmpHURT4E/ 7RmjbsdtP0BgjurSruMh5gUI2d2PPXN5jS+MEQLYyNnI+JDxx2h5gYSe8x+Sb4hT/CmL y4vpnfS6F0uquj2tUAXJC81V4hSHiJMX1wFkQNcL8+E8H9oNjVuNh/XNvkqzKRLhYRJt ZiJ9PcktOXhD6+0jdQ3zH1eorhOind5XtA3p24ZU8vbl3GQopYtx7XxE2C/PBeFJllUd WV2jxUB0gq44vmVoP0UCfD11v7P4iCNudieuheSvfQ8USou0ycm+QWguXA0awUttIcjR F+sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xDn64Ar0c4NUi8qPBLq+7M9+nijncdxsp88/28xGJnw=; b=12TdBmFPA3hM5rkX/WUJkX4tE3URBfJPIukhjaK/d1QFcXGk8JQz8abrEymw4wLkvH 77gogg4qRhCbmvq/iz1+EEm887hArJk1uvcsbPVSapNiL/1B/OcgKYmgnZ+pzJttEjVF 4Nho+p1U+evBYKMIasSh+Qk+TromcL3aA+FnfVfecapH2pOdnrJF+LnvuNp6W3ogXz78 diNGbrqzvSdsFqH6XOoES8lGTs4ZsGfm1W+qS+asHERMYzsK1iHK8I7CKYl7776zItdr k8LdYp0/7cHtZWbSFb2CgOB3vdcqWo11n5sZQevOEZT0z7/TGDP48iiB8rlNpzT1/q2+ 0Nag== X-Gm-Message-State: AOAM5318Y9FyZCuIX4MPOFv4QNU886ZR5ZKc8uHZamw7e95VYGiYGEho o/ZJ2GdQa8RkMw4zCZa0bpA5PnpBhOfl+w== X-Google-Smtp-Source: ABdhPJwVK9Sck1HSDU3tnXRhhZ+TLu/TvPL4V8ImGy8tSuzQLjllQH1frs98dv6/vZdDKw0w87ZHEg== X-Received: by 2002:a05:6a00:1242:b0:44c:2025:29e3 with SMTP id u2-20020a056a00124200b0044c202529e3mr18509763pfi.59.1635614221123; Sat, 30 Oct 2021 10:17:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 26/66] target/hppa: Make hppa_cpu_tlb_fill sysemu only Date: Sat, 30 Oct 2021 10:15:55 -0700 Message-Id: <20211030171635.1689530-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635615988358100001 Content-Type: text/plain; charset="utf-8" The fallback code in cpu_loop_exit_sigsegv is sufficient for hppa linux-user. Remove the code from cpu_loop that raised SIGSEGV. This makes all of the code in mem_helper.c sysemu only, so remove the ifdefs and move the file to hppa_softmmu_ss. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/hppa/cpu.h | 2 +- linux-user/hppa/cpu_loop.c | 16 ---------------- target/hppa/cpu.c | 2 +- target/hppa/mem_helper.c | 15 --------------- target/hppa/meson.build | 6 ++++-- 5 files changed, 6 insertions(+), 35 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index d3cb7a279f..294fd7297f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -323,10 +323,10 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vad= dr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); +#ifndef CONFIG_USER_ONLY bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -#ifndef CONFIG_USER_ONLY void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 81607a9b27..e0a62deeb9 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -144,22 +144,6 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_f =3D env->gr[31]; env->iaoq_b =3D env->gr[31] + 4; break; - case EXCP_ITLB_MISS: - case EXCP_DTLB_MISS: - case EXCP_NA_ITLB_MISS: - case EXCP_NA_DTLB_MISS: - case EXCP_IMP: - case EXCP_DMP: - case EXCP_DMB: - case EXCP_PAGE_REF: - case EXCP_DMAR: - case EXCP_DMPI: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr =3D env->cr[CR_IOR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_UNALIGN: info.si_signo =3D TARGET_SIGBUS; info.si_errno =3D 0; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 89cba9d7a2..23eb254228 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -145,9 +145,9 @@ static const struct SysemuCPUOps hppa_sysemu_ops =3D { static const struct TCGCPUOps hppa_tcg_ops =3D { .initialize =3D hppa_translate_init, .synchronize_from_tb =3D hppa_cpu_synchronize_from_tb, - .tlb_fill =3D hppa_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D hppa_cpu_tlb_fill, .cpu_exec_interrupt =3D hppa_cpu_exec_interrupt, .do_interrupt =3D hppa_cpu_do_interrupt, .do_unaligned_access =3D hppa_cpu_do_unaligned_access, diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index afc5b56c3e..bf07445cd1 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -24,20 +24,6 @@ #include "hw/core/cpu.h" #include "trace.h" =20 -#ifdef CONFIG_USER_ONLY -bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - HPPACPU *cpu =3D HPPA_CPU(cs); - - /* ??? Test between data page fault and data memory protection trap, - which would affect si_code. */ - cs->exception_index =3D EXCP_DMP; - cpu->env.cr[CR_IOR] =3D address; - cpu_loop_exit_restore(cs, retaddr); -} -#else static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) { int i; @@ -392,4 +378,3 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulon= g vaddr) hppa_tlb_entry *ent =3D hppa_find_tlb(env, vaddr); return ent ? ent->ar_type : -1; } -#endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/meson.build b/target/hppa/meson.build index 8a7ff82efc..021e42a2d0 100644 --- a/target/hppa/meson.build +++ b/target/hppa/meson.build @@ -7,13 +7,15 @@ hppa_ss.add(files( 'gdbstub.c', 'helper.c', 'int_helper.c', - 'mem_helper.c', 'op_helper.c', 'translate.c', )) =20 hppa_softmmu_ss =3D ss.source_set() -hppa_softmmu_ss.add(files('machine.c')) +hppa_softmmu_ss.add(files( + 'machine.c', + 'mem_helper.c', +)) =20 target_arch +=3D {'hppa': hppa_ss} target_softmmu_arch +=3D {'hppa': hppa_softmmu_ss} --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635617513076191.91086252059904; Sat, 30 Oct 2021 11:11:53 -0700 (PDT) Received: from localhost ([::1]:44396 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgspc-0007VB-0K for importer@patchew.org; Sat, 30 Oct 2021 14:11:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryc-0002Gy-Ka for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:08 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:39614) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryZ-0000BN-3j for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:05 -0400 Received: by mail-pj1-x1031.google.com with SMTP id y14-20020a17090a2b4e00b001a5824f4918so6266300pjc.4 for ; Sat, 30 Oct 2021 10:17:02 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.17.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:17:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Bcv7+vrfVWDaxhREKP7oW3QycojCjuZf0xWMtNuZYi8=; b=oH12cz+P2xNgI7+VF4g6HcZ0VT4h9PfGNebvXuhFSA0voxdvW4kQlYOlqEkK+rGAEb 55BNVmh6cqAYTcV2paAl0sDJ7gajSl+ELlXPJratijiAW6B84B2Wmy2jHxeo02mjFRuL he2Xtx1O2/lZZ44m/mHeTdSchfZNWMwll6aOW/AgD/mjRSeb8R7Akg379WH5H8jxEJQU FtPymAtN9PDo4OxbBGc8d4yU2fv+zHo6O5dau80YBNgn1CgOgOMQx03sE5tQEAgYPXXf jHQYrWN/hpD9clq5lkAnRa/wOXIC+v8LCtZBK/wqsuO+YA+1ydVwG57BkgojszscOUeV JAWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Bcv7+vrfVWDaxhREKP7oW3QycojCjuZf0xWMtNuZYi8=; b=ldHOVHZV8XAYWInGVvM9P/nSQHi32lOFyywBpqhL5V5veHu7/LBzsw6hg5F1qo7P9G 9X4WJxMuzM8MPckn4RptmqBHnSgzV0Oh/bqfYCURfd+bWAPdTKsh1JE5MXNjIg+HbY8G DvPSZDgS/NW6FKVV4xh/yAXJJUY6U+SrzI3TwJj5y/gcGYkaZzg+vgxBMBbBMFJvl/vh 9lWoh1gkSkqWnIBpxH3xva/dglSDkxTfpNWy7B/YTCWXJrxct+EsP/5UH4Zf5hngxQxS IWjrjxn5HIlZwxadY89R89RlDcSBqr5wOhwUSmCDFtCk2qR5amt0GK4SksOc4TAVjWFr /E6A== X-Gm-Message-State: AOAM532e1lFuVMNhm9ljqGdE1a07pkILSg3g0UMkfEn5uEQ2ozuGUdd+ Y5l+tJLPaVSqmXbN8wq7pWutTAVTQbsmZQ== X-Google-Smtp-Source: ABdhPJzam3w+9+mtFOCYP86ELbP+srD9ADJF0dL/ZKEq9konX1agKlpJqrVk/BtL9Q9TVp5qsSPfDg== X-Received: by 2002:a17:90b:1bce:: with SMTP id oa14mr18936500pjb.191.1635614221807; Sat, 30 Oct 2021 10:17:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 27/66] target/i386: Implement x86_cpu_record_sigsegv Date: Sat, 30 Oct 2021 10:15:56 -0700 Message-Id: <20211030171635.1689530-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635617514275100001 Record cr2, error_code, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. Use the maperr parameter to properly set PG_ERROR_P_MASK. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/i386/tcg/helper-tcg.h | 6 ++++++ target/i386/tcg/tcg-cpu.c | 3 ++- target/i386/tcg/user/excp_helper.c | 23 +++++++++++++++++------ 3 files changed, 25 insertions(+), 7 deletions(-) diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 60ca09e95e..0a4401e917 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -43,9 +43,15 @@ bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); #endif =20 /* helper.c */ +#ifdef CONFIG_USER_ONLY +void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif =20 void breakpoint_handler(CPUState *cs); =20 diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 3ecfae34cb..6fdfdf9598 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -72,10 +72,11 @@ static const struct TCGCPUOps x86_tcg_ops =3D { .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, .cpu_exec_enter =3D x86_cpu_exec_enter, .cpu_exec_exit =3D x86_cpu_exec_exit, - .tlb_fill =3D x86_cpu_tlb_fill, #ifdef CONFIG_USER_ONLY .fake_user_interrupt =3D x86_cpu_do_interrupt, + .record_sigsegv =3D x86_cpu_record_sigsegv, #else + .tlb_fill =3D x86_cpu_tlb_fill, .do_interrupt =3D x86_cpu_do_interrupt, .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, .debug_excp_handler =3D breakpoint_handler, diff --git a/target/i386/tcg/user/excp_helper.c b/target/i386/tcg/user/excp= _helper.c index a89b5228fd..cd507e2a1b 100644 --- a/target/i386/tcg/user/excp_helper.c +++ b/target/i386/tcg/user/excp_helper.c @@ -22,18 +22,29 @@ #include "exec/exec-all.h" #include "tcg/helper-tcg.h" =20 -bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra) { X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; =20 + /* + * The error_code that hw reports as part of the exception frame + * is copied to linux sigcontext.err. The exception_index is + * copied to linux sigcontext.trapno. Short of inventing a new + * place to store the trapno, we cannot let our caller raise the + * signal and set exception_index to EXCP_INTERRUPT. + */ env->cr[2] =3D addr; - env->error_code =3D (access_type =3D=3D MMU_DATA_STORE) << PG_ERROR_W_= BIT; - env->error_code |=3D PG_ERROR_U_MASK; + env->error_code =3D ((access_type =3D=3D MMU_DATA_STORE) << PG_ERROR_W= _BIT) + | (maperr ? 0 : PG_ERROR_P_MASK) + | PG_ERROR_U_MASK; cs->exception_index =3D EXCP0E_PAGE; + + /* Disable do_interrupt_user. */ env->exception_is_int =3D 0; env->exception_next_eip =3D -1; - cpu_loop_exit_restore(cs, retaddr); + + cpu_loop_exit_restore(cs, ra); } --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635618116859399.49040716225625; Sat, 30 Oct 2021 11:21:56 -0700 (PDT) Received: from localhost ([::1]:60878 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgszL-0002g8-QK for importer@patchew.org; Sat, 30 Oct 2021 14:21:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57862) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryc-0002Gz-Jz for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:08 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:35426) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgrya-0000Bm-5G for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:06 -0400 Received: by mail-pl1-x62c.google.com with SMTP id n18so8929469plc.2 for ; Sat, 30 Oct 2021 10:17:03 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.17.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:17:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/utnMsLyouv7LilvnHYZPxrZ8zRoC/jZ7xS1qGJE894=; b=eD/yScecEPUyvblU1mUFzn3VOT6P33rWW6WhmLY13UXFiIdqs0oj8LxFpEfTQgpam5 p9NEV7sNLM58QjFyrY6dFfNUzFtPfGrFooVVR6h8ynSEnN2TrEqs4iywD93C3ZFBHEQB Rf2NvHGxUj8h/w7+5qrbtw+b4jmyNCtDyZVTrQMKmguF3nALqv8yAJtulrbsAHiO60UL 8H/THup/qXxEs+YsANz2642CN15Ckf7pLJnyH5B1swekLQBxDkxBkOdmZZX15MeAf1Fk QB87TFBe5rLDUxwEK7qco7H/EqV3ZawlSSLYa4/1jVJDrBOinyvuWdVbNeKHYj6HukUm MdFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/utnMsLyouv7LilvnHYZPxrZ8zRoC/jZ7xS1qGJE894=; b=zuZoaF/jK0Tmzk301hzCMdaQS0IU3erIKY6KmJke+GpKjGgW0N9gnOrWaVZBkP2Vm5 PVrSd0lSvBHUd3agRbD7S3ukVQTthlQWNlaNBTF/42R44vBANolWZH74hDJB5eAeQht6 HwNfy6anr5R+ISsJv8ZGnaq46Yf78XjUx+d1NVqsC+961b7Z1vKA3PaN8362ssis4PuB mOsXO4uv0DfymsFbI7pga+uPWvGPqI7etIfSeUWzYgI4iSfVfoayz75676C6U19M7jXI DLIdsGOXvwfOPN1CaMdoWR4Dq6k5fhL7eBv/fgsxmZVlRO6DPLO2PaUSvqyDaB8gFePC to6w== X-Gm-Message-State: AOAM5331CIe4Xj3G/RMAafKVCGIOoQ0ElUtvBsSw8JpLtwQIWsEcHp17 MM6PU2NVwt189aAHvYILa7lRHjxUrCpbEQ== X-Google-Smtp-Source: ABdhPJxySpXd0tT9JPf9cf56+jEirTp/hjpIaY/t7SbNNdzEa6EOPlX4Yj/+Rge+QVlumNXrtZAyOw== X-Received: by 2002:a17:902:c409:b0:140:5a3c:8e99 with SMTP id k9-20020a170902c40900b001405a3c8e99mr15987051plk.37.1635614222893; Sat, 30 Oct 2021 10:17:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 28/66] target/m68k: Make m68k_cpu_tlb_fill sysemu only Date: Sat, 30 Oct 2021 10:15:57 -0700 Message-Id: <20211030171635.1689530-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635618117957100001 The fallback code in cpu_loop_exit_sigsegv is sufficient for m68k linux-user. Remove the code from cpu_loop that handled EXCP_ACCESS. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 10 ---------- target/m68k/cpu.c | 2 +- target/m68k/helper.c | 6 +----- 3 files changed, 2 insertions(+), 16 deletions(-) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index ebf32be78f..790bd558c3 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -90,16 +90,6 @@ void cpu_loop(CPUM68KState *env) case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; - case EXCP_ACCESS: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->mmu.ar; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_DEBUG: info.si_signo =3D TARGET_SIGTRAP; info.si_errno =3D 0; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 66d22d1189..c7aeb7da9c 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -515,9 +515,9 @@ static const struct SysemuCPUOps m68k_sysemu_ops =3D { =20 static const struct TCGCPUOps m68k_tcg_ops =3D { .initialize =3D m68k_tcg_init, - .tlb_fill =3D m68k_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D m68k_cpu_tlb_fill, .cpu_exec_interrupt =3D m68k_cpu_exec_interrupt, .do_interrupt =3D m68k_cpu_do_interrupt, .do_transaction_failed =3D m68k_cpu_transaction_failed, diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 137a3e1a3d..5728e48585 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -978,16 +978,12 @@ void m68k_set_irq_level(M68kCPU *cpu, int level, uint= 8_t vector) } } =20 -#endif - bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType qemu_access_type, int mmu_idx, bool probe, uintptr_t retaddr) { M68kCPU *cpu =3D M68K_CPU(cs); CPUM68KState *env =3D &cpu->env; - -#ifndef CONFIG_USER_ONLY hwaddr physical; int prot; int access_type; @@ -1051,12 +1047,12 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address,= int size, if (!(access_type & ACCESS_STORE)) { env->mmu.ssw |=3D M68K_RW_040; } -#endif =20 cs->exception_index =3D EXCP_ACCESS; env->mmu.ar =3D address; cpu_loop_exit_restore(cs, retaddr); } +#endif /* !CONFIG_USER_ONLY */ =20 uint32_t HELPER(bitrev)(uint32_t x) { --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635617241373617.3016751904077; Sat, 30 Oct 2021 11:07:21 -0700 (PDT) Received: from localhost ([::1]:35614 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgslA-0001au-KE for importer@patchew.org; Sat, 30 Oct 2021 14:07:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57864) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryc-0002HR-Px for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:08 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:33340) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgrya-0000C7-So for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:06 -0400 Received: by mail-pg1-x534.google.com with SMTP id r28so13081772pga.0 for ; Sat, 30 Oct 2021 10:17:04 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.17.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:17:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uBSoYrit32aNGLBOXaD1hzT0A4rXkiN+8LxdOJhc9ag=; b=kd1RSk58ZH1sTKyfBBANuNoWBho0yQcQokREU5EhDAjjwJSXKOhrgYnRILuB6APz8Q HQc1SYJFOleEB6mbgC4G3xXzC3zr5p5Moi7TV8cu6HZjSVKxkBESYVFSw97yDwUgtc6n xkXm+5csEAQueDR3CqMRTVlTelyVeYw8WksRfr1i6eJ75ci/HTjZxatCn5Q0uGMhbYxm b/zIcSRwisw9UdenV+tacKJc1dQUwPEz+G7bJCts2isM7Eqs892sNJx9eKvKqO9GRLRw txbJETS6oGATHH30b2AkHDUPKiLEmijUQvJBFfOF/BT2htnNkz04Uf7vHm60n6uAFod7 W3NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uBSoYrit32aNGLBOXaD1hzT0A4rXkiN+8LxdOJhc9ag=; b=JD5FhJ5b3H7+tsm+uv8yV9X/soowpetwXbumhLCsHtp/6R1PhgbGmeSQ1P+xsXP68d noA4gtsvHuKiu7QJItygtu1oAKXSNr12jMPa37rP+dBQAJaQiDYBPT/azSoZ1FTwkilB F/rr83ISTNIYlMXcOGNgHNFeLBSofeJEWoCnv2POVKcb5W0PjhjRdl4TA1hIMzufuD3Q 4sdGV+KmX+GXhSX77hV4gOcFk+HgR8nLBxeY6CqN+L7iIl7l7ExpldZeBNf9RByiXZD0 BR43y4b6hQwiY4q7tI7ULg4hr5BWsbzO/npfU8fg7w8i2AUWahWQ38VoifI/C210YIt2 Gv0Q== X-Gm-Message-State: AOAM531hOeUUNMVwcT+2PmdmJcvjGE16E7u2E+NZOaSCFIQotoGVzimn oLL3EDsa1y1iRh/O/QgDVnRLkaZkJIWkuA== X-Google-Smtp-Source: ABdhPJyy+kW+HPJJ46XL75B9b4Bf07ygwD29V+7nVaSdSTFwdc98kJsXIwOZTrtElx5wNWpDwqMouw== X-Received: by 2002:aa7:83cd:0:b0:480:9e79:fae5 with SMTP id j13-20020aa783cd000000b004809e79fae5mr3202713pfn.42.1635614223696; Sat, 30 Oct 2021 10:17:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 29/66] target/microblaze: Make mb_cpu_tlb_fill sysemu only Date: Sat, 30 Oct 2021 10:15:58 -0700 Message-Id: <20211030171635.1689530-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635617242310100001 Content-Type: text/plain; charset="utf-8" The fallback code in cpu_loop_exit_sigsegv is sufficient for microblaze linux-user. Remove the code from cpu_loop that handled the unnamed 0xaa exception. Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/microblaze/cpu.h | 8 ++++---- linux-user/microblaze/cpu_loop.c | 10 ---------- target/microblaze/cpu.c | 2 +- target/microblaze/helper.c | 13 +------------ 4 files changed, 6 insertions(+), 27 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b7a848bbae..e9cd0b88de 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -394,10 +394,6 @@ void mb_tcg_init(void); #define MMU_USER_IDX 2 /* See NB_MMU_MODES further up the file. */ =20 -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); - typedef CPUMBState CPUArchState; typedef MicroBlazeCPU ArchCPU; =20 @@ -415,6 +411,10 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *en= v, target_ulong *pc, } =20 #if !defined(CONFIG_USER_ONLY) +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_l= oop.c index 52222eb93f..a94467dd2d 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -37,16 +37,6 @@ void cpu_loop(CPUMBState *env) process_queued_cpu_work(cs); =20 switch (trapnr) { - case 0xaa: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D 0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 15db277925..b9c888b87e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -365,9 +365,9 @@ static const struct SysemuCPUOps mb_sysemu_ops =3D { static const struct TCGCPUOps mb_tcg_ops =3D { .initialize =3D mb_tcg_init, .synchronize_from_tb =3D mb_cpu_synchronize_from_tb, - .tlb_fill =3D mb_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D mb_cpu_tlb_fill, .cpu_exec_interrupt =3D mb_cpu_exec_interrupt, .do_interrupt =3D mb_cpu_do_interrupt, .do_transaction_failed =3D mb_cpu_transaction_failed, diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index dd2aecd1d5..a607fe68e5 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -24,18 +24,7 @@ #include "qemu/host-utils.h" #include "exec/log.h" =20 -#if defined(CONFIG_USER_ONLY) - -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - cs->exception_index =3D 0xaa; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - +#ifndef CONFIG_USER_ONLY static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu, MMUAccessType access_type) { --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635617833770505.2931480247013; Sat, 30 Oct 2021 11:17:13 -0700 (PDT) Received: from localhost ([::1]:53012 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsum-00052A-Lw for importer@patchew.org; Sat, 30 Oct 2021 14:17:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57938) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryg-0002Hs-5k for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:10 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:35784) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryc-0000CL-B8 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:08 -0400 Received: by mail-pj1-x1036.google.com with SMTP id n11-20020a17090a2bcb00b001a1e7a0a6a6so13110067pje.0 for ; Sat, 30 Oct 2021 10:17:05 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.17.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:17:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ap2DHedkoq+uxK6WhzWLDOfP9mxx1Wp6apyTQWx8z3U=; b=zbAF9M/YKxCCaI5YonECC2S/W9AU3audRCK0j+KOk80NjwN21ZaJB0T2J5zMYQBHmr g8ggb+JpKAx0+Olksq8OKUMkjgajPXwG1DGVxPBdQ8KVUL/B49n/QL9vWsCjKQZwhrTz C8EY+s8LaH/Uh+S7y7hUOUxFmpnbeYdRVLRYMkRWoYta65uuGp4wlMhmsd8FFdxcRG6U xLnqkmbbaNXB5gz8ItgAF3nV6eGJj3Sg1wBXZcabPY07zkpPoeyY2ehhtu/cM+U6qSjx QPF2VfaB4GW8Tc+EPztSdkCVvT5gDWmuBYD+3BUR5L+7riZxXvQtsnluzw5X3c4WY0rt 5PpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ap2DHedkoq+uxK6WhzWLDOfP9mxx1Wp6apyTQWx8z3U=; b=Tx9veVZJprjo46w4/beI4/PvE07hY5E5WrZJqkUOAiI4Ry6KCYUwNiEuDG004sERUg 1o1A4lHWZ7GHzlcPMsUBfjOAwBJpQ6/rpcs1xIKT/Q/x2TL7HypBY2kR/XuK1WL2DFq8 j543IbnDjQBYmWLDbYyGtbqCmu3fZiH9aI7Apy8a4/1PcMNJb5jnNRVGLLgxQ0A2uWmf Tw5Eoa0H+o945YsQpqaZlvy9mqDVd6Mqii0Yknb6XPKStwoGgCxRo6VNss1q7MiS0mJU Of/YATDz1Ji0iAPQeT+FPJqg0ENzY3kajZzK19I6nBwPgOozBjZq/4XCu400cYa7tLiw u7DQ== X-Gm-Message-State: AOAM532glnk15mzdkUy+tAIu4mcJqcziqq6z9xQAaYBsa+yhlxKFA5uz S9h4ws5PsjIwdvkgKG3FG30qqVDptYGyKg== X-Google-Smtp-Source: ABdhPJw5VjLewtlX3w/Wc61Df8g25OII5OylA5stHiiNKoK/DH99EyLByaHX02UYcamxF2a2dr3xIw== X-Received: by 2002:a17:90a:4e42:: with SMTP id t2mr19211349pjl.108.1635614224716; Sat, 30 Oct 2021 10:17:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 30/66] target/mips: Make mips_cpu_tlb_fill sysemu only Date: Sat, 30 Oct 2021 10:15:59 -0700 Message-Id: <20211030171635.1689530-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635617835059100001 The fallback code in cpu_loop_exit_sigsegv is sufficient for mips linux-user. This means we can remove tcg/user/tlb_helper.c entirely. Remove the code from cpu_loop that raised SIGSEGV. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/mips/tcg/tcg-internal.h | 7 ++-- linux-user/mips/cpu_loop.c | 11 ------ target/mips/cpu.c | 2 +- target/mips/tcg/user/tlb_helper.c | 59 ------------------------------- target/mips/tcg/meson.build | 3 -- target/mips/tcg/user/meson.build | 3 -- 6 files changed, 5 insertions(+), 80 deletions(-) delete mode 100644 target/mips/tcg/user/tlb_helper.c delete mode 100644 target/mips/tcg/user/meson.build diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index bad3deb611..466768aec4 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -18,9 +18,6 @@ void mips_tcg_init(void); =20 void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb= ); -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) QEMU_NORETURN; @@ -60,6 +57,10 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr= physaddr, MemTxResult response, uintptr_t retadd= r); void cpu_mips_tlb_flush(CPUMIPSState *env); =20 +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + #endif /* !CONFIG_USER_ONLY */ =20 #endif diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index cb03fb066b..b735c99a24 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -158,17 +158,6 @@ done_syscall: } env->active_tc.gpr[2] =3D ret; break; - case EXCP_TLBL: - case EXCP_TLBS: - case EXCP_AdEL: - case EXCP_AdES: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->CP0_BadVAddr; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_CpU: case EXCP_RI: info.si_signo =3D TARGET_SIGILL; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 00e0c55d0e..4aae23934b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -539,9 +539,9 @@ static const struct SysemuCPUOps mips_sysemu_ops =3D { static const struct TCGCPUOps mips_tcg_ops =3D { .initialize =3D mips_tcg_init, .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, - .tlb_fill =3D mips_cpu_tlb_fill, =20 #if !defined(CONFIG_USER_ONLY) + .tlb_fill =3D mips_cpu_tlb_fill, .cpu_exec_interrupt =3D mips_cpu_exec_interrupt, .do_interrupt =3D mips_cpu_do_interrupt, .do_transaction_failed =3D mips_cpu_do_transaction_failed, diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_h= elper.c deleted file mode 100644 index 210c6d529e..0000000000 --- a/target/mips/tcg/user/tlb_helper.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * MIPS TLB (Translation lookaside buffer) helpers. - * - * Copyright (c) 2004-2005 Jocelyn Mayer - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ -#include "qemu/osdep.h" - -#include "cpu.h" -#include "exec/exec-all.h" -#include "internal.h" - -static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type) -{ - CPUState *cs =3D env_cpu(env); - - env->error_code =3D 0; - if (access_type =3D=3D MMU_INST_FETCH) { - env->error_code |=3D EXCP_INST_NOTAVAIL; - } - - /* Reference to kernel address from user mode or supervisor mode */ - /* Reference to supervisor address from user mode */ - if (access_type =3D=3D MMU_DATA_STORE) { - cs->exception_index =3D EXCP_AdES; - } else { - cs->exception_index =3D EXCP_AdEL; - } - - /* Raise exception */ - if (!(env->hflags & MIPS_HFLAG_DM)) { - env->CP0_BadVAddr =3D address; - } -} - -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - /* data access */ - raise_mmu_exception(env, address, access_type); - do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); -} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 8f6f7508b6..98003779ae 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -28,9 +28,6 @@ mips_ss.add(when: 'TARGET_MIPS64', if_true: files( 'mxu_translate.c', )) =20 -if have_user - subdir('user') -endif if have_system subdir('sysemu') endif diff --git a/target/mips/tcg/user/meson.build b/target/mips/tcg/user/meson.= build deleted file mode 100644 index 79badcd321..0000000000 --- a/target/mips/tcg/user/meson.build +++ /dev/null @@ -1,3 +0,0 @@ -mips_user_ss.add(files( - 'tlb_helper.c', -)) --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635617973680572.616077020263; Sat, 30 Oct 2021 11:19:33 -0700 (PDT) Received: from localhost ([::1]:57490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsx2-00088K-LD for importer@patchew.org; Sat, 30 Oct 2021 14:19:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57910) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgrye-0002Ha-Ie for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:10 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:38665) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryd-0000CS-2M for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:08 -0400 Received: by mail-pf1-x434.google.com with SMTP id l1so5877141pfu.5 for ; Sat, 30 Oct 2021 10:17:06 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.17.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:17:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zhmoQq400LN3ckB+F14vIMLu76bali80G5XXiJl040k=; b=bytSKraKSabTEwyj0IjM65jDl1g6qC4xLDbk+wEPfhLA8vBgOD7A8pU9tewfr0FMOS /MDpUj7zJOB1DMM/ALteRrclPQc8pb2YHMIgzxK/nCJLDX6w1yS/zPdIhZR+Ledft+FQ Bx302SrxDiAVvpu2AfSmknMLTxsfGbXxMa3pND4FUEV79niQh0JllMUF07fN3PG/QaHN Oh4nXrhhz3YJkGdTmWDmcOY9qJrwRwhxrs1kWu7wQmVqVWWyYWPAJesPix7v826Bftk8 PyyZJibrCxzqVX60YpdYa0dffdf28Qptn30ubVgQiBcUxWQueLHpc+85yBttF5Tjpvkl 5tkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zhmoQq400LN3ckB+F14vIMLu76bali80G5XXiJl040k=; b=1Ui7Uu03wM9EKhrxVQ3wqhJEXU3N8CrlWyBvniLRdMXTtHgJlLkmuQrBXzfZRfQD18 HjzUydq6sNXO8tYh+HHzEj9ipCBib+tftTnte7a4WRAvQl1sdkqGc+LyIkHGNfGG+WMV uvUU81aR+Y+Dh3PZi/Ve2ytZqjGpgGPgwlMcnPSGLmxSxAR5slOvnduBd07fqXPCXCHd jO1rbArIQsV5Xp6pgUnneFKWxMw+hBoIrytLG2ZqZcskQ5q560SM53i+EKNROk5iIv3m YO4nZNIWf9UOXECwEsnXcjWKIBRdLKxLucqAmALKkmlpQZV7I/3PG/AC0Q1WaI4X5KNc e2gw== X-Gm-Message-State: AOAM530wRSaAB7PPWL05x6kCzJKsURMicUWTxNHsp/tIg6ep9uP5WzLE zdeE0Q5ztd7G/0IcrSU/ZB3XmAeZ9/yt4w== X-Google-Smtp-Source: ABdhPJz7LE7tOukFfQdrHcn9TbZwra3O7Ihe3lZtQ6lESbFYhAm61e1iEhoAh92c4BQ5gZsOcPw8nw== X-Received: by 2002:a05:6a00:a23:b0:43d:e856:a3d4 with SMTP id p35-20020a056a000a2300b0043de856a3d4mr18377721pfh.17.1635614225417; Sat, 30 Oct 2021 10:17:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 31/66] target/nios2: Implement nios2_cpu_record_sigsegv Date: Sat, 30 Oct 2021 10:16:00 -0700 Message-Id: <20211030171635.1689530-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635617975568100001 Because the linux-user kuser page handling is currently implemented by detecting magic addresses in the unnamed 0xaa trap, we cannot simply remove nios2_cpu_tlb_fill and rely on the fallback code. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 6 ++++++ target/nios2/cpu.c | 6 ++++-- target/nios2/helper.c | 7 ++++--- 3 files changed, 14 insertions(+), 5 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index a80587338a..1a69ed7a49 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -218,9 +218,15 @@ static inline int cpu_mmu_index(CPUNios2State *env, bo= ol ifetch) MMU_SUPERVISOR_IDX; } =20 +#ifdef CONFIG_USER_ONLY +void nios2_cpu_record_sigsegv(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif =20 static inline int cpu_interrupts_enabled(CPUNios2State *env) { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 58ecd27d75..4cade61e93 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -216,9 +216,11 @@ static const struct SysemuCPUOps nios2_sysemu_ops =3D { =20 static const struct TCGCPUOps nios2_tcg_ops =3D { .initialize =3D nios2_tcg_init, - .tlb_fill =3D nios2_cpu_tlb_fill, =20 -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D nios2_cpu_record_sigsegv, +#else + .tlb_fill =3D nios2_cpu_tlb_fill, .cpu_exec_interrupt =3D nios2_cpu_exec_interrupt, .do_interrupt =3D nios2_cpu_do_interrupt, .do_unaligned_access =3D nios2_cpu_do_unaligned_access, diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 53be8398e9..e5c98650e1 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -38,10 +38,11 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[R_EA] =3D env->regs[R_PC] + 4; } =20 -bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { + /* FIXME: Disentangle kuser page from linux-user sigsegv handling. */ cs->exception_index =3D 0xaa; cpu_loop_exit_restore(cs, retaddr); } --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163561661278686.42190159951883; Sat, 30 Oct 2021 10:56:52 -0700 (PDT) Received: from localhost ([::1]:37504 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsb5-0000gd-M0 for importer@patchew.org; Sat, 30 Oct 2021 13:56:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57940) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryg-0002Ht-68 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:10 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:50848) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryd-0000Ch-CQ for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:09 -0400 Received: by mail-pj1-x1033.google.com with SMTP id gn3so9425142pjb.0 for ; Sat, 30 Oct 2021 10:17:06 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.17.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:17:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OmzSkk+8uZ7WQNpgJweNybw+HfMXuLaYRrksniy1sko=; b=tuoQPu0Y+e7m1SvdA1gP00pMkLWFBRULTMvJjHhuVyFL6Cfmh8WZDw1hRTsD2H/fgv qNaMLEsPaw02u09zaLTa1t5O7wdZISOqQQ9TZ9F+1SPUcL8zBWmXb6w1o8KE9SEGjBdM DmaSAaX65AbaiTrevca9odLdwSyXQWfs3prD8Ufl2FwO4xqtIc0N0hykaWKGhMeejS7Z wVstOJ9QrZkyeC/e95pSuyMFoAo19pircShNSPs3zWXl4+ITFXRGxRzX3qt6cF4TlmwW 0WkUrfwPNoulxtU4uPPLudvnfs05/pywAtbHjA6wdlz+aAmbutm7G4AEQec9yebCgQ/w 3E6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OmzSkk+8uZ7WQNpgJweNybw+HfMXuLaYRrksniy1sko=; b=PGN6LAHOfM1w+UbbP13fDcL0oE5L0Areec7Ywk7z/ibKbERksCY9d/P8TTOciWA73U +Un3T+tTwHbGBUbq1rLv8eoNQWLVPF89dZKutB3s+NS9EPzMfMO28xGvJDCiG1Xnl0y3 PscLLEdv7hWKUyUJdQvdIF8L7AEeaO6WVnb2j14biGrFDdCUuphvxK4oZ5C1mnTMDvkc bWoY+gQzDUBIIxu0VrAS+lJgNxvMGFLID/GroAZfjmL4X5yIJd5CuY/4u5BqDzISj2a/ YEBP2jh63xzZTqh+n550bdCLsGSunsBmmhGaEJr3UfkaXQ9GMPzlgmeJbNjexhKb5Pno ACoA== X-Gm-Message-State: AOAM531KqlhlWDGq8SmOLyVQPxTh1w822XTzS5XaLp+hech0NOElsLe1 yymuklmJB6Y1j46uOZc0JR0kmq29cHbXUA== X-Google-Smtp-Source: ABdhPJwUXaT5PwRqkLIkBQSPVAWlF6KxxD9a56NoGjqQUlYg1A0lSL0dpa3E/QkZldl0j772Y1dW2w== X-Received: by 2002:a17:90a:928a:: with SMTP id n10mr27076997pjo.128.1635614226168; Sat, 30 Oct 2021 10:17:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 32/66] linux-user/openrisc: Abort for EXCP_RANGE, EXCP_FPE Date: Sat, 30 Oct 2021 10:16:01 -0700 Message-Id: <20211030171635.1689530-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616615211100001 Content-Type: text/plain; charset="utf-8" QEMU does not allow the system control bits for either exception to be enabled in linux-user, therefore both exceptions are dead code. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- linux-user/openrisc/cpu_loop.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index f6360db47c..10b7147f68 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -56,7 +56,6 @@ void cpu_loop(CPUOpenRISCState *env) break; case EXCP_DPF: case EXCP_IPF: - case EXCP_RANGE: info.si_signo =3D TARGET_SIGSEGV; info.si_errno =3D 0; info.si_code =3D TARGET_SEGV_MAPERR; @@ -77,13 +76,6 @@ void cpu_loop(CPUOpenRISCState *env) info._sifields._sigfault._addr =3D env->pc; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case EXCP_FPE: - info.si_signo =3D TARGET_SIGFPE; - info.si_errno =3D 0; - info.si_code =3D 0; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_INTERRUPT: /* We processed the pending cpu work above. */ break; @@ -96,6 +88,15 @@ void cpu_loop(CPUOpenRISCState *env) case EXCP_ATOMIC: cpu_exec_step_atomic(cs); break; + case EXCP_RANGE: + /* Requires SR.OVE set, which linux-user won't do. */ + cpu_abort(cs, "Unexpected RANGE exception"); + case EXCP_FPE: + /* + * Requires FPSCR.FPEE set. Writes to FPSCR from usermode not + * yet enabled in kernel ABI, so linux-user does not either. + */ + cpu_abort(cs, "Unexpected FPE exception"); default: g_assert_not_reached(); } --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635616248014984.3360327014593; Sat, 30 Oct 2021 10:50:48 -0700 (PDT) Received: from localhost ([::1]:42134 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsVB-0001Q4-Uh for importer@patchew.org; Sat, 30 Oct 2021 13:50:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57944) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryg-0002Hv-E2 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:10 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:45793) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgrye-0000Cp-CO for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:10 -0400 Received: by mail-pg1-x533.google.com with SMTP id f5so12974662pgc.12 for ; Sat, 30 Oct 2021 10:17:07 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.17.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:17:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pnbVDz2F7bl2MnMZvXAf7/LYYOvOlpdsDMsaNKSumSw=; b=cA6sp4tlc2EsLFWa9Yb7uYpXg0ZUzXgMalSCD/Ip8R0I91eTjvan41jDcSVK5pqtRI WDWYPtUJqnLC873edgyw9tSKK5C2b8oRKm+A3MR6/j8Xds9m+zJoHnnJZOr1CHl7rk3T wLFvCrv2l4LKgZipfijavv9R9U+7nTy6kzCpTBCarw9mWsMinJB453pN0pilWe+FA7ds kpwtHAjxqqEHIR2/P6etKqrMKXc3nCHDoD7LkLyUCTE0z6YiYLIZ7UBiPUFc2DXI9cxA 6dz2IdRI6Ko/iVNIWTtbAhWzg+CJkz63z3p/ECeICbIaWgoW6+udtCZKOm6VUWtBYmRP Ozgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pnbVDz2F7bl2MnMZvXAf7/LYYOvOlpdsDMsaNKSumSw=; b=7LdUdhrOalvTMBIlK8o3RNL3TPSbppoPrnjFDQ9SzB+qoju9zmBmYewDumsqHbghu2 vrKbRAizGI3jxcNXXpExiyg8H7jsK4PMcOigJT4ivGzUZD6UYN1QJjO6vsM8DDGY85bR nMGckUJG53tXcVq5an5FvDi9Pe3lIINgqVaGbgtDsJ6xUUPjSL2wAvW7QBg35mNCb1h5 +wGyBK0AXooHVt7XwvWu8ETW5zdAM4iHYq7K+KFdT5u6HjP9YODqKr0v/a3xVzp1wSqS GkWFFC7fBKmpVqHowMW/HtGci/2gRE8gJWvowgB4WTZ6iOY802LS+gmpgW14u5Hiotbl 6uNw== X-Gm-Message-State: AOAM5333prWlj0DOLFhvh+eUs0vEzyQNTjw7m9FBvLqchG2dX+UGAAoS RmGvF2TsZBSqEsA0KFLpa/Kp0u7kbuC/pQ== X-Google-Smtp-Source: ABdhPJzo0a+fNfojpafmmkpgkkOzdx1tOmReVGk632ReSqse9nQgq0DRNBHgMne68xpCMb2hwLJd7w== X-Received: by 2002:a62:e514:0:b0:47c:12f6:3aae with SMTP id n20-20020a62e514000000b0047c12f63aaemr18607429pff.26.1635614227198; Sat, 30 Oct 2021 10:17:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 33/66] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only Date: Sat, 30 Oct 2021 10:16:02 -0700 Message-Id: <20211030171635.1689530-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616249612100001 The fallback code in cpu_loop_exit_sigsegv is sufficient for openrisc linux-user. This makes all of the code in mmu.c sysemu only, so remove the ifdefs and move the file to openrisc_softmmu_ss. Remove the code from cpu_loop that handled EXCP_DPF. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 7 ++++--- linux-user/openrisc/cpu_loop.c | 8 -------- target/openrisc/cpu.c | 2 +- target/openrisc/mmu.c | 9 --------- target/openrisc/meson.build | 2 +- 5 files changed, 6 insertions(+), 22 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 187a4a114e..ee069b080c 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -317,14 +317,15 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu= , vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg= ); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); -bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); int print_insn_or1k(bfd_vma addr, disassemble_info *info); =20 #define cpu_list cpu_openrisc_list =20 #ifndef CONFIG_USER_ONLY +bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + extern const VMStateDescription vmstate_openrisc_cpu; =20 void openrisc_cpu_do_interrupt(CPUState *cpu); diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index 10b7147f68..3cfdbbf037 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -54,14 +54,6 @@ void cpu_loop(CPUOpenRISCState *env) cpu_set_gpr(env, 11, ret); } break; - case EXCP_DPF: - case EXCP_IPF: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_ALIGN: info.si_signo =3D TARGET_SIGBUS; info.si_errno =3D 0; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 27cb04152f..dfbafc5236 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -186,9 +186,9 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { =20 static const struct TCGCPUOps openrisc_tcg_ops =3D { .initialize =3D openrisc_translate_init, - .tlb_fill =3D openrisc_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D openrisc_cpu_tlb_fill, .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, .do_interrupt =3D openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 94df8c7bef..e561ef245b 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -23,11 +23,8 @@ #include "exec/exec-all.h" #include "exec/gdbstub.h" #include "qemu/host-utils.h" -#ifndef CONFIG_USER_ONLY #include "hw/loader.h" -#endif =20 -#ifndef CONFIG_USER_ONLY static inline void get_phys_nommu(hwaddr *phys_addr, int *prot, target_ulong address) { @@ -94,7 +91,6 @@ static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_ad= dr, int *prot, return need & PAGE_EXEC ? EXCP_ITLBMISS : EXCP_DTLBMISS; } } -#endif =20 static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, int exception) @@ -112,8 +108,6 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, in= t size, { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); int excp =3D EXCP_DPF; - -#ifndef CONFIG_USER_ONLY int prot; hwaddr phys_addr; =20 @@ -138,13 +132,11 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, = int size, if (probe) { return false; } -#endif =20 raise_mmu_exception(cpu, addr, excp); cpu_loop_exit_restore(cs, retaddr); } =20 -#ifndef CONFIG_USER_ONLY hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); @@ -177,4 +169,3 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, v= addr addr) return phys_addr; } } -#endif diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build index e445dec4a0..84322086ec 100644 --- a/target/openrisc/meson.build +++ b/target/openrisc/meson.build @@ -10,7 +10,6 @@ openrisc_ss.add(files( 'fpu_helper.c', 'gdbstub.c', 'interrupt_helper.c', - 'mmu.c', 'sys_helper.c', 'translate.c', )) @@ -19,6 +18,7 @@ openrisc_softmmu_ss =3D ss.source_set() openrisc_softmmu_ss.add(files( 'interrupt.c', 'machine.c', + 'mmu.c', )) =20 target_arch +=3D {'openrisc': openrisc_ss} --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635616369192619.4191287546515; Sat, 30 Oct 2021 10:52:49 -0700 (PDT) Received: from localhost ([::1]:50510 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsXA-0007Bf-6n for importer@patchew.org; Sat, 30 Oct 2021 13:52:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57974) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryi-0002K1-Hs for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:13 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:46791) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryf-0000DR-Te for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:11 -0400 Received: by mail-pg1-x529.google.com with SMTP id m21so12952887pgu.13 for ; Sat, 30 Oct 2021 10:17:08 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.17.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:17:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b7jpFgMMciMmW9Xl8VdlfSERFh4gLfLYDvd7byDKhQQ=; b=bmggfLRWPCJlTliDYIwBF8AYW0VkvebmqgGIIqytjKXy3KZlUkUvhBwyV3DAeFF3Ux 6zZRRoW/foO7p51WiwKTvH9lv0Gq4w3desbgQDwjyv1BPkX7lPWLQw5exHwH/stxrCOg qVYym6y9m7K1ibCV12ln0gntrzj7gJPyqHd64KeDun8I8icAcMSMBOa0b+9SLTW6A+OW h/p2auyDhFj41cVZTvETvNtaaBGhwZOJY6G7N1zr8igrHRKPRywOyFDh2RxAHpIMLOJP qEfwajpBMsb2y26V6PJsRojOjL8uNB5imsn5l5wFQMu3gihQ8POZAa0QvDyFapx4UT7I uvTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b7jpFgMMciMmW9Xl8VdlfSERFh4gLfLYDvd7byDKhQQ=; b=Hbaa94Dg47HSETowMzBWQPCVNWaLmC4Djah17x8OQ2cFvgTPr9Fwmj0zFvOlta5dCj Xnd+Qo9SfpWyya7Awd8O60kBJuwbBO2m0Z28HECPZh0DNdctk4IMqacGFqKbDuAicGTP lsaJv6ixmkIu2Jb74P+NDO9UWEnsdPH+MHeLeptPnvDNRdmrtsmzASJBUUK2WWOgQjIa 045NI7ifP/GzEvGTw/qxeE0wLhzkvppDXmdOq+tm7j9WrMITcmsdUBr3RLmnKEioUMIs BbH3nzHPDGFGSMskL2axukGXwpVXUF3NMquLRrflI0wcT6yXSQYFyurTgAmHjdKAkj9T hJeg== X-Gm-Message-State: AOAM530VRkk9GZTZMTSeDdVu39ablvJhA1+R9u0aC5D/LueDQkxFVYrj WPLP8v9CLVxEHD4cVXg3LuXQBssOKpWsTw== X-Google-Smtp-Source: ABdhPJzRHoczupkHll1mbPl1t+KPExVH+zlLmGLOXS4YVz6n4UINrdIgpT3r3h82s5mi/TE0O/EBPw== X-Received: by 2002:a05:6a00:148c:b0:47c:1776:3599 with SMTP id v12-20020a056a00148c00b0047c17763599mr18320750pfu.32.1635614227940; Sat, 30 Oct 2021 10:17:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 34/66] target/ppc: Implement ppc_cpu_record_sigsegv Date: Sat, 30 Oct 2021 10:16:03 -0700 Message-Id: <20211030171635.1689530-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616370366100001 Record DAR, DSISR, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. This is exactly what the user-mode ppc_cpu_tlb_fill does, so simply rename it as ppc_cpu_record_sigsegv. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 3 --- target/ppc/internal.h | 9 +++++++++ target/ppc/cpu_init.c | 6 ++++-- target/ppc/user_only_helper.c | 15 +++++++++++---- 4 files changed, 24 insertions(+), 9 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 0472ec9154..e946da5f3a 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1302,9 +1302,6 @@ extern const VMStateDescription vmstate_ppc_cpu; =20 /*************************************************************************= ****/ void ppc_translate_init(void); -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); =20 #if !defined(CONFIG_USER_ONLY) void ppc_store_sdr1(CPUPPCState *env, target_ulong value); diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 55284369f5..339974b7d8 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -283,5 +283,14 @@ static inline void pte_invalidate(target_ulong *pte0) #define PTE_PTEM_MASK 0x7FFFFFBF #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) =20 +#ifdef CONFIG_USER_ONLY +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#endif =20 #endif /* PPC_INTERNAL_H */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 65545ba9ca..1c7a7b4b38 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -9014,9 +9014,11 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D { =20 static const struct TCGCPUOps ppc_tcg_ops =3D { .initialize =3D ppc_translate_init, - .tlb_fill =3D ppc_cpu_tlb_fill, =20 -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D ppc_cpu_record_sigsegv, +#else + .tlb_fill =3D ppc_cpu_tlb_fill, .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .do_interrupt =3D ppc_cpu_do_interrupt, .cpu_exec_enter =3D ppc_cpu_exec_enter, diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index aa3f867596..7ff76f7a06 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -21,16 +21,23 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "internal.h" =20 - -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; int exception, error_code; =20 + /* + * Both DSISR and the "trap number" (exception vector offset, + * looked up from exception_index) are present in the linux-user + * signal frame. + * FIXME: we don't actually populate the trap number properly. + * It would be easiest to fill in an env->trap value now. + */ if (access_type =3D=3D MMU_INST_FETCH) { exception =3D POWERPC_EXCP_ISI; error_code =3D 0x40000000; --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635616514922269.08970391979494; Sat, 30 Oct 2021 10:55:14 -0700 (PDT) Received: from localhost ([::1]:59048 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsZV-0004gA-T9 for importer@patchew.org; Sat, 30 Oct 2021 13:55:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57976) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryi-0002KP-L3 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:13 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:40571) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryf-0000DZ-Vz for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:12 -0400 Received: by mail-pj1-x102e.google.com with SMTP id n36-20020a17090a5aa700b0019fa884ab85so13057397pji.5 for ; Sat, 30 Oct 2021 10:17:09 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.17.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:17:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HtawaHYSfgiYXorLPYx7eO4JeOJDito5IEpdHHHLhLI=; b=lmdjodi1zC9160wxOhmCH889U5IhoFe3nerTLJjBHCvULJacfMO3NZFouTIZehwXTC YNdwsyCBRUctFBlvg8FMxIodV9LAxS+YHlYE/gND0+EQJtj3Fe8vdyeBTuKLh0zhGbw6 /dg+lpJoGm3ADTe+ySJCJXqV77ZZ1mGJWS+iwaT9/kacudKPiD8l3pg8hKrmDEsitVU6 9tBL45TyjqCOLodHgryPk0kXcuheZ5AjLAHn2LaWN/ozed0qEEktBERWfZPf4PH+1X50 yOcLTBbdDarBFI+lr6gsOe1YXlBNvyaxALtz98Hfs06S0NgcUNDSuGTh3et7/kWow4ot cmvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HtawaHYSfgiYXorLPYx7eO4JeOJDito5IEpdHHHLhLI=; b=MVeJfDwcqlH8h1UGRRi7hwZodoXpOQBQ6eou3++80mYe/nG8XU4bEu9rtuFkK3FYeb X2riyy2pDn7J2yDlXS8Vye1Ko+r3BMB3v43IWW9WalPJrSs8EN/esXOZc97Je3AZntu5 xja2107ITkYC/W5NONXblPla0CnZiNL+mVmelMQnOQJ0xB1LBX1E4/pmDcAFKadNywRA Stih5RcixQ3e2PCAMGL4zr4dNCzBBd3gV5Sr/dAyTP+BlQzQDTrkilZ+XgeN3yJHH9Zl 6KbSFDrI1gWd1JA1uOGY6i4MZJEhxiwpcOQiHgLQ+xAx6m08KGqCdJFZUBW28yXwEQfI xpoA== X-Gm-Message-State: AOAM532dUmXREfnKwPIKZjVH3MFaOsvcOcr0PqqFpCpnoXyQ6HvnFL8g XBD9G6La1n9oQv3mb1Zj4FksSu+LOEzYDA== X-Google-Smtp-Source: ABdhPJzTAR2vQDsQ8Sk6tbVJGfyCtV6O0tib/nr7CWcC/zfADi8GWw+7XTHfzTBS+3GmjtdkzdyluA== X-Received: by 2002:a17:90b:1e09:: with SMTP id pg9mr27906420pjb.59.1635614228810; Sat, 30 Oct 2021 10:17:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 35/66] target/riscv: Make riscv_cpu_tlb_fill sysemu only Date: Sat, 30 Oct 2021 10:16:04 -0700 Message-Id: <20211030171635.1689530-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616516133100001 The fallback code in cpu_loop_exit_sigsegv is sufficient for riscv linux-user. Remove the code from cpu_loop that raised SIGSEGV. Reviewed-by: Warner Losh Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- linux-user/riscv/cpu_loop.c | 7 ------- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 21 +-------------------- 3 files changed, 2 insertions(+), 28 deletions(-) diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index e5bb6d908a..b301dac802 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -87,13 +87,6 @@ void cpu_loop(CPURISCVState *env) sigcode =3D TARGET_TRAP_BRKPT; sigaddr =3D env->pc; break; - case RISCV_EXCP_INST_PAGE_FAULT: - case RISCV_EXCP_LOAD_PAGE_FAULT: - case RISCV_EXCP_STORE_PAGE_FAULT: - signum =3D TARGET_SIGSEGV; - sigcode =3D TARGET_SEGV_MAPERR; - sigaddr =3D env->badaddr; - break; case RISCV_EXCP_SEMIHOST: env->gpr[xA0] =3D do_common_semihosting(cs); env->pc +=3D 4; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d53125dbc..f812998123 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -694,9 +694,9 @@ static const struct SysemuCPUOps riscv_sysemu_ops =3D { static const struct TCGCPUOps riscv_tcg_ops =3D { .initialize =3D riscv_translate_init, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, - .tlb_fill =3D riscv_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D riscv_cpu_tlb_fill, .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, .do_interrupt =3D riscv_cpu_do_interrupt, .do_transaction_failed =3D riscv_cpu_do_transaction_failed, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f30ff672f8..9eeed38c7e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -814,7 +814,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, riscv_cpu_two_stage_lookup(mmu_idx); riscv_raise_exception(env, cs->exception_index, retaddr); } -#endif /* !CONFIG_USER_ONLY */ =20 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -822,7 +821,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; -#ifndef CONFIG_USER_ONLY vaddr im_address; hwaddr pa =3D 0; int prot, prot2, prot_pmp; @@ -954,25 +952,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, } =20 return true; - -#else - switch (access_type) { - case MMU_INST_FETCH: - cs->exception_index =3D RISCV_EXCP_INST_PAGE_FAULT; - break; - case MMU_DATA_LOAD: - cs->exception_index =3D RISCV_EXCP_LOAD_PAGE_FAULT; - break; - case MMU_DATA_STORE: - cs->exception_index =3D RISCV_EXCP_STORE_PAGE_FAULT; - break; - default: - g_assert_not_reached(); - } - env->badaddr =3D address; - cpu_loop_exit_restore(cs, retaddr); -#endif } +#endif /* !CONFIG_USER_ONLY */ =20 /* * Handle Traps --=20 2.25.1 From nobody Mon Feb 9 17:48:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163561664447887.75505641184657; Sat, 30 Oct 2021 10:57:24 -0700 (PDT) Received: from localhost ([::1]:39560 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsbb-00025t-9D for importer@patchew.org; Sat, 30 Oct 2021 13:57:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58008) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryk-0002L5-E2 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:14 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:54095) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryh-0000Dy-SO for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:14 -0400 Received: by mail-pj1-x1030.google.com with SMTP id iq11so2450892pjb.3 for ; Sat, 30 Oct 2021 10:17:10 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.17.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:17:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=66Bl8EQR5t0ae9YRNU1Dduo8SF5bSu1MJ1ucFe28OE8=; b=xS57va7fGiTuXFu4BeMARbyZh6HksRJa2h9Ne1dcTEjSSm15h5xKBg3uLOnhi2CQdO eUG3WyWqxsIZEG49aD+J4/iJ+tFADlYfvsRLJDUWWszJbbpqsrzJ9GauhJm43ThKO2um K8DGD24K8dJAQoczsA5l4cz6F3mB53P9WECeh6jtE/KI8m5CIVp/6SWALtXFDgQI0yqO yLt8NfPq10gehbrcPvYPS39PwXRSi5Vdr8wT6zwBpojxvfWEYlMmcPpP6vBqG+ufvNhv s4nUFDnG+uCl6lqiMTN8A98/S9BmW99043xrAmDK3gh1UM2oNQB9c/ZI7qZ9A6tJ3i4Y mY7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=66Bl8EQR5t0ae9YRNU1Dduo8SF5bSu1MJ1ucFe28OE8=; b=1nihLm1Gv4dy9DwzgZoO3ndYdoGjxGJcIA4qiZmnGE9z/EBpbmuv8RHqS3kXkSfJ3g iTSz02W41SnveYTtFfIa+z0mrP0DVizcanpHoDFTtLGNTmxfd3p1HEEDGlZrWcXaCYas DyVShL2h7Ps4yEqGv5c1qiqQMaVhIJBAWghz75rQciqZniseOZYJPVfyhueI7O4yVRH5 muAHVhsYTNVEwn0h4Siq+Xhb2OF/DtlrSaZg1sg7amNCd+mmiYPawuxlEaRCJR3lg4J9 IGZxydDs7OzEtmgWhmWJLStgIFhsI/DEeqQb0w5ZxJ+lUoLaJ7t1B5pLaJ6n09kP0/CP NdZw== X-Gm-Message-State: AOAM533xgVlLEnIJqtBm29UFDeY6KpCC1mvOCCD0aG+NDC/eBWUmGKc/ h7DNohHZ7zosZXaDS7n9v1usa/llaZXGtw== X-Google-Smtp-Source: ABdhPJx2JywIiZrZ04tE8b9fbnPFltWrqMTG8ezb2Lkftq2OEsWKRVGbV4qu4NnofsRjhJftt1EmqQ== X-Received: by 2002:a17:903:10a:b0:141:6975:1cec with SMTP id y10-20020a170903010a00b0014169751cecmr16211863plc.51.1635614229730; Sat, 30 Oct 2021 10:17:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 36/66] target/s390x: Use probe_access_flags in s390_probe_access Date: Sat, 30 Oct 2021 10:16:05 -0700 Message-Id: <20211030171635.1689530-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616646210100001 Content-Type: text/plain; charset="utf-8" Not sure why the user-only code wasn't rewritten to use probe_access_flags at the same time that the sysemu code was converted. For the purpose of user-only, this is an exact replacement. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/s390x/tcg/mem_helper.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 17e3f83641..362a30d99e 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -141,20 +141,12 @@ static int s390_probe_access(CPUArchState *env, targe= t_ulong addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t ra) { +#if defined(CONFIG_USER_ONLY) + return probe_access_flags(env, addr, access_type, mmu_idx, + nonfault, phost, ra); +#else int flags; =20 -#if defined(CONFIG_USER_ONLY) - flags =3D page_get_flags(addr); - if (!(flags & (access_type =3D=3D MMU_DATA_LOAD ? PAGE_READ : PAGE_WR= ITE_ORG))) { - env->__excp_addr =3D addr; - flags =3D (flags & PAGE_VALID) ? PGM_PROTECTION : PGM_ADDRESSING; - if (nonfault) { - return flags; - } - tcg_s390_program_interrupt(env, flags, ra); - } - *phost =3D g2h(env_cpu(env), addr); -#else /* * For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr= =3D=3DNULL * to detect if there was an exception during tlb_fill(). @@ -173,8 +165,8 @@ static int s390_probe_access(CPUArchState *env, target_= ulong addr, int size, (access_type =3D=3D MMU_DATA_STORE ? BP_MEM_WRITE : BP_MEM_READ), ra); } -#endif return 0; +#endif } =20 static int access_prepare_nf(S390Access *access, CPUS390XState *env, --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635618341963453.5373049045795; Sat, 30 Oct 2021 11:25:41 -0700 (PDT) Received: from localhost ([::1]:38912 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgt2y-0006uY-Mi for importer@patchew.org; Sat, 30 Oct 2021 14:25:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58022) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryl-0002O2-HK for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:15 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:41671) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryi-0000EK-9t for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:15 -0400 Received: by mail-pf1-x436.google.com with SMTP id u33so278305pfg.8 for ; Sat, 30 Oct 2021 10:17:11 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.17.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:17:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ij1YRgU0peRo+QSVg6ezzkIr6IGfKaWXUXRkApukMz0=; b=EKiSZVL07poOg+G8OU4uOPul7nXaPSTIA7AbHSJ0kHPvuf8O9SPf+7CF15y8SFpNav ot7pZ295v8O/XoTvh8o+MaqBjNmUau+cMX2KiYQX/Ck06onqpd7iTDFodmB5mTN/ZhHN OzR2THohJ9bU3DeWxNxQg92AIru/DDwMv5XbIeS3j91KiFqdI3pNu89++DJDWVVriC4h 4iA7KA5UUekV7ZwUpAbMNBk++IsQj3YB+vPROeV7ObWKypy3YQ+U+7uElq/0ST/OTRcV qgkA3UYMPgTWT+frZmobWQpOtJVZIISMxy5BinsIQxF9+RFWIGpVop88A6o+CXSAz85/ heHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ij1YRgU0peRo+QSVg6ezzkIr6IGfKaWXUXRkApukMz0=; b=u8XpzBuewYqYrf1f4lJ5CnrYsZ//CPJ1Q0ZVc6FBqOO7j0ZAjW51w7pe55OqXzChe8 BnqjcTSftE/suhMOIeX9CioOTqXun9cf4dPnNT/za//BggYpdFBWzlHbJVa2/EZ1uUqA O4adlmQ71q3ebI2THTujwRHm87gj2eY1V5YqzwIyshAtOIr3wiPJKCSNxx6X+3WjCOUr 6h2QVguNNY4DPKeuAke1YpJjVhY8wx3EXhHFtGP2KnDTSxqMCRxhldWtSkcgFU0+Y8XQ 1y6W/JxEiGXDZy6csbWwpdGNf6xZu5/meposErcb4br6Z/NCXjWCUAfJiAborlHOzLxT OnsA== X-Gm-Message-State: AOAM531TS2f8xzDCbKz241hzAVYaqCwGzAPU3/QcXOKRp8CCHXYbWFsF Y0nZtqhdBo5RBk3OLYcI6T697gZfIBsBHw== X-Google-Smtp-Source: ABdhPJxcI81f/AlcuNrFgTUJdGsxPialX1gJTegEawHKPnLEuDrHEeE3nGYF5U3eJRvbgVX658J+nA== X-Received: by 2002:a62:1743:0:b0:480:a01f:bf14 with SMTP id 64-20020a621743000000b00480a01fbf14mr3200323pfx.72.1635614230446; Sat, 30 Oct 2021 10:17:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 37/66] target/s390x: Implement s390_cpu_record_sigsegv Date: Sat, 30 Oct 2021 10:16:06 -0700 Message-Id: <20211030171635.1689530-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635618342933100001 Move the masking of the address from cpu_loop into s390_cpu_record_sigsegv -- this is governed by hw, not linux. This does mean we have to raise our own exception, rather than return to the fallback. Use maperr to choose between PGM_PROTECTION and PGM_ADDRESSING. Use the appropriate si_code for each in cpu_loop. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/s390x/s390x-internal.h | 13 ++++++++++--- linux-user/s390x/cpu_loop.c | 13 ++++++------- target/s390x/cpu.c | 6 ++++-- target/s390x/tcg/excp_helper.c | 18 +++++++++++------- 4 files changed, 31 insertions(+), 19 deletions(-) diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 27d4a03ca1..163aa4f94a 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -270,13 +270,20 @@ ObjectClass *s390_cpu_class_by_name(const char *name); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); -bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) QEMU_NORETURN; =20 +#ifdef CONFIG_USER_ONLY +void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr); +#else +bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#endif + =20 /* fpu_helper.c */ uint32_t set_cc_nz_f32(float32 v); diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c index 69b69981f6..d089c8417e 100644 --- a/linux-user/s390x/cpu_loop.c +++ b/linux-user/s390x/cpu_loop.c @@ -24,8 +24,6 @@ #include "cpu_loop-common.h" #include "signal-common.h" =20 -/* s390x masks the fault address it reports in si_addr for SIGSEGV and SIG= BUS */ -#define S390X_FAIL_ADDR_MASK -4096LL =20 static int get_pgm_data_si_code(int dxc_code) { @@ -111,12 +109,13 @@ void cpu_loop(CPUS390XState *env) n =3D TARGET_ILL_ILLOPC; goto do_signal_pc; case PGM_PROTECTION: + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_ACCERR, + env->__excp_addr); + break; case PGM_ADDRESSING: - sig =3D TARGET_SIGSEGV; - /* XXX: check env->error_code */ - n =3D TARGET_SEGV_MAPERR; - addr =3D env->__excp_addr & S390X_FAIL_ADDR_MASK; - goto do_signal; + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, + env->__excp_addr); + break; case PGM_EXECUTE: case PGM_SPECIFICATION: case PGM_SPECIAL_OP: diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7b7b05f1d3..593dda75c4 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -266,9 +266,11 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 static const struct TCGCPUOps s390_tcg_ops =3D { .initialize =3D s390x_translate_init, - .tlb_fill =3D s390_cpu_tlb_fill, =20 -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D s390_cpu_record_sigsegv, +#else + .tlb_fill =3D s390_cpu_tlb_fill, .cpu_exec_interrupt =3D s390_cpu_exec_interrupt, .do_interrupt =3D s390_cpu_do_interrupt, .debug_excp_handler =3D s390x_cpu_debug_excp_handler, diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 3d6662a53c..b923d080fc 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -89,16 +89,20 @@ void s390_cpu_do_interrupt(CPUState *cs) cs->exception_index =3D -1; } =20 -bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { S390CPU *cpu =3D S390_CPU(cs); =20 - trigger_pgm_exception(&cpu->env, PGM_ADDRESSING); - /* On real machines this value is dropped into LowMem. Since this - is userland, simply put this someplace that cpu_loop can find it. = */ - cpu->env.__excp_addr =3D address; + trigger_pgm_exception(&cpu->env, maperr ? PGM_ADDRESSING : PGM_PROTECT= ION); + /* + * On real machines this value is dropped into LowMem. Since this + * is userland, simply put this someplace that cpu_loop can find it. + * S390 only gives the page of the fault, not the exact address. + * C.f. the construction of TEC in mmu_translate(). + */ + cpu->env.__excp_addr =3D address & TARGET_PAGE_MASK; cpu_loop_exit_restore(cs, retaddr); } =20 --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635616840626728.5925223080643; Sat, 30 Oct 2021 11:00:40 -0700 (PDT) Received: from localhost ([::1]:48200 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsel-0007oJ-Hh for importer@patchew.org; Sat, 30 Oct 2021 14:00:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58014) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryl-0002Lm-0X for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:15 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:45926) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryi-0000EP-Bm for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:14 -0400 Received: by mail-pj1-x102c.google.com with SMTP id ls14-20020a17090b350e00b001a00e2251c8so9585298pjb.4 for ; Sat, 30 Oct 2021 10:17:11 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.17.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:17:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8ZM/9TjmIZZ72copbPvsL/6T35TidGs+EyZyHS5h5dE=; b=F1qcW3PTTHPZ4hGJbfU0qm8QqjflT9PZ2e72sU6WAiEE2n+niTdxa3e/YyPbRjdhPq FHJ0up9Kl73Gauh3Gt+PR2oI6P0B1ZDYFJD1csxnriKubBa4bARmIcnj5CKqoItz8oc8 tyUoxKwNeIrKmmopC6tRAT5fkFAPS4FhV8KA5dC2IfNWrH7LCSo+4lYwciPS6anloMGF Ufp7VxNsYF4tx/72Di0k7VBkE96QE/PU7s5D+rdqvmslj+Jy9ZR4LcKH0vIerLYUl/1z NbO3lQ0RrY8p0hGFk+tAvKlvXc2DmjIAD/SEbaeKveckKUfAW6psf9dhC/G8V+FeZtxK LKYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8ZM/9TjmIZZ72copbPvsL/6T35TidGs+EyZyHS5h5dE=; b=moH8hxv/v/LbCnPjZcFy5avm4yN00vxDARPzaWCyd4ZpbsZ3nCHzfsWUdLHKO5LiZi CO6zK9BfZNHDmNymx6K9Hm9UVWBtvmsxlQJvFE5vlXaru9m5mCTl2Vje4naNlIEf+g4Z JS3fFeNVxF2+YZ53rkXV/lFf1B+YhQoa0pROJDzXSuJoy0y41Hy8V4mwCNP5uZgQfmkf Tcquxyb2UZRJotkOiXukopDLrhdl5iYX6GxBWXeSzv1zfE4n/DOCIGH+a5K74Y5VBrky n7mFicjgPGyi/4p9fo7CFxV//mo6I1kQm1sCb43us932TlkcDsOcZteaopxn7yvvKcjs EPuw== X-Gm-Message-State: AOAM532zhIUIIrWA5kGWsm5gCYXUQqSnAn92uPJwHPHcfcSmCK7MWUAw UW/iFZfOUJrcWlXqWKMrlCyVnmWQYnUErA== X-Google-Smtp-Source: ABdhPJzqECkDRzuy37oJQ0G8MIm3z7eo9MATvpp1+Q+Yqp+UCQQSIiSCmfAxclJLlDhiViXCIfHA3w== X-Received: by 2002:a17:90a:718b:: with SMTP id i11mr27866736pjk.22.1635614231133; Sat, 30 Oct 2021 10:17:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 38/66] target/sh4: Make sh4_cpu_tlb_fill sysemu only Date: Sat, 30 Oct 2021 10:16:07 -0700 Message-Id: <20211030171635.1689530-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616842603100001 Content-Type: text/plain; charset="utf-8" The fallback code in cpu_loop_exit_sigsegv is sufficient for sh4 linux-user. Remove the code from cpu_loop that raised SIGSEGV. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/sh4/cpu.h | 6 +++--- linux-user/sh4/cpu_loop.c | 8 -------- target/sh4/cpu.c | 2 +- target/sh4/helper.c | 9 +-------- 4 files changed, 5 insertions(+), 20 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index dc81406646..4cfb109f56 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -213,12 +213,12 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, va= ddr addr, uintptr_t retaddr) QEMU_NORETURN; =20 void sh4_translate_init(void); +void sh4_cpu_list(void); + +#if !defined(CONFIG_USER_ONLY) bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); - -void sh4_cpu_list(void); -#if !defined(CONFIG_USER_ONLY) void superh_cpu_do_interrupt(CPUState *cpu); bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); void cpu_sh4_invalidate_tlb(CPUSH4State *s); diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c index 65b8972e3c..ac9b01840c 100644 --- a/linux-user/sh4/cpu_loop.c +++ b/linux-user/sh4/cpu_loop.c @@ -65,14 +65,6 @@ void cpu_loop(CPUSH4State *env) info.si_code =3D TARGET_TRAP_BRKPT; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case 0xa0: - case 0xc0: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->tea; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); arch_interrupt =3D false; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 2047742d03..06b2691dc4 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -236,9 +236,9 @@ static const struct SysemuCPUOps sh4_sysemu_ops =3D { static const struct TCGCPUOps superh_tcg_ops =3D { .initialize =3D sh4_translate_init, .synchronize_from_tb =3D superh_cpu_synchronize_from_tb, - .tlb_fill =3D superh_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D superh_cpu_tlb_fill, .cpu_exec_interrupt =3D superh_cpu_exec_interrupt, .do_interrupt =3D superh_cpu_do_interrupt, .do_unaligned_access =3D superh_cpu_do_unaligned_access, diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 53cb9c3b63..6a620e36fc 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -796,8 +796,6 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) return false; } =20 -#endif /* !CONFIG_USER_ONLY */ - bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -806,11 +804,6 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, CPUSH4State *env =3D &cpu->env; int ret; =20 -#ifdef CONFIG_USER_ONLY - ret =3D (access_type =3D=3D MMU_DATA_STORE ? MMU_DTLB_VIOLATION_WRITE : - access_type =3D=3D MMU_INST_FETCH ? MMU_ITLB_VIOLATION : - MMU_DTLB_VIOLATION_READ); -#else target_ulong physical; int prot; =20 @@ -829,7 +822,6 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, if (ret !=3D MMU_DTLB_MULTIPLE && ret !=3D MMU_ITLB_MULTIPLE) { env->pteh =3D (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_M= ASK); } -#endif =20 env->tea =3D address; switch (ret) { @@ -868,3 +860,4 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, } cpu_loop_exit_restore(cs, retaddr); } +#endif /* !CONFIG_USER_ONLY */ --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635618233537734.9423458274522; Sat, 30 Oct 2021 11:23:53 -0700 (PDT) Received: from localhost ([::1]:35980 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgt1E-0004xI-Do for importer@patchew.org; Sat, 30 Oct 2021 14:23:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58024) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgryl-0002PH-S3 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:15 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:42977) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgryj-0000Ed-Fl for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:17:15 -0400 Received: by mail-pj1-x1036.google.com with SMTP id nn3-20020a17090b38c300b001a03bb6c4ebso9607095pjb.1 for ; Sat, 30 Oct 2021 10:17:12 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id nv4sm3111943pjb.17.2021.10.30.10.17.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:17:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OFBASZgYo/dnEXgBhwjQsgVMikt4qFVfoC5aZFh8E0o=; b=hn6eQcNsa3UxaC/ODRJXUKmGHGGuto6mmkFhWfHMai9e9OJPTs1lsX8xcZtu+xIcLq cE0pcVikGuca9LEXuVGlE4DnaEe/8DY8BwFrzbTHAAtWZ8AZbp6b1q3xRk26S45sGckj 1Y7ofw5pjK4XpOhG8woKyQjhyWp6tbf/hE02EZjJtjIcOGQMej5hlcwDHE9Ff+F5fhNH 9vlGJislC1vTSScfAut9Sx70T/iqUd5L3IcF3E1iI5sjHJ2WO+lDKdttmyhktV8KbMie jdrFN7dl0gqPzCxrU6duewBvap1if6jPQjvNiBsDGsVb2J2/+xUaxMP7fBblPTQV0xfA nF8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OFBASZgYo/dnEXgBhwjQsgVMikt4qFVfoC5aZFh8E0o=; b=uicw/kUafeUhoNeaKX5p14XxxPQRBwSj5Pgz/1v6nr2Me3jSbpvlyFgCqjdz9iI8p5 NVK0r7KJeVSOIe0mRXr7LfVFG46rpjvWO0tPHdAgVQ3qopxPzMPhURe0lhcNIPjbUyUh sM7W8JCeZhUHHGGqKOd516gbEzU7eflHv7yYUEPFgp7MFXimWrzwaDU7c0/5DXrbq8p2 Wt8nkPawoz5rsSxLzzQ7YfyisCDU5j26gU/+oaNA3GVvGxbAJmJzjSZnFRhNtbN16tY4 aLcoAcl2mKi7nSsUqQ2kI2Saf41ONrhhqHAABdGngI8+LMHg4jBLxnqf+lFR9tP0NBFV KebQ== X-Gm-Message-State: AOAM533lL67a1c11hdYHWzTXrxem6OUUTyYAVM64J8CCB8sLfHDl39XJ tS27/d6qBO9iWnar8vagu7RXyn92NMmSSA== X-Google-Smtp-Source: ABdhPJxCXj6exfHc/78Rzx12UsKjt5nPwUb7ruxLsRgl3SvzmD1B8SPvA3yP34tv5RzZvBd5PiKBnA== X-Received: by 2002:a17:902:6a86:b0:13f:f048:9778 with SMTP id n6-20020a1709026a8600b0013ff0489778mr16018094plk.27.1635614232067; Sat, 30 Oct 2021 10:17:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 39/66] target/sparc: Make sparc_cpu_tlb_fill sysemu only Date: Sat, 30 Oct 2021 10:16:08 -0700 Message-Id: <20211030171635.1689530-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635618234162100001 The fallback code in cpu_loop_exit_sigsegv is sufficient for sparc linux-user. This makes all of the code in mmu_helper.c sysemu only, so remove the ifdefs and move the file to sparc_softmmu_ss. Remove the code from cpu_loop that handled TT_DFAULT and TT_TFAULT. Cc: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- linux-user/sparc/cpu_loop.c | 25 ------------------------- target/sparc/cpu.c | 2 +- target/sparc/mmu_helper.c | 25 ------------------------- target/sparc/meson.build | 2 +- 4 files changed, 2 insertions(+), 52 deletions(-) diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index ad29b4eb6a..0ba65e431c 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -219,17 +219,6 @@ void cpu_loop (CPUSPARCState *env) case TT_WIN_UNF: /* window underflow */ restore_window(env); break; - case TT_TFAULT: - case TT_DFAULT: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->mmuregs[4]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; #else case TT_SPILL: /* window overflow */ save_window(env); @@ -237,20 +226,6 @@ void cpu_loop (CPUSPARCState *env) case TT_FILL: /* window underflow */ restore_window(env); break; - case TT_TFAULT: - case TT_DFAULT: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - if (trapnr =3D=3D TT_DFAULT) - info._sifields._sigfault._addr =3D env->dmmu.mmuregs[4= ]; - else - info._sifields._sigfault._addr =3D cpu_tsptr(env)->tpc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; #ifndef TARGET_ABI32 case 0x16e: flush_windows(env); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 21dd27796d..55268ed2a1 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -865,9 +865,9 @@ static const struct SysemuCPUOps sparc_sysemu_ops =3D { static const struct TCGCPUOps sparc_tcg_ops =3D { .initialize =3D sparc_tcg_init, .synchronize_from_tb =3D sparc_cpu_synchronize_from_tb, - .tlb_fill =3D sparc_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D sparc_cpu_tlb_fill, .cpu_exec_interrupt =3D sparc_cpu_exec_interrupt, .do_interrupt =3D sparc_cpu_do_interrupt, .do_transaction_failed =3D sparc_cpu_do_transaction_failed, diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index a44473a1c7..2ad47391d0 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -25,30 +25,6 @@ =20 /* Sparc MMU emulation */ =20 -#if defined(CONFIG_USER_ONLY) - -bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; - - if (access_type =3D=3D MMU_INST_FETCH) { - cs->exception_index =3D TT_TFAULT; - } else { - cs->exception_index =3D TT_DFAULT; -#ifdef TARGET_SPARC64 - env->dmmu.mmuregs[4] =3D address; -#else - env->mmuregs[4] =3D address; -#endif - } - cpu_loop_exit_restore(cs, retaddr); -} - -#else - #ifndef TARGET_SPARC64 /* * Sparc V8 Reference MMU (SRMMU) @@ -926,4 +902,3 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) } return phys_addr; } -#endif diff --git a/target/sparc/meson.build b/target/sparc/meson.build index a3638b9503..a801802ee2 100644 --- a/target/sparc/meson.build +++ b/target/sparc/meson.build @@ -6,7 +6,6 @@ sparc_ss.add(files( 'gdbstub.c', 'helper.c', 'ldst_helper.c', - 'mmu_helper.c', 'translate.c', 'win_helper.c', )) @@ -16,6 +15,7 @@ sparc_ss.add(when: 'TARGET_SPARC64', if_true: files('int6= 4_helper.c', 'vis_helpe sparc_softmmu_ss =3D ss.source_set() sparc_softmmu_ss.add(files( 'machine.c', + 'mmu_helper.c', 'monitor.c', )) =20 --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635617113823183.65605179739362; Sat, 30 Oct 2021 11:05:13 -0700 (PDT) Received: from localhost ([::1]:60300 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsjA-0007Vv-P1 for importer@patchew.org; Sat, 30 Oct 2021 14:05:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58562) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1i-0001QQ-3s for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:18 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:36702) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1g-000295-1I for qemu-devel@nongnu.org; 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[174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kAcqfrBKLTctf7S2SRnWlKvQ84+gE9eIlExzwRxWIv4=; b=y5QQGo1MLXU+/OR5/9pZ0aFtq/lSM76ObKfWwPaiY1CT85YqtP4O0xbq44KYt7T4eR YR2do6E0qrt897F8zq85tpgzvPJRZK8AFbS0XM9O4cJbNBd4DhIm1dk7lYTfhyGoFmzZ GbUQEUk2s/RUlsYrWGHW2Bj8pf2dDiyriFlyEIM75S7ZL3PtxBYU+Xvj8QzmCe74fEeg Lo//h+M3lNt6m2PqixCf6mjijQf1x0vj5UtsPXlbaBXjAlFnC2tn0SX4TWgI/XN47Fn7 Nx9qH+N/Mnimcj80ogFkmsYzA5rQ9YHSm19fKmgJ0wQTG+69JrNtZLngnCqxgOJ7u3hS iE3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kAcqfrBKLTctf7S2SRnWlKvQ84+gE9eIlExzwRxWIv4=; b=KczZi9HTwbIXeEoIpeolEXmfV8L66uOsfAS8QNCqdDMk/b/J0q0ohOYevM4BbQB0uy oFa/uYLSOSS3QTPU2QPtQR31CGPykk7Mkd6MTMLUdBPj3KlK5B/6K8Y+UiCNkNf9YRtq dJXTgd4Hn2X8gkOY9U3fZBvI3UWrzQnw1aLIHKbIYlvxUBaTpCrhVTlgJ4yFt2xKonO2 mF3TNHWBIGX1vfJ0ugHtYQqS2q6ySVkmxOiRIgme7cKIp6SZ/4Em6K+DeVLpURyu9zBf iC/kGv1AWHbr4gNEgU0dneY49GTZdXt2un3kFU7OFEpoc0rxC+/c8ectxZC5lwYVNb9T gisg== X-Gm-Message-State: AOAM530vcb2RTaz2Sz9OHAUE0ZwT5Ba5RWqerP/++Rj7pH0Pngh+h9fM E3kUJn5m42ySFifj5IrwW6S4yhDldH0ykw== X-Google-Smtp-Source: ABdhPJxqLDu0KLTq3ApGRHZRajc9UJZ9L2XdzgMNpxdGQgMb9PhjHjdBNlg/SnBYp7SLQJT2OyAlLA== X-Received: by 2002:a17:903:1252:b0:13d:f3f6:2e1c with SMTP id u18-20020a170903125200b0013df3f62e1cmr16209629plh.73.1635614413909; Sat, 30 Oct 2021 10:20:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 40/66] target/xtensa: Make xtensa_cpu_tlb_fill sysemu only Date: Sat, 30 Oct 2021 10:16:09 -0700 Message-Id: <20211030171635.1689530-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635617116005100001 The fallback code in cpu_loop_exit_sigsegv is sufficient for xtensa linux-user. Remove the code from cpu_loop that raised SIGSEGV. Acked-by: Max Filippov Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 2 +- linux-user/xtensa/cpu_loop.c | 9 --------- target/xtensa/cpu.c | 2 +- target/xtensa/helper.c | 22 +--------------------- 4 files changed, 3 insertions(+), 32 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index f9a510ca46..02143f2f77 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -563,10 +563,10 @@ struct XtensaCPU { }; =20 =20 +#ifndef CONFIG_USER_ONLY bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c index 622afbcd34..a83490ab35 100644 --- a/linux-user/xtensa/cpu_loop.c +++ b/linux-user/xtensa/cpu_loop.c @@ -226,15 +226,6 @@ void cpu_loop(CPUXtensaState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; =20 - case LOAD_PROHIBITED_CAUSE: - case STORE_PROHIBITED_CAUSE: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr =3D env->sregs[EXCVADDR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - default: fprintf(stderr, "exccause =3D %d\n", env->sregs[EXCCAUSE]); g_assert_not_reached(); diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c1cbd03595..224f723236 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -192,10 +192,10 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = =3D { =20 static const struct TCGCPUOps xtensa_tcg_ops =3D { .initialize =3D xtensa_translate_init, - .tlb_fill =3D xtensa_cpu_tlb_fill, .debug_excp_handler =3D xtensa_breakpoint_handler, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D xtensa_cpu_tlb_fill, .cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt, .do_interrupt =3D xtensa_cpu_do_interrupt, .do_transaction_failed =3D xtensa_cpu_do_transaction_failed, diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f18ab383fd..29d216ec1b 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -242,27 +242,7 @@ void xtensa_cpu_list(void) } } =20 -#ifdef CONFIG_USER_ONLY - -bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; - - qemu_log_mask(CPU_LOG_INT, - "%s: rw =3D %d, address =3D 0x%08" VADDR_PRIx ", size = =3D %d\n", - __func__, access_type, address, size); - env->sregs[EXCVADDR] =3D address; - env->sregs[EXCCAUSE] =3D (access_type =3D=3D MMU_DATA_STORE ? - STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE= ); - cs->exception_index =3D EXC_USER; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - +#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163561895374251.57767137295366; Sat, 30 Oct 2021 11:35:53 -0700 (PDT) Received: from localhost ([::1]:56164 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgtCq-0001oV-J8 for importer@patchew.org; Sat, 30 Oct 2021 14:35:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58578) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1i-0001R5-RR for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:21 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:44871) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1g-00029A-6x for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:18 -0400 Received: by mail-pl1-x62d.google.com with SMTP id t11so8905724plq.11 for ; Sat, 30 Oct 2021 10:20:15 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AlAKO3pHLk0w42dzpdqlCWgmBC5kkngUdLfuQLXO9ho=; b=ZvF1MOcVZbocKmC7qpDsXhuxKuOHCT5JbfKFaZToefSxL/a03CFtfaUXNRcVKJXmnI VQqp9F23iW/wMKNapCdnJNhmFtvRoFANksM5xSWIe5L36ncWq8/gvdOxESu24x+yFEuU iPS4V1LrvkHC6AZnCZZ53M9Gnt57lU51p4QCYWMZujGKgS0PB419vQrhwsQxYAldsm13 kb/owWrOkYKaBkNvGSDYotv0/g2J83Fs0qlCyibtvYe9w3nbXtKZa6rhY+FEQLOOspL9 htK/CB560/pPkfHexuR1bjqbG6kCI0AIXw3kaJm5duzCvoYP9yqcrXqh936bRD7xQAub Ke4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AlAKO3pHLk0w42dzpdqlCWgmBC5kkngUdLfuQLXO9ho=; b=lf/kkvMG85580zETlbX15DOX2eGsitrE9bhU8PkO3atvgZUdiAjz8l+TXvhoXbFiVV qqvRDLtbrVQJ1hSFhvXoAUxBjJIMAyfD+B0pFiaYFFQdNQ7rKsoQuXqDvA/GPVKYVOe8 RCyBVJ73ZzCZ6locQMRJsOIzB9/by1WSuuzIUD0i2RQ1UIYfZXQJbMxusN4S9pBy5Oix NaIad2MY20zuKo3MSXKSy46P+qM0bKV516202KsxaBDRhWwnQo5KdsUs86DrGo2sg+4K RrPbmLsugR8k/R/AQz7NVQw+EoOx7TFkeThymbTvk4mrW7WHuWemx4tD8H+K7oeE8KUL Oc4A== X-Gm-Message-State: AOAM532EiHiM3WaXXMnxw41nEkS2znJgDQhKc2IGNV8kbviR/RPUhUNL FbPBpRfH7mLPwdMC95/+nC4aW/n8P5gc8Q== X-Google-Smtp-Source: ABdhPJwR4mVILa6P3G3TeuAEDwJhJEjc/5v8fYUoYBlfVWcQnInY8GtU1sSTS82ls2eqIYDawlozYA== X-Received: by 2002:a17:902:728b:b0:13f:c086:bdfe with SMTP id d11-20020a170902728b00b0013fc086bdfemr15957427pll.6.1635614414757; Sat, 30 Oct 2021 10:20:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 41/66] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Date: Sat, 30 Oct 2021 10:16:10 -0700 Message-Id: <20211030171635.1689530-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635618955649100003 We have replaced tlb_fill with record_sigsegv for user mode. Move the declaration to restrict it to system emulation. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 22 ++++++++++------------ linux-user/signal.c | 3 --- 2 files changed, 10 insertions(+), 15 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 41718b695b..8eadd404c8 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -35,18 +35,6 @@ struct TCGCPUOps { void (*cpu_exec_enter)(CPUState *cpu); /** @cpu_exec_exit: Callback for cpu_exec cleanup */ void (*cpu_exec_exit)(CPUState *cpu); - /** - * @tlb_fill: Handle a softmmu tlb miss or user-only address fault - * - * For system mode, if the access is valid, call tlb_set_page - * and return true; if the access is invalid, and probe is - * true, return false; otherwise raise an exception and do - * not return. For user-only mode, always raise an exception - * and do not return. - */ - bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); /** @debug_excp_handler: Callback for handling debug exceptions */ void (*debug_excp_handler)(CPUState *cpu); =20 @@ -68,6 +56,16 @@ struct TCGCPUOps { #ifdef CONFIG_SOFTMMU /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** + * @tlb_fill: Handle a softmmu tlb miss + * + * If the access is valid, call tlb_set_page and return true; + * if the access is invalid and probe is true, return false; + * otherwise raise an exception and do not return. + */ + bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); /** * @do_transaction_failed: Callback for handling failed memory transac= tions * (ie bus faults or external aborts; not MMU faults) diff --git a/linux-user/signal.c b/linux-user/signal.c index 135983747d..9d60abc038 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -697,9 +697,6 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong = addr, =20 if (tcg_ops->record_sigsegv) { tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); - } else if (tcg_ops->tlb_fill) { - tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, = ra); - g_assert_not_reached(); } =20 force_sig_fault(TARGET_SIGSEGV, --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635618716078149.85419985795886; Sat, 30 Oct 2021 11:31:56 -0700 (PDT) Received: from localhost ([::1]:49710 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgt90-0005l4-O7 for importer@patchew.org; Sat, 30 Oct 2021 14:31:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58602) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1l-0001RE-9A for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:22 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:34523) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1h-00029G-0K for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:21 -0400 Received: by mail-pf1-x42c.google.com with SMTP id 127so12335592pfu.1 for ; Sat, 30 Oct 2021 10:20:16 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vGec2V7sqBlJXZFFOVGa4jSeCFBEP3Km3jAuCBMCplk=; b=TEcgx0ZuLk0mVfx3LHzcdtCguBL8HUedrt7ayH8FU7IeY5TySv/aQ4/hVlFBJKV7ef aeTD3/pTFrHfsNzBL2mohx73VAoFCpaY95HP8qJRvWeRFvvuuAZ3gfh1qne2BZr0lAf+ KGykZnUhFcP4+AjJsDi7xfN3sgS9beQyIblV2sQQQehsYfj7Hu+FWmEqPJcbBmzvq+iA 9xFrGwoagJ2TIkbmQIzPgEP9kzyT4gepOLki+p1xQjKtFFQxlAyNcB/28lgzvnKhKOIs JsKjISFm8oByM388BzjdH//WT/iAMvJGZu/9Foj+2FZsbWZCyFcq1oBeM8awjs/axilB /Nng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vGec2V7sqBlJXZFFOVGa4jSeCFBEP3Km3jAuCBMCplk=; b=Szu12UtD3sSrWUhofXZ9Tq8/e5IVujF+WmRacJTGQqzqwmfUixTkAKuuZS8bejoacp cl1UCLCxbxuqeedWMo2OEQtwBZJGafp4G8KbTAkY/E/7nvRepb05XDp4WLx8uyL3raSv souwViyvIiC8aGhOcnW3S695QQNVHt1Q5i//VTo6fygj2JnNvSrieXYsPQxCmJ07oFcs 6rFYTKTEhp84mPcjOZC0qrcttt11duedc/3QaMxZK+xeBwj701P1yaM60SQk2pzAYpPd FPRmN3HtKaPlWLuo5XouAqIvzuYstxuK8fHSqT0Se5gGuKMALdYOIr9wpLZ7CNVfeUTZ VHow== X-Gm-Message-State: AOAM533xaQ8imB/5ojFSOFEL7e+BzJQlOE8a04IaN7ugeHvhlT+8/oKe m3fLzsRrOSGqcGrnw0cEJIy7AnXbj5CvMw== X-Google-Smtp-Source: ABdhPJxXridwUano5oqeE2ZLa+MAEU0u8vqhv+FaMExc0g4NotOmMN/jfNu+weqDd4B2l9maXbeF5g== X-Received: by 2002:a05:6a00:1ac9:b0:47c:236d:65f1 with SMTP id f9-20020a056a001ac900b0047c236d65f1mr18567124pfv.3.1635614415708; Sat, 30 Oct 2021 10:20:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 42/66] hw/core: Add TCGCPUOps.record_sigbus Date: Sat, 30 Oct 2021 10:16:11 -0700 Message-Id: <20211030171635.1689530-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635618717262100003 Content-Type: text/plain; charset="utf-8" Add a new user-only interface for updating cpu state before raising a signal. This will take the place of do_unaligned_access for user-only and should result in less boilerplate for each guest. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 8eadd404c8..e13898553a 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -135,6 +135,29 @@ struct TCGCPUOps { void (*record_sigsegv)(CPUState *cpu, vaddr addr, MMUAccessType access_type, bool maperr, uintptr_t ra); + /** + * record_sigbus: + * @cpu: cpu context + * @addr: misaligned guest address + * @access_type: access was read/write/execute + * @ra: host pc for unwinding + * + * We are about to raise SIGBUS with si_code BUS_ADRALN, + * and si_addr set for @addr. Record anything further needed + * for the signal ucontext_t. + * + * If the emulated kernel does not provide the signal handler with + * anything besides the user context registers, and the siginfo_t, + * then this hook need do nothing and may be omitted. + * Otherwise, record the data and return; the caller will raise + * the signal, unwind the cpu state, and return to the main loop. + * + * If it is simpler to re-use the sysemu do_unaligned_access code, + * @ra is provided so that a "normal" cpu exception can be raised. + * In this case, the signal must be raised by the architecture cpu_loo= p. + */ + void (*record_sigbus)(CPUState *cpu, vaddr addr, + MMUAccessType access_type, uintptr_t ra); #endif /* CONFIG_SOFTMMU */ #endif /* NEED_CPU_H */ =20 --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635619138044262.34570824119874; Sat, 30 Oct 2021 11:38:58 -0700 (PDT) Received: from localhost ([::1]:34192 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgtFp-000637-2u for importer@patchew.org; Sat, 30 Oct 2021 14:38:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58626) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1n-0001SP-3i for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:25 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:41653) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1h-00029L-LX for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:21 -0400 Received: by mail-pl1-x636.google.com with SMTP id z11so8912639plg.8 for ; Sat, 30 Oct 2021 10:20:17 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1Ep7pHHg1zb1sPSHGpQ1/FF+Txy5JMnbD431/U5MPag=; b=t5T8Q7bXCnjztyyeSXIMeTShRPqGze7C5CDko58XZl/h3aHchf+onWiIA2t75Hk1Jc dBB8gfQKH97Uzn7/ACDuHGpLETiauncVjVjoYe5z5XaeiVM+FZM82bE3LrGg45BcT3gL ZLJZVsU9ecaFdsowHkYHIwQuYijq9gni/v6MDzVabt4VpTOVo4dQ+qd2tAB5PsBbQVE8 xxwYiInPR3T9wABxk6AMfvUMaWkj5Bpek4+dFInrjY2aJ1FAMBT3+2QZ8OYxMsQY30qQ INtGz3v4rxuTTbmc1390wj2P1KUAgUdS1+XiRN4KvRK6+KFIQByvQtlQ1h2TB0Hax3MF +oTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1Ep7pHHg1zb1sPSHGpQ1/FF+Txy5JMnbD431/U5MPag=; b=GXVQkTOVlQFnZz9nXGe2ceHIInq6CMMyqjMGej7F09jVMmKNb4AvipITZKt0P2F56d XXRUiwMfgP24f9fJOFD+1wnu0vekHNTlKr0I6IV8eM7vSGTCgid9ReoY/smZfhUYbbhS srs+X+LS/Qw5KhVBxFOBQbNEj/haHSIxGGpZHF3HwxTCAjS0RuiuxDgS8aw8xwHXPKhd YeS11SmiRbLw4Fwzgr0XrrWHEC/pj0ZHOxI4/8mvMX25IZyTymtBsPy1j2mgS+Dk//Ob DaH/ofqcVCdOkCMwQDYQwNfCzhlG9Pd9gzpXsorg4WlOzkbRmRVvruZWUl273pbgwPzF PS0Q== X-Gm-Message-State: AOAM533TDY9fCBlAfu4KzXGkdAgiqTl3KWeYukogaQZsOipNU1Zqnips hP2ML9eQUuCX7ldAJDqUBvVy2VN6GCUmxw== X-Google-Smtp-Source: ABdhPJzkqg/YL3aezG6E1cYJK5Oz/HZOOrNDuXp+9oADr3ONpYTS2TretgMR/qBbV74+Dw1q2vmVQg== X-Received: by 2002:a17:902:7892:b0:141:b34e:d884 with SMTP id q18-20020a170902789200b00141b34ed884mr8734584pll.87.1635614416385; Sat, 30 Oct 2021 10:20:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 43/66] linux-user: Add cpu_loop_exit_sigbus Date: Sat, 30 Oct 2021 10:16:12 -0700 Message-Id: <20211030171635.1689530-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635619138310100003 This is a new interface to be provided by the os emulator for raising SIGBUS on fault. Use the new record_sigbus target hook. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 14 ++++++++++++++ linux-user/signal.c | 14 ++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f74578500c..6bb2a0f7ec 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -700,6 +700,20 @@ void QEMU_NORETURN cpu_loop_exit_sigsegv(CPUState *cpu= , target_ulong addr, MMUAccessType access_type, bool maperr, uintptr_t ra); =20 +/** + * cpu_loop_exit_sigbus: + * @cpu: the cpu context + * @addr: the guest address of the alignment fault + * @access_type: access was read/write/execute + * @ra: host pc for unwinding + * + * Use the TCGCPUOps hook to record cpu state, do guest operating system + * specific things to raise SIGBUS, and jump to the main cpu loop. + */ +void QEMU_NORETURN cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, + uintptr_t ra); + #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/linux-user/signal.c b/linux-user/signal.c index 9d60abc038..df2c8678d0 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -706,6 +706,20 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong= addr, cpu_loop_exit_restore(cpu, ra); } =20 +void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, uintptr_t ra) +{ + const struct TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; + + if (tcg_ops->record_sigbus) { + tcg_ops->record_sigbus(cpu, addr, access_type, ra); + } + + force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, addr); + cpu->exception_index =3D EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, ra); +} + /* abort execution with signal */ static void QEMU_NORETURN dump_core_and_abort(int target_sig) { --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635617437686409.9072729954124; Sat, 30 Oct 2021 11:10:37 -0700 (PDT) Received: from localhost ([::1]:40788 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsoO-00050w-9H for importer@patchew.org; Sat, 30 Oct 2021 14:10:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58616) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1m-0001RH-2t for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:22 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:45944) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1i-0002AW-I7 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:21 -0400 Received: by mail-pj1-x1036.google.com with SMTP id ls14-20020a17090b350e00b001a00e2251c8so9589856pjb.4 for ; Sat, 30 Oct 2021 10:20:18 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lCTWBHg3yAPeLZcM1I7LLlGr7M38G+m6NQblxbcjKCQ=; b=Dy3LzhKKgB7BMAxTIXqqfj+KUDeS40rOS7LWaQ6ti+lJGXwng+eavRsxrz8pDRLilH AWCaSPoPm/0Z513LdxaNwybn1ANeUXmraIFXRRGfRws8f3diBsFBRiy+g4zoU8NQANTp 6TWmsUoyaC3JRXtF+BvZ0NuKPP56iafIej8w8ksNs5n0jt8juUNlPwKMOAmafnNhg60U cJYcX4uHntq9H2n1ia6epxU7NvRFCTjn8yqz6VNiFduJbwsuZqsIqxHSmNDjjhwO1o0G yJwCbbp5PDrIz9NERsO37CXG57KHzr4r59nP8YqJr+wAtpGojJvzqLcXLNId4oLtYFuw 6bKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lCTWBHg3yAPeLZcM1I7LLlGr7M38G+m6NQblxbcjKCQ=; b=oN/nRYYL71GKOa9DAXvnG9Pgl4Vo9Mk1YSrPiupdaddGHyCexDDcLmsXR97JvExNnB UJIKC4UifTavybj9TrvfDVm3zYj4LeS+lX3QcPRgrcKkg3SgfTDE1XpPlyhEL/itL+4N gyyuILBbNNdq147l2N51PoFOc75XWzI8hDJgdMvxvBlZXzES7tBGZe43WEdwzBsBNi22 l+d6fzk9Efu801DEt6ptY3sRpanKnOsKfk4DkbNypWrUnu1z38F/jyFwKx4ScI3Dv2MQ tw1L8nso489MY6qclr8ZfOgVybq2fXFc53q9gYB6HrD+RxI3cWBMOFaqJloBjJGbc0t5 zz7w== X-Gm-Message-State: AOAM53009cRj4awFY4hQqGLtXaLEKqxJGIi8mj4U3+wD25HpmhaO6YCz e6erLqcWkJCivSxKbKNxqa3bTt6GqKD4HA== X-Google-Smtp-Source: ABdhPJz4QvjIwThtOifN+/RMlEWo4McKknJrwZ4Y3+qUt0zp7BEY1zn4pyvZupiDIlFnz2jfNjjpEg== X-Received: by 2002:a17:90b:1010:: with SMTP id gm16mr26919681pjb.190.1635614417362; Sat, 30 Oct 2021 10:20:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 44/66] target/alpha: Implement alpha_cpu_record_sigbus Date: Sat, 30 Oct 2021 10:16:13 -0700 Message-Id: <20211030171635.1689530-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635617438976100001 Record trap_arg{0,1,2} for the linux-user signal frame. Raise SIGBUS directly from cpu_loop_exit_sigbus, which means we can remove the code for EXCP_UNALIGN in cpu_loop. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 8 +++++--- linux-user/alpha/cpu_loop.c | 7 ------- target/alpha/cpu.c | 1 + target/alpha/mem_helper.c | 30 ++++++++++++++++++++++-------- 4 files changed, 28 insertions(+), 18 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index d49cc36d07..afd975c878 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -282,9 +282,6 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags); hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; =20 #define cpu_list alpha_cpu_list =20 @@ -451,10 +448,15 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned = reg, uint64_t val); void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, MMUAccessType access_type, bool maperr, uintptr_t retaddr); +void alpha_cpu_record_sigbus(CPUState *cs, vaddr address, + MMUAccessType access_type, uintptr_t retaddr); #else bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 4cc8e0a55c..4029849d5c 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -54,13 +54,6 @@ void cpu_loop(CPUAlphaState *env) fprintf(stderr, "External interrupt. Exit\n"); exit(EXIT_FAILURE); break; - case EXCP_UNALIGN: - info.si_signo =3D TARGET_SIGBUS; - info.si_errno =3D 0; - info.si_code =3D TARGET_BUS_ADRALN; - info._sifields._sigfault._addr =3D env->trap_arg0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_OPCDEC: do_sigill: info.si_signo =3D TARGET_SIGILL; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 69f32c3078..a8990d401b 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -221,6 +221,7 @@ static const struct TCGCPUOps alpha_tcg_ops =3D { =20 #ifdef CONFIG_USER_ONLY .record_sigsegv =3D alpha_cpu_record_sigsegv, + .record_sigbus =3D alpha_cpu_record_sigbus, #else .tlb_fill =3D alpha_cpu_tlb_fill, .cpu_exec_interrupt =3D alpha_cpu_exec_interrupt, diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 75e72bc337..47283a0612 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -23,18 +23,12 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" =20 -/* Softmmu support */ -#ifndef CONFIG_USER_ONLY -void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +static void do_unaligned_access(CPUAlphaState *env, vaddr addr, uintptr_t = retaddr) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; uint64_t pc; uint32_t insn; =20 - cpu_restore_state(cs, retaddr, true); + cpu_restore_state(env_cpu(env), retaddr, true); =20 pc =3D env->pc; insn =3D cpu_ldl_code(env, pc); @@ -42,6 +36,26 @@ void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr a= ddr, env->trap_arg0 =3D addr; env->trap_arg1 =3D insn >> 26; /* opcode */ env->trap_arg2 =3D (insn >> 21) & 31; /* dest regno */ +} + +#ifdef CONFIG_USER_ONLY +void alpha_cpu_record_sigbus(CPUState *cs, vaddr addr, + MMUAccessType access_type, uintptr_t retaddr) +{ + AlphaCPU *cpu =3D ALPHA_CPU(cs); + CPUAlphaState *env =3D &cpu->env; + + do_unaligned_access(env, addr, retaddr); +} +#else +void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + AlphaCPU *cpu =3D ALPHA_CPU(cs); + CPUAlphaState *env =3D &cpu->env; + + do_unaligned_access(env, addr, retaddr); cs->exception_index =3D EXCP_UNALIGN; env->error_code =3D 0; cpu_loop_exit(cs); --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635619333136822.811766920899; Sat, 30 Oct 2021 11:42:13 -0700 (PDT) Received: from localhost ([::1]:40586 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgtIx-0001yK-W9 for importer@patchew.org; Sat, 30 Oct 2021 14:42:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58638) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1n-0001Sy-Gt for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:25 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:38574) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1k-0002Al-Vf for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:22 -0400 Received: by mail-pl1-x62d.google.com with SMTP id i5so8921929pla.5 for ; Sat, 30 Oct 2021 10:20:19 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jLMjBC8As2Qf0j/kKO70QMZc6RPo1kSmruI7dUHbIeQ=; b=oeJSCtLGFxN51rTrk6L/KTZYDmm2Gs350N2/oZH2AafuMqdhodizIeze9Vyx8RIeyZ 1QAGpRiBWUQ2yMtYu1+Ci1P+CpCEO77HqDJ/dgCM3C5u5dbkrhpni6KAC9kou/t0g9M4 +iaURw0AO+TljvyTP1Bin6ymGxl5cUjb1ebkeb8DQMzuve1A0sIF8hR/YJox1dBLGDaK VUO6J6XReUDdl74pyCSVgEA7P0odxosm7xYGsVkEU5o0++acS+SHP6K4ZawQmuzlxFwX s2faXvZlbLCnzi2jVDqvHyPffa0X6Ns2suKZopeDFI2ePfQeoiyzj8bvoFtBNhAxFfxk PgxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jLMjBC8As2Qf0j/kKO70QMZc6RPo1kSmruI7dUHbIeQ=; b=VtEml3jtx7qC786mRhQT5ay2yIzpeo5ENWS6iqhPQQlTWKhxP3XCd940ae9aahomvm 3jlCPdMF+utRDpapLFf8oFbfjTE59hhRRoJJtNnSMRYrFssA/tPimVzPhLT4SREyFBVu y+Of2ACj68dbYFkRpSRgKdf3/rT1oJ0P/qc//JgMjq+iVW009zmThwxyQIbi9mirxxD0 48fU5GpxeUYgjSxeA2f8mKn6IG2u7aLgQQcGBRDJuBKt47XWNf+/JOyciwCCYvj+qPaV KVGOdjOqDR8rXLLxkhjClRpDsrw9nZwNkHKEi2j5jjKCsDeML81CEKvR4Z6yNe3l0UbA ktwg== X-Gm-Message-State: AOAM5312tr3qtqG+0UyDvaOJp3Ttg0vJ2x2hj/tUkMQuGoKJuD0r1F+F Y0IvKgnNhGGorph6+uQ6f19CJZtOH2Bz9A== X-Google-Smtp-Source: ABdhPJx41zkXfSq4QMqPaWfRuJ6TmUuyQnjgSvK1VjGCcLaqLArAvlbkrVqnIoltIdOpWqxXQM3fRA== X-Received: by 2002:a17:90a:598d:: with SMTP id l13mr19287351pji.8.1635614418226; Sat, 30 Oct 2021 10:20:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 45/66] target/arm: Implement arm_cpu_record_sigbus Date: Sat, 30 Oct 2021 10:16:14 -0700 Message-Id: <20211030171635.1689530-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635619334100100001 Content-Type: text/plain; charset="utf-8" Because of the complexity of setting ESR, re-use the existing arm_cpu_do_unaligned_access function. This means we have to handle the exception ourselves in cpu_loop, transforming it to the appropriate signal. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 2 ++ linux-user/aarch64/cpu_loop.c | 12 +++++++++--- linux-user/arm/cpu_loop.c | 30 ++++++++++++++++++++++++++---- target/arm/cpu.c | 1 + target/arm/cpu_tcg.c | 1 + target/arm/tlb_helper.c | 6 ++++++ 6 files changed, 45 insertions(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 5a7aaf0f51..89f7610ebc 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -548,6 +548,8 @@ static inline bool arm_extabort_type(MemTxResult result) void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, MMUAccessType access_type, bool maperr, uintptr_t ra); +void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr, + MMUAccessType access_type, uintptr_t ra); #else bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 034b737435..97e0728b67 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -79,7 +79,7 @@ void cpu_loop(CPUARMState *env) { CPUState *cs =3D env_cpu(env); - int trapnr, ec, fsc, si_code; + int trapnr, ec, fsc, si_code, si_signo; abi_long ret; =20 for (;;) { @@ -121,20 +121,26 @@ void cpu_loop(CPUARMState *env) fsc =3D extract32(env->exception.syndrome, 0, 6); switch (fsc) { case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + si_signo =3D TARGET_SIGSEGV; si_code =3D TARGET_SEGV_MAPERR; break; case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + si_signo =3D TARGET_SIGSEGV; si_code =3D TARGET_SEGV_ACCERR; break; case 0x11: /* Synchronous Tag Check Fault */ + si_signo =3D TARGET_SIGSEGV; si_code =3D TARGET_SEGV_MTESERR; break; + case 0x21: /* Alignment fault */ + si_signo =3D TARGET_SIGBUS; + si_code =3D TARGET_BUS_ADRALN; + break; default: g_assert_not_reached(); } - - force_sig_fault(TARGET_SIGSEGV, si_code, env->exception.vaddre= ss); + force_sig_fault(si_signo, si_code, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index ae09adcb95..01cb6eb534 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -25,6 +25,7 @@ #include "cpu_loop-common.h" #include "signal-common.h" #include "semihosting/common-semi.h" +#include "target/arm/syndrome.h" =20 #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r =3D get_user_u32((x), (gaddr)); \ @@ -280,7 +281,7 @@ static bool emulate_arm_fpa11(CPUARMState *env, uint32_= t opcode) void cpu_loop(CPUARMState *env) { CPUState *cs =3D env_cpu(env); - int trapnr; + int trapnr, si_signo, si_code; unsigned int n, insn; abi_ulong ret; =20 @@ -423,9 +424,30 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* XXX: check env->error_code */ - force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, - env->exception.vaddress); + /* For user-only we don't set TTBCR_EAE, so look at the FSR. */ + switch (env->exception.fsr & 0x1f) { + case 0x1: /* Alignment */ + si_signo =3D TARGET_SIGBUS; + si_code =3D TARGET_BUS_ADRALN; + break; + case 0x3: /* Access flag fault, level 1 */ + case 0x6: /* Access flag fault, level 2 */ + case 0x9: /* Domain fault, level 1 */ + case 0xb: /* Domain fault, level 2 */ + case 0xd: /* Permision fault, level 1 */ + case 0xf: /* Permision fault, level 2 */ + si_signo =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_ACCERR; + break; + case 0x5: /* Translation fault, level 1 */ + case 0x7: /* Translation fault, level 2 */ + si_signo =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_MAPERR; + break; + default: + g_assert_not_reached(); + } + force_sig_fault(si_signo, si_code, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a18a58ca0..a211804fd3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2035,6 +2035,7 @@ static const struct TCGCPUOps arm_tcg_ops =3D { =20 #ifdef CONFIG_USER_ONLY .record_sigsegv =3D arm_cpu_record_sigsegv, + .record_sigbus =3D arm_cpu_record_sigbus, #else .tlb_fill =3D arm_cpu_tlb_fill, .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 7b3bea2fbb..13d0e9b195 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -902,6 +902,7 @@ static const struct TCGCPUOps arm_v7m_tcg_ops =3D { =20 #ifdef CONFIG_USER_ONLY .record_sigsegv =3D arm_cpu_record_sigsegv, + .record_sigbus =3D arm_cpu_record_sigbus, #else .tlb_fill =3D arm_cpu_tlb_fill, .cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index dc5860180f..12a934e924 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -213,4 +213,10 @@ void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr, cpu_restore_state(cs, ra, true); arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi); } + +void arm_cpu_record_sigbus(CPUState *cs, vaddr addr, + MMUAccessType access_type, uintptr_t ra) +{ + arm_cpu_do_unaligned_access(cs, addr, access_type, MMU_USER_IDX, ra); +} #endif /* !defined(CONFIG_USER_ONLY) */ --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635617687528417.76533820563134; Sat, 30 Oct 2021 11:14:47 -0700 (PDT) Received: from localhost ([::1]:49428 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgssQ-0002WR-7T for importer@patchew.org; Sat, 30 Oct 2021 14:14:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58662) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1o-0001Sz-AA for qemu-devel@nongnu.org; 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[174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fbekWwHWkYvCfsIkbs+I86iCi1VerGNgnv3kr2JgTV8=; b=vIbEBM7aaprS8d8s+b6EXzgU/N8gttVa9GjS1Xncdw9QArplZ7nQaUreYg4YJaaEvY tG1XZCLBGdKaFAZLqy27nU1Xd3YkTGsRNHQbkOnYr+56X6tJaJ7J3ZTAhhf9+UQU+BI8 SDBZkcVGutSmb3J9jTDTUjnOsN/hHXOFtOOYm4lDhZEWB7K1cDln//Kw1adOlN0JBVaE 5nyXU6Nk/ndddXlZ6UOC5Q8u7dMRDcRlFX7Ze1MdGbW2Besyl0U5YzPH5R3GtEwi/hpU EW6lyizOfbeup6iOoTSJP11rFBFMPFQwAfs/7Sk9DB1Q3EK/U55XEsQP6SceGpu3Sbvh 8HeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fbekWwHWkYvCfsIkbs+I86iCi1VerGNgnv3kr2JgTV8=; b=EwMckoGEzDNHW40tNtEI7JKO1tr+EwvppyZ7azuwNq93497NisHMWhGLK6y1JV32NU v+FFIMpGbMxjnee2L6IKpTA0H91QT1L0Eo5g+ukV9TrasXWVHKbWHRjE5KewAbnlo0S5 g2gjwHqEz1OSQDRlG1qBB9d5mvLSX9pvp+UNgbycZTn0OPugm6gqZ3LDx/KZ/U2WnVvP tCSqNp7EYNL4DZzB2FZxp59CEGb+my8SPeWLTJrIC4drMyEk1j9QLt2Wt1k6O9tQhfZ+ 9/UGvj7lZsoSV1l47QajCa+WA1lT0P6CU+2Yx3JJbM5N3OpVIJVVX/VQ1Y0FWjkFDgr8 iaZg== X-Gm-Message-State: AOAM5331tQtq+kAFMwuwPGY7pAj4Ra43Z4/bsWFteztoRIIYjAk6u+Wc u5KXAeltLxvtATYAZjLSpfKw9Pjn2HyPTw== X-Google-Smtp-Source: ABdhPJx/zGx12wMvzTQftO4eLQlGRq2oft7mLvDizKfGh4deWW/YBpML28XOHes98NeSqKBRqwkxNA== X-Received: by 2002:a05:6a00:851:b0:47c:288c:88f7 with SMTP id q17-20020a056a00085100b0047c288c88f7mr18427405pfk.29.1635614419097; Sat, 30 Oct 2021 10:20:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 46/66] linux-user/hppa: Remove EXCP_UNALIGN handling Date: Sat, 30 Oct 2021 10:16:15 -0700 Message-Id: <20211030171635.1689530-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635617687968100001 Content-Type: text/plain; charset="utf-8" We will raise SIGBUS directly from cpu_loop_exit_sigbus. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- linux-user/hppa/cpu_loop.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index e0a62deeb9..375576c8f0 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -144,13 +144,6 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_f =3D env->gr[31]; env->iaoq_b =3D env->gr[31] + 4; break; - case EXCP_UNALIGN: - info.si_signo =3D TARGET_SIGBUS; - info.si_errno =3D 0; - info.si_code =3D 0; - info._sifields._sigfault._addr =3D env->cr[CR_IOR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_ILL: case EXCP_PRIV_OPR: case EXCP_PRIV_REG: --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635616951135526.6504847085515; Sat, 30 Oct 2021 11:02:31 -0700 (PDT) Received: from localhost ([::1]:52908 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsgX-0002bd-VE for importer@patchew.org; Sat, 30 Oct 2021 14:02:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58670) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1o-0001T2-N3 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:26 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:43931) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1l-0002B3-Qk for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:24 -0400 Received: by mail-pl1-x62d.google.com with SMTP id y1so8902406plk.10 for ; Sat, 30 Oct 2021 10:20:20 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mTKdaHiEpe60z+ThGKt8c3K8jQRQXSW+5obPKHUiPMs=; b=vRHSQTBxihlddshAA986+iSiR0Nil9TNfH5cy5j0mEEUv7Ovted3tzIZ0QxxEN9a9z Qd161FDUp6F6m2S1FkbGD1emlcTsvxBj26uGgDDroKILuRZEkwVAgJ/QeweFiw4uAaHC oW1a2X+BgQEOv90XhrTPa2BGYJND0tJU+fh9cKMe2hqc0DU8FCYNiGuELJqkJBG/7GCt i0s8s7Te+E5Fx+QEPGGj3lrxUk5DTgDfcc2VLf1DnKKGYGITFwa3r7ah/b3splqM2KUQ fIi9IrX1NxqGS1LKDlu963ChISm5bxuBWJYpYsSwV22m5m2vMzrHIP+pGcdXosezmADW DhoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mTKdaHiEpe60z+ThGKt8c3K8jQRQXSW+5obPKHUiPMs=; b=1UgGUAjj7v1Xzwh1seR/CK98by1FWoZr0e6NsCGKr4/PjZd8sIOK4M78MhGFgW5sdZ efzBneaxQZ2siVfmfsLEyzpBklg7nv7zehw75+hPOG+w9xuHtXcLccTEhMdw64y9pl4P OKfLmESwP2ed53sAtcLLCkTa8y+oArSRqBOxZGbOrUEJfIzG2IM5FKzrkdmueUKKV7T/ IxP4CT0w9Pdlaay6CRd57qbFXWaVs7z0O/M8sNoiKxNAcPbAqPl8ASlfDYVudv3309J7 G1e6eY4wQwOSyfDHJoFRhxbCK7Y/v29Dg4bCv9pI4h67/H1euOdyN/bFbj36NSZCOavW G5sA== X-Gm-Message-State: AOAM533SJ20nVem/10Aj7691IRKsWKmsuLE6PKzec/baWi6iZfPnvpoW E46Hh8E9p0PH5v6w0eAA491f2cuL9L99Kg== X-Google-Smtp-Source: ABdhPJz4zl/P9N8T9mjIsif7Tw1criAHj+nqjOEwR0Ow6vz3BZR64Fccd37oijYWOmOCMAa/wNPrGg== X-Received: by 2002:a17:90b:4b4c:: with SMTP id mi12mr19311342pjb.57.1635614419955; Sat, 30 Oct 2021 10:20:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 47/66] target/microblaze: Do not set MO_ALIGN for user-only Date: Sat, 30 Oct 2021 10:16:16 -0700 Message-Id: <20211030171635.1689530-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635616951705100001 Content-Type: text/plain; charset="utf-8" The kernel will fix up unaligned accesses, so emulate that by allowing unaligned accesses to succeed. Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 437bbed6d6..2561b904b9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -722,6 +722,7 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int = ra, int rb) } #endif =20 +#ifndef CONFIG_USER_ONLY static void record_unaligned_ess(DisasContext *dc, int rd, MemOp size, bool store) { @@ -734,6 +735,7 @@ static void record_unaligned_ess(DisasContext *dc, int = rd, =20 tcg_set_insn_start_param(dc->insn_start, 1, iflags); } +#endif =20 static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, int mem_index, bool rev) @@ -755,12 +757,19 @@ static bool do_load(DisasContext *dc, int rd, TCGv ad= dr, MemOp mop, } } =20 + /* + * For system mode, enforce alignment if the cpu configuration + * requires it. For user-mode, the Linux kernel will have fixed up + * any unaligned access, so emulate that by *not* setting MO_ALIGN. + */ +#ifndef CONFIG_USER_ONLY if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { record_unaligned_ess(dc, rd, size, false); mop |=3D MO_ALIGN; } +#endif =20 tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop); =20 @@ -901,12 +910,19 @@ static bool do_store(DisasContext *dc, int rd, TCGv a= ddr, MemOp mop, } } =20 + /* + * For system mode, enforce alignment if the cpu configuration + * requires it. For user-mode, the Linux kernel will have fixed up + * any unaligned access, so emulate that by *not* setting MO_ALIGN. + */ +#ifndef CONFIG_USER_ONLY if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { record_unaligned_ess(dc, rd, size, true); mop |=3D MO_ALIGN; } +#endif =20 tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); =20 --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635618463715310.4526027297155; Sat, 30 Oct 2021 11:27:43 -0700 (PDT) Received: from localhost ([::1]:42738 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgt4w-00018k-Ol for importer@patchew.org; Sat, 30 Oct 2021 14:27:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58730) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1s-0001UW-5f for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:28 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:43932) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1m-0002Bt-PL for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:25 -0400 Received: by mail-pl1-x62e.google.com with SMTP id y1so8902423plk.10 for ; Sat, 30 Oct 2021 10:20:21 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=54O7y5F6cil48JbVjJeuP4tBSWG4MHFPBxntrZflWpI=; b=ibu/o+rJIff6CuW/WKtJapnHSvuNL5Uywd2jck1FIAu6ae0RKiWodiNq+f/waHzgbj WPR9ira2DgQBK1GnIIXEYYS+qX8vn7Y6fuGahGvMbzlAn0GyEf4RAj3nP5sU7zdKle3k vZwd2sWX74unrVwzksgvQrlJllvPBTUXkzmN8pnY7nTcELiXICB3TCAvh2hHUclgl7yv repJ4EBmQGWo8NB5KBIMKfmNqkfYthYCMYEe+zapjr/v7pY/BRJbD+Q7TqpaJan9BVc3 uNdVnAf6R9fRpONExFqpJarm8l63KHmkQAVXFINlj84LcqI4oOU6+X0X1UGOsbW/3a+M GIEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=54O7y5F6cil48JbVjJeuP4tBSWG4MHFPBxntrZflWpI=; b=Ai75KX8c0s6Xn736mV9uR56ZH+8ZgaHutoPCtlYXTcEELh7HGHx9C2SW5tGiAifKqm BXSWZ6Z5dOHtG10xJ3TtHMq+nf+74onBdairEIJH4tJi73q6VIllGaJBjGY7bP5mON5/ JAhObkSesuyMxFo6uJv5Rci6LjhDuUmUewjB1whIx8LhTCudgWqChsWeZ/pbVac/tMnb EjBANVXvK9+K5g68KoWs0gxLjF3QI//W0oY5/uvPqytab7StMVt8CB3bSmjdLIRX+Cko Tp+DDhYnictFSzSJKNDIXvF42M8z2APX76Gy8fLE1AMEYDdIjiGS+c64jNeVD13IknpV m6dw== X-Gm-Message-State: AOAM532oxoR6uvaE3hR+VCAAyvYWUINY9TejIKlYTqAZOoKHk0eW+TFT jUEct8U3Ye0uNjiYEt5L09KXhW8DyTdMpw== X-Google-Smtp-Source: ABdhPJwiFa9bZgXS50vy12J1Nakd/AEbZ0l1u9mYRenz9gWUpKJMuFVH3KMtuwTxOOQcqxeYVn/8lA== X-Received: by 2002:a17:90b:350c:: with SMTP id ls12mr6529680pjb.197.1635614421083; Sat, 30 Oct 2021 10:20:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 48/66] target/ppc: Move SPR_DSISR setting to powerpc_excp Date: Sat, 30 Oct 2021 10:16:17 -0700 Message-Id: <20211030171635.1689530-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635618465834100001 Content-Type: text/plain; charset="utf-8" By doing this while sending the exception, we will have already done the unwinding, which makes the ppc_cpu_do_unaligned_access code a bit cleaner. Update the comment about the expected instruction format. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/ppc/excp_helper.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index b7d1767920..88a8de4b80 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -454,13 +454,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int = excp_model, int excp) break; } case POWERPC_EXCP_ALIGN: /* Alignment exception = */ - /* Get rS/rD and rA from faulting opcode */ /* - * Note: the opcode fields will not be set properly for a - * direct store load/store, but nobody cares as nobody - * actually uses direct store segments. + * Get rS/rD and rA from faulting opcode. + * Note: We will only invoke ALIGN for atomic operations, + * so all instructions are X-form. */ - env->spr[SPR_DSISR] |=3D (env->error_code & 0x03FF0000) >> 16; + { + uint32_t insn =3D cpu_ldl_code(env, env->nip); + env->spr[SPR_DSISR] |=3D (insn & 0x03FF0000) >> 16; + } break; case POWERPC_EXCP_PROGRAM: /* Program exception = */ switch (env->error_code & ~0xF) { @@ -1462,14 +1464,9 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr= vaddr, int mmu_idx, uintptr_t retaddr) { CPUPPCState *env =3D cs->env_ptr; - uint32_t insn; - - /* Restore state and reload the insn we executed, for filling in DSISR= . */ - cpu_restore_state(cs, retaddr, true); - insn =3D cpu_ldl_code(env, env->nip); =20 cs->exception_index =3D POWERPC_EXCP_ALIGN; - env->error_code =3D insn & 0x03FF0000; - cpu_loop_exit(cs); + env->error_code =3D 0; + cpu_loop_exit_restore(cs, retaddr); } #endif --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635618476084426.2877852652074; Sat, 30 Oct 2021 11:27:56 -0700 (PDT) Received: from localhost ([::1]:43368 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgt58-0001Zm-Vy for importer@patchew.org; Sat, 30 Oct 2021 14:27:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58734) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1s-0001UY-6j for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:28 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:35512) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1o-0002C3-1v for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:25 -0400 Received: by mail-pf1-x42d.google.com with SMTP id s5so753007pfg.2 for ; Sat, 30 Oct 2021 10:20:22 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hDIIDmSt3XkX7dozNp8YyanBuOQiSpBj16JErrhb+ZE=; b=lrdYcKbzQ0c+F3yUg3gPnHdd01mr+Zsevis/Hpk6OAGdzCnjHeHgZDjjBKuAgUgLuZ x+sio0YitJs9t7SbbuGirw48WVgAZntqXU+zXzeIadwZjuhz99q5kXIK9dv9NtCTnqvP nRo8oPvg6H2ujVWC7IZDPydxlIz7lsFqz7joHIJ1MrYn3RuvUuec9wBQnNZJbWUE1XA/ rxKl0KbYUg2Bvonb3bKkFRklpY3SqunsQDVn+dwVE9jUA6FoBFZMEopBGeVyHI/NNP7s 4sMdiESoiT3YdkIfD2dDgDs6SkTOZycahkSyMDTfRPwrXSmE50bjlYlxa4QKFrK26j+F kUXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hDIIDmSt3XkX7dozNp8YyanBuOQiSpBj16JErrhb+ZE=; b=4ES7mHGrtUAKMDMZDs+1uQ80w9jpmkGAM66ne2aerKX7uu55ugsSwglbRGrFKhQp/V qxn6u+vEFa8q8ic3osoGicx7YBjg1948zev/tW/4MI9Tbwn8xw6OC7I4uCv4EtDho9Gt QacTdq3YvPYgNDHuuboJiXnbWcpIGJqkQfSTSvSg+RMVvRz8xXidnqjoiP+y4/+pXo5l FglDwYFa5NzMLgCwl5kXoTTib/6QBW0xn7SRTj9+GaILb/YuQyXvA482WVaPgC600674 v78qLAy2ZUjuhAI/pww+0ZZK1QqFqrJ3vdY7YOjDhYPgjoufF0yJF5uznMHiAA5JKyfR x8Mw== X-Gm-Message-State: AOAM533HrIccwWp4F6RFcOpHUKRrkT/ouBL8xTmPc00D5G/XFnzF+pn0 4NdK/bBu9IpPhXsvG8JorB3KbeSa2oZSPg== X-Google-Smtp-Source: ABdhPJxkfzS/EGK4MQLC2fo0Ek06uyWpr5cP1cXzqu4pTjUjtlnrco7OeSuey0Gp+woDP5ExxbalGw== X-Received: by 2002:a62:5304:0:b0:44c:719c:a2c with SMTP id h4-20020a625304000000b0044c719c0a2cmr17729993pfb.13.1635614421984; Sat, 30 Oct 2021 10:20:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 49/66] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Date: Sat, 30 Oct 2021 10:16:18 -0700 Message-Id: <20211030171635.1689530-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , laurent@vivier.eu, f4bug@amsat.org, qemu-ppc@nongnu.org, alex.bennee@linaro.org, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635618478350100003 Content-Type: text/plain; charset="utf-8" We ought to have been recording the virtual address for reporting to the guest trap handler. Cc: qemu-ppc@nongnu.org Reviewed-by: Warner Losh Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/ppc/excp_helper.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 88a8de4b80..e568a54536 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1465,6 +1465,20 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr= vaddr, { CPUPPCState *env =3D cs->env_ptr; =20 + switch (env->mmu_model) { + case POWERPC_MMU_SOFT_4xx: + case POWERPC_MMU_SOFT_4xx_Z: + env->spr[SPR_40x_DEAR] =3D vaddr; + break; + case POWERPC_MMU_BOOKE: + case POWERPC_MMU_BOOKE206: + env->spr[SPR_BOOKE_DEAR] =3D vaddr; + break; + default: + env->spr[SPR_DAR] =3D vaddr; + break; + } + cs->exception_index =3D POWERPC_EXCP_ALIGN; env->error_code =3D 0; cpu_loop_exit_restore(cs, retaddr); --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635618235060509.35560180893106; Sat, 30 Oct 2021 11:23:55 -0700 (PDT) Received: from localhost ([::1]:36120 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgt1G-00052i-2x for importer@patchew.org; Sat, 30 Oct 2021 14:23:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58732) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1s-0001UX-6O for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:28 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:36831) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1o-0002CG-3k for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:26 -0400 Received: by mail-pf1-x433.google.com with SMTP id m26so12324323pff.3 for ; Sat, 30 Oct 2021 10:20:23 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O2Pwh8dMK2GW2V5gEng3hQsybzKfwzmJDjUzbvltEB4=; b=nqrF955v9kb7EQxVqymq9d1/c8X+v7cVJQSpwUXgu73Vozq4D+PfC+T9P/SktMWf94 sHeDyWGYE045aJO3JpAmQCp8MAOC/4UzfxdHZFHrHmeemht8Uf6+bGYFI5H4aNMJV10E tt3vazMguDgzRXwByvw2u5wcGgNoA9GmYMNRPNjuFiLXclBrgGFj1CoAIeD66R9kj2Df zT2bWBvgBdJAui1IJet3KUDjN47Pkh10Te3lHu9yL9SLfd+0UDMxF8FUb/sA13NK8q7K CBYvUOPzCxAdHRfZBqmmAY6APfXIfC/qoiMbCT1/+XA7GUJWghXrNNlyBc4I0bvCcCsZ wTnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O2Pwh8dMK2GW2V5gEng3hQsybzKfwzmJDjUzbvltEB4=; b=K+CRg1wrDKQr+haatITe1CrQ8EDNRHVC12Sn4GProODGTBC56jRBdIvUC7t8ZG7n5Z HlSO50zFkfCa/GxjygXt6CVkZfsoTPefyECltiMNm51Onohsz5/CEq4OaPgif8eQGYo0 332Pfb9CEHZXJHt3eoFjPdt0pbVImgwGQVVdpW7PuPxKQA1+C8XZh9RkrlKReu3bpS81 Qe2+xUVUrB1mHTuq7+oWCIWEYy4wbY269wWfCiCel8Cb1aX1w01bTaSl+D94yojrcsLv fhIxsjef9lJC5RqH1yXbbVmdjs0YS9+VPUDG0A2bD1PtUAxKAJt7ga4p3mBnCwe8BUcV GF3g== X-Gm-Message-State: AOAM533Sy3d7GTgMK+Cw2SPExVSxzKRjN3ZlUlzZYCzG2xHnmgUkRiV2 Me6t8aOXJ6Hpe8526I4aBbD2M7ofMJ+KiA== X-Google-Smtp-Source: ABdhPJxzjWx7hiKOGnVuE6bUVBsTA2Q/WpwedKbN7Ix9wE1wqetW8a3SYpwwiRdsMSxQflrkOyvSJg== X-Received: by 2002:a63:b519:: with SMTP id y25mr13535863pge.237.1635614422858; Sat, 30 Oct 2021 10:20:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 50/66] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu Date: Sat, 30 Oct 2021 10:16:19 -0700 Message-Id: <20211030171635.1689530-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635618236029100003 This is not used by, nor required by, user-only. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/ppc/internal.h | 8 +++----- target/ppc/excp_helper.c | 8 +++----- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 339974b7d8..6aa9484f34 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -211,11 +211,6 @@ void helper_compute_fprf_float16(CPUPPCState *env, flo= at16 arg); void helper_compute_fprf_float32(CPUPPCState *env, float32 arg); void helper_compute_fprf_float128(CPUPPCState *env, float128 arg); =20 -/* Raise a data fault alignment exception for the specified virtual addres= s */ -void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; - /* translate.c */ =20 int ppc_fixup_cpu(PowerPCCPU *cpu); @@ -291,6 +286,9 @@ void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr, bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; #endif =20 #endif /* PPC_INTERNAL_H */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index e568a54536..17607adbe4 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1454,11 +1454,8 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_= ulong rb) =20 book3s_msgsnd_common(pir, PPC_INTERRUPT_DOORBELL); } -#endif -#endif /* CONFIG_TCG */ -#endif +#endif /* TARGET_PPC64 */ =20 -#ifdef CONFIG_TCG void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) @@ -1483,4 +1480,5 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr = vaddr, env->error_code =3D 0; cpu_loop_exit_restore(cs, retaddr); } -#endif +#endif /* CONFIG_TCG */ +#endif /* !CONFIG_USER_ONLY */ --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635618003884254.74886832538232; Sat, 30 Oct 2021 11:20:03 -0700 (PDT) Received: from localhost ([::1]:57678 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsxW-0008F6-Qi for importer@patchew.org; Sat, 30 Oct 2021 14:20:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58736) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1s-0001UZ-7W for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:28 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:38676) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1o-0002CS-Qj for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:26 -0400 Received: by mail-pf1-x42f.google.com with SMTP id l1so5883274pfu.5 for ; Sat, 30 Oct 2021 10:20:24 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QuBUrcbK5IHnv9/MH2TrxQjSj4HGL7JlA8tE+X8E85A=; b=uzGAZOTROIjYZtqTo5srpp6DR2S9fF4wTxV/rSJiYJywDociAz4L0UgYP9V2T3OckI lx5i8BWjSoENUNMzCS94pcyvkPM+uYX/rATHhfZtL80Jn35+mJ9Vu+VqyC9q7sYkrcKy CFSjTi70bUQx94gGyNOvlj/Ova1WjkWLDCP0Q6Sg8A8RVELRMKrvmnsr7HD49amRVpj3 hC4M+VA3axpV6Hyxond4Ocz22jHYkRVVPKbGYN51xXXigKsu4+QBmMCWtAu6f7WVfUsJ 87UJnt2dKcqcsA9iLPAL4za67mLvicQ6yR7JgHgWkeESWCXokxIoKynvk5ruT4rG4Tta LcMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QuBUrcbK5IHnv9/MH2TrxQjSj4HGL7JlA8tE+X8E85A=; b=HOq3xEJ1VbJkjJsovYhgxeMywzU9IqOf0O6h8dEmDgrI+v5/gUsyFIg8ZSy2CSboft kkwCrWyE860uUog9OeH0v03+53p1jrvg1CDOi7k0cX7GWDOCM+QLwcrFnxxWv7k5Dd8M 1P17A1RPR5539I320PLnRfiMnglqnlBW1N6N1CFWxYtO36CJCSuAP2B0zmnArrrf6tme HgGwUN9WbCXeQPLoEdqjnghrGDXttZ4hLxovKPYXA1topsC3vPZBtW/gupU8N4Sg7iWF cW9clwiLoIfMjx8wasamjlW/NRiW9xl5hzBeuNuKZ1pki4AnNUDv75yPp243PLOXOtK/ eclg== X-Gm-Message-State: AOAM5339sAi9CxjACok+0H6Raxls2h86zl5y0LaCeT7H5baVzGLhip5m jQ2ZYp40sao3hJqP7ZEB1acXNfZtN436VA== X-Google-Smtp-Source: ABdhPJyif/41dccvglP3ypyx96BcjQVFy39VCuq9UvwTwJDGGzMio/TEIOhkzZ7a3xfyUnfHK/zlQQ== X-Received: by 2002:a62:158b:0:b0:480:7e39:91a9 with SMTP id 133-20020a62158b000000b004807e3991a9mr3931976pfv.64.1635614423538; Sat, 30 Oct 2021 10:20:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 51/66] linux-user/ppc: Remove POWERPC_EXCP_ALIGN handling Date: Sat, 30 Oct 2021 10:16:20 -0700 Message-Id: <20211030171635.1689530-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SUBJ_WIPE_DEBT=1.004 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635618005113100001 Content-Type: text/plain; charset="utf-8" We will raise SIGBUS directly from cpu_loop_exit_sigbus. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- linux-user/ppc/cpu_loop.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index 840b23736b..483e669300 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -162,14 +162,6 @@ void cpu_loop(CPUPPCState *env) cpu_abort(cs, "External interrupt while in user mode. " "Aborting\n"); break; - case POWERPC_EXCP_ALIGN: /* Alignment exception = */ - /* XXX: check this */ - info.si_signo =3D TARGET_SIGBUS; - info.si_errno =3D 0; - info.si_code =3D TARGET_BUS_ADRALN; - info._sifields._sigfault._addr =3D env->nip; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case POWERPC_EXCP_PROGRAM: /* Program exception = */ case POWERPC_EXCP_HV_EMU: /* HV emulation = */ /* XXX: check this */ --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635617160325771.2799002186607; Sat, 30 Oct 2021 11:06:00 -0700 (PDT) Received: from localhost ([::1]:33156 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsjv-0008Gp-9v for importer@patchew.org; Sat, 30 Oct 2021 14:05:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58762) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1u-0001Vs-Iv for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:30 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:37753) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1q-0002Cg-Gy for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:29 -0400 Received: by mail-pg1-x533.google.com with SMTP id s136so12999171pgs.4 for ; Sat, 30 Oct 2021 10:20:25 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RjnbfjA/SuXJ4jF6cq76qF1xRJpDxH7O+xJW5W8IXoI=; b=kDp7EotzZACyF3SS+FYFA1VutgNiis3RGFwomzqFtaYPOrybNEE9ztKj08ZL01GaCQ fL0f1vreOznnNz9pbKRu6Hqdh9qVqaaIbjNi8+A9of3+GhRQopO0v2rmDAfL7bt2A/hr 0FgD4JmbLqBaK2ohLNAksus14gt5jnyMxEpYuReEeesCQhCQ/kp8g4mKxsUhQs1YqlQD JW1ucClD7XPFvx1hxr3LMZ7bETqbItSayDSVyWMgH4kXpCb/nPA0uihApPnFgiRIzYqw G4pXu24RRnDbPhJ09kt7DOMoDvf4iC2QcKPx5ikc5YOAR6JEVzYKv1a+7XoiVOoViGrk P78Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RjnbfjA/SuXJ4jF6cq76qF1xRJpDxH7O+xJW5W8IXoI=; b=vo62B0YbJcU5EM5TYgiqTbsYifIc8z2mNI7L3ovUztd3LMlftO045UkIGpY4x5dqCm TLwDbnAzXfkBrJhJAIYaUhuVhoCu/GjGf6IyEmfX/6zKQh+otb/vVPI1pjc96wvC9Klk 2LUxNz3C41zZo9gRNDZU8wA7Xy2bmTXNfAYLguaQ+7aTrBrUoIIePpvGstrxRPhC97DC KQ7DAR1mdm8k0VY4DlcpRHxuCTIK1YXk6mBVuStIwZVprNv0SWOx8L8zirLmIr191uPh 7tHJGGnVsREu1UUFdv3KUdn+ZIwXmS8PBKkEqalzObOtsLcn6DXu9BYEs/Rrn8RR1SIh 6b2g== X-Gm-Message-State: AOAM531hbOBxB4d6ul81ygHbXgg0DD7y+T7gw9TEyUThWjDyZ2dgWoBm QS+fKp0K4CLxvdEu5zWCoS8uqHTzXEcRjQ== X-Google-Smtp-Source: ABdhPJx/6mqiUr12ygcIyfQxZ78u1wTwz9rB3pP8RI5iP0wmLKZRG9J8evf3PUO+Qn3Sm7viLE72Sg== X-Received: by 2002:a05:6a00:230e:b0:44c:4f2d:9b00 with SMTP id h14-20020a056a00230e00b0044c4f2d9b00mr18461349pfh.24.1635614424408; Sat, 30 Oct 2021 10:20:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 52/66] target/s390x: Implement s390x_cpu_record_sigbus Date: Sat, 30 Oct 2021 10:16:21 -0700 Message-Id: <20211030171635.1689530-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635617161342100001 For s390x, the only unaligned accesses that are signaled are atomic, and we don't actually want to raise SIGBUS for those, but instead raise a SPECIFICATION error, which the kernel will report as SIGILL. Split out a do_unaligned_access function to share between the user-only s390x_cpu_record_sigbus and the sysemu s390x_do_unaligned_access. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/s390x/s390x-internal.h | 8 +++++--- target/s390x/cpu.c | 1 + target/s390x/tcg/excp_helper.c | 27 ++++++++++++++++++++------- 3 files changed, 26 insertions(+), 10 deletions(-) diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 163aa4f94a..1a178aed41 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -270,18 +270,20 @@ ObjectClass *s390_cpu_class_by_name(const char *name); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); -void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; =20 #ifdef CONFIG_USER_ONLY void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, MMUAccessType access_type, bool maperr, uintptr_t retaddr); +void s390_cpu_record_sigbus(CPUState *cs, vaddr address, + MMUAccessType access_type, uintptr_t retaddr); #else bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; #endif =20 =20 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 593dda75c4..ccdbaf84d5 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -269,6 +269,7 @@ static const struct TCGCPUOps s390_tcg_ops =3D { =20 #ifdef CONFIG_USER_ONLY .record_sigsegv =3D s390_cpu_record_sigsegv, + .record_sigbus =3D s390_cpu_record_sigbus, #else .tlb_fill =3D s390_cpu_tlb_fill, .cpu_exec_interrupt =3D s390_cpu_exec_interrupt, diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index b923d080fc..4e7648f301 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -82,6 +82,19 @@ void HELPER(data_exception)(CPUS390XState *env, uint32_t= dxc) tcg_s390_data_exception(env, dxc, GETPC()); } =20 +/* + * Unaligned accesses are only diagnosed with MO_ALIGN. At the moment, + * this is only for the atomic operations, for which we want to raise a + * specification exception. + */ +static void QEMU_NORETURN do_unaligned_access(CPUState *cs, uintptr_t reta= ddr) +{ + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + + tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr); +} + #if defined(CONFIG_USER_ONLY) =20 void s390_cpu_do_interrupt(CPUState *cs) @@ -106,6 +119,12 @@ void s390_cpu_record_sigsegv(CPUState *cs, vaddr addre= ss, cpu_loop_exit_restore(cs, retaddr); } =20 +void s390_cpu_record_sigbus(CPUState *cs, vaddr address, + MMUAccessType access_type, uintptr_t retaddr) +{ + do_unaligned_access(cs, retaddr); +} + #else /* !CONFIG_USER_ONLY */ =20 static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx) @@ -593,17 +612,11 @@ void s390x_cpu_debug_excp_handler(CPUState *cs) } } =20 -/* Unaligned accesses are only diagnosed with MO_ALIGN. At the moment, - this is only for the atomic operations, for which we want to raise a - specification exception. */ void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - S390CPU *cpu =3D S390_CPU(cs); - CPUS390XState *env =3D &cpu->env; - - tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr); + do_unaligned_access(cs, retaddr); } =20 static void QEMU_NORETURN monitor_event(CPUS390XState *env, --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635619452213857.1768152785862; Sat, 30 Oct 2021 11:44:12 -0700 (PDT) Received: from localhost ([::1]:46234 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgtKt-0005m9-37 for importer@patchew.org; Sat, 30 Oct 2021 14:44:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1v-0001Yw-JG for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:32 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:39808) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1r-0002Cr-UM for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:30 -0400 Received: by mail-pg1-x52b.google.com with SMTP id g184so12997664pgc.6 for ; Sat, 30 Oct 2021 10:20:26 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3/CJUXQvBCEoPlihnnAPxMwhS0SfN83B4jFLy6O6YSI=; b=x4oHy7QXJG1FCqQUvcaotGySnL91ekJfcTP+asUWAsssuCANDKA+Fveknp0lIxRMp3 nNSYLzfqTjLaOawH8INsfwtlASoBH8fsd0ZYVn+0B9267108/ONTeoprcG4FDPqxjmDl 9QdD3oGWg2oB+YeVk9jPw8iMtavoXibxQswO0ELwUourUAjOwTdMGyGPrHWhqJrLzXqm uYQi1rtdoh7I4TYUx96S92oxnrMeTfYQKhn+MCToH6JTH0EX7VhnQWZ0zPy99qq259kZ NHX/EE3YRErbbPL+ymOk9uQyPHEe/VXSYu8ll3uXJJBS12pNjV1WhMwk9S5lhe6p6BpX cr1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3/CJUXQvBCEoPlihnnAPxMwhS0SfN83B4jFLy6O6YSI=; b=4zCuHdrtSfIZZx4IYkbAKUQsomWl4JikIjO1T2ih9EmxO0WVZ81TPZZ6EwLcKAAVet pleBiGvmQa93qVVombPXR66FDB8KCInVHlRfpHmgG4qb+xb5Ox8zjDxT9L2TWYb/eU7c s/wc8A/EdfRg+aItzdgQfJu5jzHA7iLrOnIbDS15g6v8ILOe6u2StzaXhLnzonDmnrwM PDk7rySyTacc9lSiPDEPPG2RgtAMUg2eH4oRzjbksjJa3H7g8xX2AcxqvNiBXG7quFrD sBx7B1umF3yEBUsMMSDN++W9JDfjirLb5BZHTu3PBnltOIOyk0YTFasYJ6DK86fbSyjO eXSg== X-Gm-Message-State: AOAM532YcOnhjeK8XIF8o6Bh+V9OGiTp+TkaS910Zthcx0w81dTc+ZbE aH6RIx5rCiUbGEEMaInb19h6Hy43fN4ZgQ== X-Google-Smtp-Source: ABdhPJzJxEriHKshKgS2pcIKKDDQk2BJUzNMQGMyP3MgZQnSsymDaqZAwvDm7ilnN+he844iwso5LQ== X-Received: by 2002:a63:2cd8:: with SMTP id s207mr13595431pgs.312.1635614425551; Sat, 30 Oct 2021 10:20:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 53/66] target/sh4: Set fault address in superh_cpu_do_unaligned_access Date: Sat, 30 Oct 2021 10:16:22 -0700 Message-Id: <20211030171635.1689530-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635619453515100003 We ought to have been recording the virtual address for reporting to the guest trap handler. Cc: Yoshinori Sato Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/sh4/op_helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index c996dce7df..752669825f 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -29,6 +29,9 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr a= ddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { + CPUSH4State *env =3D cs->env_ptr; + + env->tea =3D addr; switch (access_type) { case MMU_INST_FETCH: case MMU_DATA_LOAD: @@ -37,6 +40,8 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr a= ddr, case MMU_DATA_STORE: cs->exception_index =3D 0x100; break; + default: + g_assert_not_reached(); } cpu_loop_exit_restore(cs, retaddr); } --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635618735897401.67443882357065; Sat, 30 Oct 2021 11:32:15 -0700 (PDT) Received: from localhost ([::1]:49818 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgt9K-0005pC-Tt for importer@patchew.org; Sat, 30 Oct 2021 14:32:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58788) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1v-0001Yx-LE for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:32 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:38681) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1r-0002DO-Ud for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:31 -0400 Received: by mail-pf1-x434.google.com with SMTP id l1so5883362pfu.5 for ; Sat, 30 Oct 2021 10:20:27 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P+LiSx7CkE3blKbhg5ALaxOT08dtFOhalcqlNc9ibvc=; b=Os4XC7xz6OE376lMGaw9BdNtb0/eK6y4plZLVIEqixEnuGmuzbgFQ8CbmcF/M1BYy1 uHaTqevjdhlADWORORgQwL7rzVf0S9txLdsouVEzE+yOPWCKD04NvrlWNSKWJPQybOEQ zzaDdooye3tbLPZIZqW/aGooaVla6hdpmdOdF6CAJDqP+OTnvdY5ufsdcKZvv8w869sM yGxkpGKeliwLQVVAOkTa+tG3JISQsj3a6nGy9VGUsid9BnaQgZ31kaW3KpgO6PhZ/RYY 00/qOiSo0MC00u8FTEtfl09kwAfWOPeVnNpvSE8m0pzXkfYmFrB6LyWZVuEjNK+JeH2D gRtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P+LiSx7CkE3blKbhg5ALaxOT08dtFOhalcqlNc9ibvc=; b=HAOsRrJjfxZ0ysOMPC8aCNPZKrNwe0cPub1HPBtxfgkj5da8ShDy3879ZXMUiKCMgc ezVCfStSAHVl8qc/ApcSMVRLbCN1yhxIoJvx+XLrCUkGwSYn4x/rZmOcgXu3+8kr+jqZ +9FkREjrnLywRHaz9Fb7S0Y90rIoLVsBPyRoUB517eUtHD7ThnW9B+hYA143XfcNipWz TEn3m/NijFZFGr5q0/Fc9MrDW2jqFMl6JHgQnUcDNyLbPQqXFOuFRKpM43RbKTv3cbyo PVYsCbMOKPrg2ykQ+XEv3HRRCVj/cXGc1KI0Y4hbwI4xjOSGmW+yta++D2E+z4nLNFW9 0N2g== X-Gm-Message-State: AOAM531eyouKbU4GXrgMYeh38rMViUGqn6Un3RGwM17Hf/N6zScIuf9T UinkBcr40Fembhv6Z+i4v6/ZWxGre3uv2w== X-Google-Smtp-Source: ABdhPJwUTkL16rELXy/79sKpiHfodxi4mJ6QvuBSRCyFBSFZbCopGt/t1jPU8m4ZlMf3RQAypyLL6w== X-Received: by 2002:a62:e901:0:b0:47b:f1bc:55e4 with SMTP id j1-20020a62e901000000b0047bf1bc55e4mr18596171pfh.0.1635614426387; Sat, 30 Oct 2021 10:20:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 54/66] target/sparc: Remove DEBUG_UNALIGNED Date: Sat, 30 Oct 2021 10:16:23 -0700 Message-Id: <20211030171635.1689530-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635618736388100003 The printf should have been qemu_log_mask, the parameters themselves no longer compile, and because this is placed before unwinding the PC is actively wrong. We get better (and correct) logging on the other side of raising the exception, in sparc_cpu_do_interrupt. Reviewed-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index bbf3601cb1..0549b6adf1 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -27,7 +27,6 @@ =20 //#define DEBUG_MMU //#define DEBUG_MXCC -//#define DEBUG_UNALIGNED //#define DEBUG_UNASSIGNED //#define DEBUG_ASI //#define DEBUG_CACHE_CONTROL @@ -364,10 +363,6 @@ static void do_check_align(CPUSPARCState *env, target_= ulong addr, uint32_t align, uintptr_t ra) { if (addr & align) { -#ifdef DEBUG_UNALIGNED - printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FM= T_lx - "\n", addr, env->pc); -#endif cpu_raise_exception_ra(env, TT_UNALIGNED, ra); } } @@ -1968,10 +1963,6 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPU= State *cs, vaddr addr, SPARCCPU *cpu =3D SPARC_CPU(cs); CPUSPARCState *env =3D &cpu->env; =20 -#ifdef DEBUG_UNALIGNED - printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx - "\n", addr, env->pc); -#endif cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } #endif --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635619599445385.9076475235495; Sat, 30 Oct 2021 11:46:39 -0700 (PDT) Received: from localhost ([::1]:50374 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgtNF-00009l-CF for importer@patchew.org; Sat, 30 Oct 2021 14:46:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58810) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1w-0001Zg-Ep for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:33 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:37654) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1t-0002Ef-F3 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:32 -0400 Received: by mail-pf1-x435.google.com with SMTP id y20so1550796pfi.4 for ; Sat, 30 Oct 2021 10:20:28 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fVhlPoABQmS8wc89+ovGDAnkicIV2MZx6WAeJyRD9lM=; b=qYSk/QX9tweVQgiN6T21Jk1xMq6dXZ14bP+mcdhoat6acq4AyoVnkDZ2Bmx9Oj754K qPrYnl3gdAiDJ0t0tIScihaHhkyfbkUqq72jVSGae5mjHyc/Pid0QuSt/hMQnCRuDHp7 Qh8GlpKQ9i2SZ5CasI9ZfKWO5m/mHG5lzSarbgskaGo5tt6pW3ZxDyyYfi8ilIA/8K6i /ofsdddjDhUBvxEc5jzHNUVHANzZmg7Cnt8yuUk8mXlgVg8ZSFahHZ1F2WOhh81tKpH4 +soIJzpF6b2oLQz15FK8hlRZrqJbSnHS1Q8OwFJXiUA0tR/ETFdRN2W/q6FB2+6MXjRo prDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fVhlPoABQmS8wc89+ovGDAnkicIV2MZx6WAeJyRD9lM=; b=bSw16Dam4Qe8hOsOv/rB2YHkIFx0kH8YFBvo0fVPv/C1eqJP3BxGZ6yNEA0Jv88u+z Xj8vng7qogUj6Xl+AEksYoADfPnj06i05bczC5hoH8eAWR7Wz0bbKVtO0nRKscEOukH0 qkLvDqcaRGr3VrZqGfLJk3t6VMRel9S09TkB8iQ6L27tlVBNzCHisVPA7cNm8x4aTFmP Yf9GzHa7Te0Y7i9aWc6rklzkMvQXhcUm7b09vRJjnDnYfO3EHM/TMKfAuvr75uLEPJ0i cmH4w3E+gQsP0dDh/MSv6yyRBEaLyClODmSpuw6xsHgpwFJhV+s9AZ936GXXPmFqkElr WKDw== X-Gm-Message-State: AOAM530DAsBuSNoJF9ZzdADflVdloq53TRrClwFbrb4ggigqkdj4FJtW H2h6ISFa4mjMzP4oSh4rvCvo4CHsVbv3lQ== X-Google-Smtp-Source: ABdhPJzGlD+tZvsFcucm+ScsaCHfhmJhzU2KZyM8MAyoZtt07nEk1Wfh98EeV4ukFDiDp7f/l5g9cg== X-Received: by 2002:a65:6215:: with SMTP id d21mr13887598pgv.62.1635614427287; Sat, 30 Oct 2021 10:20:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 55/66] target/sparc: Split out build_sfsr Date: Sat, 30 Oct 2021 10:16:24 -0700 Message-Id: <20211030171635.1689530-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635619601328100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/mmu_helper.c | 72 +++++++++++++++++++++++++-------------- 1 file changed, 46 insertions(+), 26 deletions(-) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 2ad47391d0..014601e701 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -502,16 +502,60 @@ static inline int ultrasparc_tag_match(SparcTLBEntry = *tlb, return 0; } =20 +static uint64_t build_sfsr(CPUSPARCState *env, int mmu_idx, int rw) +{ + uint64_t sfsr =3D SFSR_VALID_BIT; + + switch (mmu_idx) { + case MMU_PHYS_IDX: + sfsr |=3D SFSR_CT_NOTRANS; + break; + case MMU_USER_IDX: + case MMU_KERNEL_IDX: + sfsr |=3D SFSR_CT_PRIMARY; + break; + case MMU_USER_SECONDARY_IDX: + case MMU_KERNEL_SECONDARY_IDX: + sfsr |=3D SFSR_CT_SECONDARY; + break; + case MMU_NUCLEUS_IDX: + sfsr |=3D SFSR_CT_NUCLEUS; + break; + default: + g_assert_not_reached(); + } + + if (rw =3D=3D 1) { + sfsr |=3D SFSR_WRITE_BIT; + } else if (rw =3D=3D 4) { + sfsr |=3D SFSR_NF_BIT; + } + + if (env->pstate & PS_PRIV) { + sfsr |=3D SFSR_PR_BIT; + } + + if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */ + sfsr |=3D SFSR_OW_BIT; /* overflow (not read before another fault)= */ + } + + /* FIXME: ASI field in SFSR must be set */ + + return sfsr; +} + static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, int *prot, MemTxAttrs *attrs, target_ulong address, int rw, int mmu= _idx) { CPUState *cs =3D env_cpu(env); unsigned int i; + uint64_t sfsr; uint64_t context; - uint64_t sfsr =3D 0; bool is_user =3D false; =20 + sfsr =3D build_sfsr(env, mmu_idx, rw); + switch (mmu_idx) { case MMU_PHYS_IDX: g_assert_not_reached(); @@ -520,29 +564,18 @@ static int get_physical_address_data(CPUSPARCState *e= nv, hwaddr *physical, /* fallthru */ case MMU_KERNEL_IDX: context =3D env->dmmu.mmu_primary_context & 0x1fff; - sfsr |=3D SFSR_CT_PRIMARY; break; case MMU_USER_SECONDARY_IDX: is_user =3D true; /* fallthru */ case MMU_KERNEL_SECONDARY_IDX: context =3D env->dmmu.mmu_secondary_context & 0x1fff; - sfsr |=3D SFSR_CT_SECONDARY; break; - case MMU_NUCLEUS_IDX: - sfsr |=3D SFSR_CT_NUCLEUS; - /* FALLTHRU */ default: context =3D 0; break; } =20 - if (rw =3D=3D 1) { - sfsr |=3D SFSR_WRITE_BIT; - } else if (rw =3D=3D 4) { - sfsr |=3D SFSR_NF_BIT; - } - for (i =3D 0; i < 64; i++) { /* ctx match, vaddr match, valid? */ if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical= )) { @@ -592,22 +625,9 @@ static int get_physical_address_data(CPUSPARCState *en= v, hwaddr *physical, return 0; } =20 - if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status registe= r */ - sfsr |=3D SFSR_OW_BIT; /* overflow (not read before - another fault) */ - } - - if (env->pstate & PS_PRIV) { - sfsr |=3D SFSR_PR_BIT; - } - - /* FIXME: ASI field in SFSR must be set */ - env->dmmu.sfsr =3D sfsr | SFSR_VALID_BIT; - + env->dmmu.sfsr =3D sfsr; env->dmmu.sfar =3D address; /* Fault address register */ - env->dmmu.tag_access =3D (address & ~0x1fffULL) | context; - return 1; } } --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635618954594864.9987391002776; Sat, 30 Oct 2021 11:35:54 -0700 (PDT) Received: from localhost ([::1]:56266 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgtCr-0001rt-KL for importer@patchew.org; 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[174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=muffzeHX3yZuoAcxrWs0UhKgv9u/j8rmCNk7xQHU/Hc=; b=OuWHDlUPC4yeA0vCAwp4rucFVp+b5FyGJ0mNq2QCx77hvUMFr/5Y8nftABDMhv+gIy 74oQRgfDoGEq8EX+JphlewuQzTh3RAh1Hqlc/wV1b/6jnBVdFxh7XNTQqvjbddRD2G3p yqqvVnNRj9b/tMiQBEDxfJIheXWpN3SekIOgusKAIX8DOw/XilskWIq/A+dUnhttzz3t Q+k2K4rr7h5I8nvYm4BM/txVTqVrSKnIT93mdY8lfq9FQfBhT3JN6U/Ugx7/lvIhXQ1b +VtUzwRtr9qAsXw4+baANx5NAHHBG0WDuRAG89vpOTIEMmPt2AO6ZUmAGw65yN3PDSpn 6RHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=muffzeHX3yZuoAcxrWs0UhKgv9u/j8rmCNk7xQHU/Hc=; b=gGItJUVNEy5an4F53Cmedw57fIwXYuRZSDhl8Dkx/YCNFtuG4bZ8Q9/N94Ksv3SW30 tyzN6/oUXFwBMFimbCpKotHdLCcdPJTkm5seiBY++7n269FREqqOjw/DHIeP5O4stdXT Zy8kLhTJlZTHnJbkDZhB5nL6oWz+B3BoRDEWJOxR/I4LWfpC52nLFH4RB5UAa0WcE4Nd uPF51mGYYphN2ZLnDl4ci0So4WdJQ/IQyHkRRwkIBsbT7qaBrkQfneGoz061CRSjbqgt YD4OkCH8kIXSropeV391QJECX3BU8VCmuUAWvfoQMYKxIyY1GVDZJrV8jBralOKtzWRn 1U6g== X-Gm-Message-State: AOAM532ozdKYyiR0QwhHU4diuClxbpaJjojMDKIW6EbqeduD6/yIpEyu ApKMYOsmSNv6ffOlW/UzdCkoHsQ09l1Ozg== X-Google-Smtp-Source: ABdhPJwfS6uurXSYmMBitBRZYZELkPgjZ8kHmgAWzXMNfTV0ZDlpT6Mwz2+jloppvDKKjytZr93qOA== X-Received: by 2002:a63:da0a:: with SMTP id c10mr13320198pgh.333.1635614428300; Sat, 30 Oct 2021 10:20:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 56/66] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Date: Sat, 30 Oct 2021 10:16:25 -0700 Message-Id: <20211030171635.1689530-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635618955671100004 Content-Type: text/plain; charset="utf-8" We ought to have been recording the virtual address for reporting to the guest trap handler. Move the function to mmu_helper.c, so that we can re-use code shared with get_physical_address_data. Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 13 ------------- target/sparc/mmu_helper.c | 20 ++++++++++++++++++++ 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 0549b6adf1..a3e1cf9b6e 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1953,16 +1953,3 @@ void sparc_cpu_do_transaction_failed(CPUState *cs, h= waddr physaddr, is_asi, size, retaddr); } #endif - -#if !defined(CONFIG_USER_ONLY) -void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, - uintptr_t retaddr) -{ - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; - - cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); -} -#endif diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 014601e701..f2668389b0 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -922,3 +922,23 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vad= dr addr) } return phys_addr; } + +#ifndef CONFIG_USER_ONLY +void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, + uintptr_t retaddr) +{ + SPARCCPU *cpu =3D SPARC_CPU(cs); + CPUSPARCState *env =3D &cpu->env; + +#ifdef TARGET_SPARC64 + env->dmmu.sfsr =3D build_sfsr(env, mmu_idx, access_type); + env->dmmu.sfar =3D addr; +#else + env->mmuregs[4] =3D addr; +#endif + + cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); +} +#endif /* !CONFIG_USER_ONLY */ --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635618675985752.5719804726084; Sat, 30 Oct 2021 11:31:15 -0700 (PDT) Received: from localhost ([::1]:49080 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgt8M-0005Lb-FM for importer@patchew.org; Sat, 30 Oct 2021 14:31:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1x-0001a6-KH for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:33 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:45804) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1v-0002Fr-At for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:33 -0400 Received: by mail-pg1-x52c.google.com with SMTP id f5so12980217pgc.12 for ; Sat, 30 Oct 2021 10:20:30 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G7SBr/WksrEb3wfGw9+4/7HGKeZrYxUMshTizcIBHp0=; b=ha+vwqS490HsDFEQ0F/1pikVnMkJcrluXAED+0j3rqMv+we36g6BjtrpJwLnoSPAIT FkZCAY68jMp+tTFn0alRgo8/Lgi6V9bycGgXNpuGqGceN8EgnBwTagIHCrPQbSVBvKbO 41fzzzIqKm6BjtjIkop8sGuOUm0KeJNm+yBG1JTvDzGEM/g/eEwZY+zytbT+Vx/zmkFa NcRKT4Qk85APgf/lviVO5DvxDdYb9xaDzQ1hK0gjYlc2NLbd3mknXaT4okU5Bx/iVGN7 0cpQ8nac800QTPaZB4b7rml8FB0jBxdPA4Rv498EYNolXxcXXOErEn05u8IRuiPzmeGx x6Rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G7SBr/WksrEb3wfGw9+4/7HGKeZrYxUMshTizcIBHp0=; b=fURRZ5kNYkBTfX5vwK4cpiyc/HMwaoxUE99SPDNlVBMbg9HploYmIgPxa8CJ7+hiHh xpNnhPGWJ2Fr/pxgFY5oR7uNi/xdToP6JNHx7fWf3pHaFpAbt6NDsJChpRR8eERXfZq5 RT7qqqK5kUs790p9+WB/UVRCHcAP9hDQhZszxZOkcfwKkcY3Rx677N7vbP7dOvBbR2ru cbiDibNdeDdnfbzf/6KXhym8N4w0tj1TJm5m8vmVae/SIvOAjwPWGwUW+QxcnPsb7kbp fpguengEgglS+0wH7zGSYYY0LxOQ4yUb9kQdvVqqwRdDrV53mxliyOzlEpiUuU+eaQ9j Ntpw== X-Gm-Message-State: AOAM533Zi7obj6lRc39KJ4O/3WuItBPwIQtEWGu+NB7F3d+os7M0V3Pb qoASI+dHQZRhA584vtSM2UxlbrkmRB3ejQ== X-Google-Smtp-Source: ABdhPJy+vtVUOXSuebXNw9Z4HJI0c3YLZxOu4EIChRfPYT1nbDFKmevgAwB5yoipVIunJg/t6mGdUA== X-Received: by 2002:a63:b241:: with SMTP id t1mr13676132pgo.154.1635614429261; Sat, 30 Oct 2021 10:20:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 57/66] accel/tcg: Report unaligned atomics for user-only Date: Sat, 30 Oct 2021 10:16:26 -0700 Message-Id: <20211030171635.1689530-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635618677235100001 Use the new cpu_loop_exit_sigbus for atomic_mmu_lookup, which has access to complete alignment info from the TCGMemOpIdx arg. Reviewed-by: Warner Losh Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index c4f69908e9..1ee64f01fc 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -474,11 +474,22 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, MemOpIdx oi, int size, int prot, uintptr_t retaddr) { + MemOp mop =3D get_memop(oi); + int a_bits =3D get_alignment_bits(mop); + void *ret; + + /* Enforce guest required alignment. */ + if (unlikely(addr & ((1 << a_bits) - 1))) { + MMUAccessType t =3D prot =3D=3D PAGE_READ ? MMU_DATA_LOAD : MMU_DA= TA_STORE; + cpu_loop_exit_sigbus(env_cpu(env), addr, t, retaddr); + } + /* Enforce qemu required alignment. */ if (unlikely(addr & (size - 1))) { cpu_loop_exit_atomic(env_cpu(env), retaddr); } - void *ret =3D g2h(env_cpu(env), addr); + + ret =3D g2h(env_cpu(env), addr); set_helper_retaddr(retaddr); return ret; } --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635617472899472.29562942614416; Sat, 30 Oct 2021 11:11:12 -0700 (PDT) Received: from localhost ([::1]:41700 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgsok-0005dV-1Y for importer@patchew.org; Sat, 30 Oct 2021 14:10:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58842) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1x-0001a7-OY for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:34 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:40579) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1v-0002GT-Ex for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:33 -0400 Received: by mail-pj1-x102c.google.com with SMTP id n36-20020a17090a5aa700b0019fa884ab85so13062600pji.5 for ; Sat, 30 Oct 2021 10:20:31 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MIsR5ntgtAsaxoJ+NtIU7qk3vK65x7GB6eb5bSAQ4NA=; b=j9FKfR1ccCUM+gIHVspWVzeJo0UmJ+5v4WsXAeIZcBukprR7Bqb5l0u6B+i1XIFpl/ D0tdeXiA0DCPffT15di72bdT/Pa3+Jf0085u2WPlCISn7Mt8ptXGSsPTaWRYoQ381305 7Be81toSeudq97EicGdIzEP90pjHaxGub68YbampX8XWG+liNTdxWboDHlv5pVtOYehO E0W9gHX0m9NXh6MLQa62Uqhr6JdQjipPMHJW79U8xKAAPk9sCm9CYoOqN9UHMNwISpCJ 2L9+dwdGtMsuS6tjmKl5XKRZ895hqsU9vTrr2Q2fY4ZFjLDzl7hrv0vtlrBDmGACv0H7 Vntg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MIsR5ntgtAsaxoJ+NtIU7qk3vK65x7GB6eb5bSAQ4NA=; b=Hss22LfFdgZ6rpAgCGnhtOoW5TjRKF0DyzngqN4e8fPlu7uf6cHJr88TW8Oyf8qso/ ak+oAZ1wCnlJVnfjM30pMLx27tZjsakdcwLWi4E4wYkUWFzjZmZPucProd3j2zPxaeeZ vJMo1V+fdsEZ9gDsA9CCwme3a1ZOmfcexaJEoiqsXRRNeyl1GCcT4ETz038lX8sn6qWE dYDIfl01mjtKcZETgts5LeAUK5Sy2jfAUzTWhQnam2tv2DFy1blIbvhMEHcKq6yQwCMn 9zADdvcEM/wno9DCAWH7Z3ZLHvVEEu8xkAm5Cko1XP6vYVbLEkcHlNjNB4wL4SwdNw+i wMJA== X-Gm-Message-State: AOAM533pYvxE9PQ0oLuL6hOedIMPapa62pSMxRonWB913jtfNYWEH34+ JVx0U+j2Ha+mzXSNIBB3IT+QwWBBz4pq8Q== X-Google-Smtp-Source: ABdhPJzwfg2KD3uFXuS1cRma10SVHfSF817hWTRAxXY3gsG2z6K0j2GhMKt1VIoxNYGhNK35WFp3/w== X-Received: by 2002:a17:902:e808:b0:140:55fe:1b4e with SMTP id u8-20020a170902e80800b0014055fe1b4emr15631702plg.87.1635614430147; Sat, 30 Oct 2021 10:20:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 58/66] accel/tcg: Report unaligned load/store for user-only Date: Sat, 30 Oct 2021 10:16:27 -0700 Message-Id: <20211030171635.1689530-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635617474595100001 Use the new cpu_loop_exit_sigbus for cpu_mmu_lookup. Reviewed-by: Warner Losh Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 1ee64f01fc..aaf47d89d2 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -218,9 +218,14 @@ static void validate_memop(MemOpIdx oi, MemOp expected) static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t ra, MMUAccessType type) { + MemOp mop =3D get_memop(oi); + int a_bits =3D get_alignment_bits(mop); void *ret; =20 - /* TODO: Enforce guest required alignment. */ + /* Enforce guest required alignment. */ + if (unlikely(addr & ((1 << a_bits) - 1))) { + cpu_loop_exit_sigbus(env_cpu(env), addr, type, ra); + } =20 ret =3D g2h(env_cpu(env), addr); set_helper_retaddr(ra); --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635619776006113.26176155189694; Sat, 30 Oct 2021 11:49:36 -0700 (PDT) Received: from localhost ([::1]:54798 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgtQ6-0003Jh-My for importer@patchew.org; Sat, 30 Oct 2021 14:49:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58846) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1y-0001aY-0X for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:34 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:42843) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1w-0002Gs-4O for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:33 -0400 Received: by mail-pf1-x429.google.com with SMTP id m14so12292816pfc.9 for ; Sat, 30 Oct 2021 10:20:31 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7mVMLvhvHhRE4SNYEq8lTvIaJ67DT2EyP7H4YHihO6k=; b=e9tFOewGX8cs8ldY+qy3eJoZ1SCcY+REGjWps39XAIFleMUQv/RUMdD8tAx3OtwJHJ 7cqBHvKlSVinGdtI5A0zWKq2YSj+FYHimq746T7GF9xi2zsBOm8+w7l9HT1Ii+GLoZLd SJVbG4w07av2hXlsQElwuDSnh83GDsGzA1mij3f86a3J2nhLqwlApj6MaWr2OVajBNHG dDzNLBLoW7FH/SQZz1At/ShE3cnnkPzU73nm3DY6g6k2ugaAkpFyk+TgQTP0xvVYFS4V EUIzHwOXVILTPumaZbVoqnJl4mfxvya9FkdWIRfexq34x0teWX7yyH7MsJDinVSn3fLI 4DUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7mVMLvhvHhRE4SNYEq8lTvIaJ67DT2EyP7H4YHihO6k=; b=aB6HYmudgpamAIn5ASdxnd65UDo9fTWQecatICmXdSMYTr7TwOpNazkpoz0eCTZkeI 1rrzG7REnoUjgG1FHZPG+VcvLzfuq7r2BOhbVhM9dcS7hsd0PX6pzUI1MyWor7gFGtDl vMXjdywOavLdxFvnU5aFrTpgrXrKyftfo8oByj3crVZfuA9Brk1r0+zduwtw76WHah2w hc/jnMpZCdd0eNoCKo6jggvc/pLOO4G16eQq1VMaYdjXbcz6008gY5jQhXwZf4o91Ni3 qf/ZtB8k+6x3hZXbs7Wyq1UVVSu+WvlKR0RgUd8Veec66QzJiAdVsD7vjwGjtjMmquwJ O1zw== X-Gm-Message-State: AOAM530ciweM6NU+N0/vurZzQoK/umzSDmDpH7SYQ6zN7krxlrOQxPOz KLt/Z/5zCdY+lRWOKDhvPtw+afKc5lXGPw== X-Google-Smtp-Source: ABdhPJycbYIj2QjN//k7kU+MPo6jKFNIB7BRU5VDT2eZlY+ELKIgeTQgiHtOFVArTsyaWW3Fksh1Nw== X-Received: by 2002:a63:3716:: with SMTP id e22mr13756546pga.75.1635614430899; Sat, 30 Oct 2021 10:20:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 59/66] tcg: Add helper_unaligned_{ld, st} for user-only sigbus Date: Sat, 30 Oct 2021 10:16:28 -0700 Message-Id: <20211030171635.1689530-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635619778218100001 To be called from tcg generated code on hosts that support unaligned accesses natively, in response to an access that is supposed to be aligned. Reviewed-by: Warner Losh Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 5 +++++ accel/tcg/user-exec.c | 11 +++++++++++ 2 files changed, 16 insertions(+) diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h index 8c86365611..bf40942de4 100644 --- a/include/tcg/tcg-ldst.h +++ b/include/tcg/tcg-ldst.h @@ -70,5 +70,10 @@ void helper_be_stl_mmu(CPUArchState *env, target_ulong a= ddr, uint32_t val, void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr); =20 +#else + +void QEMU_NORETURN helper_unaligned_ld(CPUArchState *env, target_ulong add= r); +void QEMU_NORETURN helper_unaligned_st(CPUArchState *env, target_ulong add= r); + #endif /* CONFIG_SOFTMMU */ #endif /* TCG_LDST_H */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index aaf47d89d2..1528a21fad 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -27,6 +27,7 @@ #include "exec/helper-proto.h" #include "qemu/atomic128.h" #include "trace/trace-root.h" +#include "tcg/tcg-ldst.h" #include "internal.h" =20 __thread uintptr_t helper_retaddr; @@ -215,6 +216,16 @@ static void validate_memop(MemOpIdx oi, MemOp expected) #endif } =20 +void helper_unaligned_ld(CPUArchState *env, target_ulong addr) +{ + cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_LOAD, GETPC()); +} + +void helper_unaligned_st(CPUArchState *env, target_ulong addr) +{ + cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_STORE, GETPC()); +} + static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t ra, MMUAccessType type) { --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635618945169570.2559794054232; Sat, 30 Oct 2021 11:35:45 -0700 (PDT) Received: from localhost ([::1]:55498 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgtCh-0001ND-Vg for importer@patchew.org; Sat, 30 Oct 2021 14:35:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58852) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs1y-0001cf-M5 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:35 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:39635) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1w-0002HQ-NK for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:34 -0400 Received: by mail-pf1-x42a.google.com with SMTP id b1so8794644pfm.6 for ; Sat, 30 Oct 2021 10:20:32 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7lLZzifCuDAFtBOJRXRut8iWPXEYL/L2LC9pwY/6QWY=; b=Itrf786Df6Agb72fWZWnk/m+KefxTuJPOUBT8RW1lRCyl20UWkKICiWMh44fXOTrhk NO2usgJdvrqhKCB4cVzwSiYZQgdJcoqZK6lWTf/Kq85m9YJF5jv7BRUz4SxUTpBLwSzu BwS+Mk4Mk4ziBrzQ/K4VMtL9mBMzJb5V41RpVDSuyJ0IrstGzsPJKkBnH2bbZLIlQH3J hU3QtMVTVuEurQclXOf2PgWiaR2VDpu1rXqxDyMIwpLNp+QOITXGijBQZ04uinaZTaLY QXZONcIcn5Dd9MKCsptK3ckMhs9aF5oY4pWwd224rIi97oAcRg6fscLknphN7rQ6BTYN t41A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7lLZzifCuDAFtBOJRXRut8iWPXEYL/L2LC9pwY/6QWY=; b=Pq0c0rkYoAMKRHffKJoRHKC1gTRCCPFJmHZi+nWnoeAaqGu5OBqkqYsxSdr6Y1q6ri 2g6ldKIMNc0DIDapYVpARwUMO+GN5ztQfJK4h1I08RxHoGrKKp1AxixYa+tBTQu6sp0m br0Efl8fDEvwpFmQSXf74kKz9RkYI6PmXPZQplbN4PQxG6DTKsmFDuSW2IOnBwyTQPgm 2b9cuCJnwP0t81+0OqJTfnrRJ6Z7LrmYftLeFxc8lt4c/pGN9eEcfd4hxUmJ7AQS/ChY d5IIaZcEkyPhfuvEBvLu/lcrhPNRH3L3XQrfIBTpABqLQdSpNDwjQPz1aND5t45To7zN jUDA== X-Gm-Message-State: AOAM532qsBAuCHQwbCn/ThO1rgiNj1tuMiRb0zCSWVclBvG/3R0OMqzV BJPxfZkexK5fkMZ8D1doQdAIjqGDcqQYeQ== X-Google-Smtp-Source: ABdhPJwGiRpaAhQejq2ZTtemk+eZAe4tVLC9VzPnGp5X8kJzWMSFvPPnwld9ij1WHq9rjVzTkM1TkA== X-Received: by 2002:a63:7706:: with SMTP id s6mr13798640pgc.184.1635614431488; Sat, 30 Oct 2021 10:20:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 60/66] linux-user: Handle BUS_ADRALN in host_signal_handler Date: Sat, 30 Oct 2021 10:16:29 -0700 Message-Id: <20211030171635.1689530-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635618947293100001 Handle BUS_ADRALN via cpu_loop_exit_sigbus, but allow other SIGBUS si_codes to continue into the host-to-guest signal conversion code. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- linux-user/signal.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-user/signal.c b/linux-user/signal.c index df2c8678d0..81c45bfce9 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -860,6 +860,9 @@ static void host_signal_handler(int host_sig, siginfo_t= *info, void *puc) cpu_loop_exit_sigsegv(cpu, guest_addr, access_type, maperr, pc= ); } else { sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + if (info->si_code =3D=3D BUS_ADRALN) { + cpu_loop_exit_sigbus(cpu, guest_addr, access_type, pc); + } } =20 sync_sig =3D true; --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635619135790322.3468398873922; Sat, 30 Oct 2021 11:38:55 -0700 (PDT) Received: from localhost ([::1]:33886 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgtFm-0005pr-CI for importer@patchew.org; Sat, 30 Oct 2021 14:38:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58918) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs23-0001jS-4J for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:39 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:37395) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1y-0002J3-5m for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:38 -0400 Received: by mail-pl1-x62c.google.com with SMTP id j1so2421330plx.4 for ; Sat, 30 Oct 2021 10:20:33 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mnqEEgywou2/cA2oB9Is2HfT4xL6ufMEEmIOEI3fkHA=; b=x06D+drAZFVdTxKRIzLQ8H4yITA6VO6xbux8PJ4TF0Q9TuiWLaDDQwm8mNKvhhe/5O AlyqO+NYF0jlN+LL+fJ4frzVh8nL5rmRs5C+bb6WHYFnEvjbpVJQQhpB9xZHzJz06eM0 Sxk4JSf3twNock3q68g5+uek7sCaULXiTsyIm46NplSfl8xKp+iyGCBc8eXjhpB+HqpG hwHpIY7x+LZvlRJWPWgtYVu1+daHoKzTZuMXzztxLRrNHwrELFhAcd9gIDc2TsPgj3EC 94Q2HcI0BIqMf8PCsFYSWdYcT3sLmsXGaf+FYU5Uz0ugwe1SvyJKg7x7U8MJSuODugTM 7g+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mnqEEgywou2/cA2oB9Is2HfT4xL6ufMEEmIOEI3fkHA=; b=mtRJbopgkfTZnJh0SV73XhAIdXac7kMTjPyEe/jrnoGQYIlSTiuMtCaB1B/NNyJndF f1cKG9sSAKFbfSePmlSotSqpYiTFFjlDTFN599NcGhTZDixJPfEbkqqRiuuLoz8tULpz sseOFff99uOTH54mJ4BV3PQOfQX/Y201gzVYrzfAJzJasVXm//aAuczonJxB4TL+WKSO yHtkCuj/dCgSWvgX/19RrYJiBvt+jK294ZjlYV+gvw5zwD3af/spRamrY8IQL0J8r8V6 LBMjq4t2C6Mbux34IkbUNDR71HEb6rLOyCnilHJvdRwSNs0SYtB6mWDbjf6qnKWAjtMz pSkw== X-Gm-Message-State: AOAM532tQgU3LkiaVEkg/UFXI38qr6yn+gxU79BaoiTq/s4HarVivf4c lroAgyM8GSCGu6YgEdOosVih9O+ndU/uEg== X-Google-Smtp-Source: ABdhPJxJBjSry+JdofB3G0BdKT9ywcg+Le3ViV9tBp3rpGnCnC4lXjZfeTC0wdqVmbsU/RfXvj8XFQ== X-Received: by 2002:a17:90a:c58f:: with SMTP id l15mr5179577pjt.168.1635614432661; Sat, 30 Oct 2021 10:20:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 61/66] linux-user: Split out do_prctl and subroutines Date: Sat, 30 Oct 2021 10:16:30 -0700 Message-Id: <20211030171635.1689530-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635619136501100001 Content-Type: text/plain; charset="utf-8" Since the prctl constants are supposed to be generic, supply any that are not provided by the host. Split out subroutines for PR_GET_FP_MODE, PR_SET_FP_MODE, PR_GET_VL, PR_SET_VL, PR_RESET_KEYS, PR_SET_TAGGED_ADDR_CTRL, PR_GET_TAGGED_ADDR_CTRL. Return EINVAL for guests that do not support these options rather than pass them on to the host. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 160 ++++++++++ linux-user/aarch64/target_syscall.h | 23 -- linux-user/alpha/target_prctl.h | 1 + linux-user/arm/target_prctl.h | 1 + linux-user/cris/target_prctl.h | 1 + linux-user/hexagon/target_prctl.h | 1 + linux-user/hppa/target_prctl.h | 1 + linux-user/i386/target_prctl.h | 1 + linux-user/m68k/target_prctl.h | 1 + linux-user/microblaze/target_prctl.h | 1 + linux-user/mips/target_prctl.h | 88 ++++++ linux-user/mips/target_syscall.h | 6 - linux-user/mips64/target_prctl.h | 1 + linux-user/mips64/target_syscall.h | 6 - linux-user/nios2/target_prctl.h | 1 + linux-user/openrisc/target_prctl.h | 1 + linux-user/ppc/target_prctl.h | 1 + linux-user/riscv/target_prctl.h | 1 + linux-user/s390x/target_prctl.h | 1 + linux-user/sh4/target_prctl.h | 1 + linux-user/sparc/target_prctl.h | 1 + linux-user/x86_64/target_prctl.h | 1 + linux-user/xtensa/target_prctl.h | 1 + linux-user/syscall.c | 433 +++++++++------------------ 24 files changed, 414 insertions(+), 320 deletions(-) create mode 100644 linux-user/aarch64/target_prctl.h create mode 100644 linux-user/alpha/target_prctl.h create mode 100644 linux-user/arm/target_prctl.h create mode 100644 linux-user/cris/target_prctl.h create mode 100644 linux-user/hexagon/target_prctl.h create mode 100644 linux-user/hppa/target_prctl.h create mode 100644 linux-user/i386/target_prctl.h create mode 100644 linux-user/m68k/target_prctl.h create mode 100644 linux-user/microblaze/target_prctl.h create mode 100644 linux-user/mips/target_prctl.h create mode 100644 linux-user/mips64/target_prctl.h create mode 100644 linux-user/nios2/target_prctl.h create mode 100644 linux-user/openrisc/target_prctl.h create mode 100644 linux-user/ppc/target_prctl.h create mode 100644 linux-user/riscv/target_prctl.h create mode 100644 linux-user/s390x/target_prctl.h create mode 100644 linux-user/sh4/target_prctl.h create mode 100644 linux-user/sparc/target_prctl.h create mode 100644 linux-user/x86_64/target_prctl.h create mode 100644 linux-user/xtensa/target_prctl.h diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_= prctl.h new file mode 100644 index 0000000000..3f5a5d3933 --- /dev/null +++ b/linux-user/aarch64/target_prctl.h @@ -0,0 +1,160 @@ +/* + * AArch64 specific prctl functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef AARCH64_TARGET_PRCTL_H +#define AARCH64_TARGET_PRCTL_H + +static abi_long do_prctl_get_vl(CPUArchState *env) +{ + ARMCPU *cpu =3D env_archcpu(env); + if (cpu_isar_feature(aa64_sve, cpu)) { + return ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_get_vl do_prctl_get_vl + +static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2) +{ + /* + * We cannot support either PR_SVE_SET_VL_ONEXEC or PR_SVE_VL_INHERIT. + * Note the kernel definition of sve_vl_valid allows for VQ=3D512, + * i.e. VL=3D8192, even though the current architectural maximum is VQ= =3D16. + */ + if (cpu_isar_feature(aa64_sve, env_archcpu(env)) + && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { + ARMCPU *cpu =3D env_archcpu(env); + uint32_t vq, old_vq; + + old_vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; + vq =3D MAX(arg2 / 16, 1); + vq =3D MIN(vq, cpu->sve_max_vq); + + if (vq < old_vq) { + aarch64_sve_narrow_vq(env, vq); + } + env->vfp.zcr_el[1] =3D vq - 1; + arm_rebuild_hflags(env); + return vq * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_set_vl do_prctl_set_vl + +static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) +{ + ARMCPU *cpu =3D env_archcpu(env); + + if (cpu_isar_feature(aa64_pauth, cpu)) { + int all =3D (PR_PAC_APIAKEY | PR_PAC_APIBKEY | + PR_PAC_APDAKEY | PR_PAC_APDBKEY | PR_PAC_APGAKEY); + int ret =3D 0; + Error *err =3D NULL; + + if (arg2 =3D=3D 0) { + arg2 =3D all; + } else if (arg2 & ~all) { + return -TARGET_EINVAL; + } + if (arg2 & PR_PAC_APIAKEY) { + ret |=3D qemu_guest_getrandom(&env->keys.apia, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APIBKEY) { + ret |=3D qemu_guest_getrandom(&env->keys.apib, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APDAKEY) { + ret |=3D qemu_guest_getrandom(&env->keys.apda, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APDBKEY) { + ret |=3D qemu_guest_getrandom(&env->keys.apdb, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APGAKEY) { + ret |=3D qemu_guest_getrandom(&env->keys.apga, + sizeof(ARMPACKey), &err); + } + if (ret !=3D 0) { + /* + * Some unknown failure in the crypto. The best + * we can do is log it and fail the syscall. + * The real syscall cannot fail this way. + */ + qemu_log_mask(LOG_UNIMP, "PR_PAC_RESET_KEYS: Crypto failure: %= s", + error_get_pretty(err)); + error_free(err); + return -TARGET_EIO; + } + return 0; + } + return -TARGET_EINVAL; +} +#define do_prctl_reset_keys do_prctl_reset_keys + +static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long = arg2) +{ + abi_ulong valid_mask =3D PR_TAGGED_ADDR_ENABLE; + ARMCPU *cpu =3D env_archcpu(env); + + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |=3D PR_MTE_TCF_MASK; + valid_mask |=3D PR_MTE_TAG_MASK; + } + + if (arg2 & ~valid_mask) { + return -TARGET_EINVAL; + } + env->tagged_addr_enable =3D arg2 & PR_TAGGED_ADDR_ENABLE; + + if (cpu_isar_feature(aa64_mte, cpu)) { + switch (arg2 & PR_MTE_TCF_MASK) { + case PR_MTE_TCF_NONE: + case PR_MTE_TCF_SYNC: + case PR_MTE_TCF_ASYNC: + break; + default: + return -EINVAL; + } + + /* + * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. + * Note that the syscall values are consistent with hw. + */ + env->cp15.sctlr_el[1] =3D + deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHI= FT); + + /* + * Write PR_MTE_TAG to GCR_EL1[Exclude]. + * Note that the syscall uses an include mask, + * and hardware uses an exclude mask -- invert. + */ + env->cp15.gcr_el1 =3D + deposit64(env->cp15.gcr_el1, 0, 16, ~arg2 >> PR_MTE_TAG_SHIFT); + arm_rebuild_hflags(env); + } + return 0; +} +#define do_prctl_set_tagged_addr_ctrl do_prctl_set_tagged_addr_ctrl + +static abi_long do_prctl_get_tagged_addr_ctrl(CPUArchState *env) +{ + ARMCPU *cpu =3D env_archcpu(env); + abi_long ret =3D 0; + + if (env->tagged_addr_enable) { + ret |=3D PR_TAGGED_ADDR_ENABLE; + } + if (cpu_isar_feature(aa64_mte, cpu)) { + /* See do_prctl_set_tagged_addr_ctrl. */ + ret |=3D extract64(env->cp15.sctlr_el[1], 38, 2) << PR_MTE_TCF_SHI= FT; + ret =3D deposit64(ret, PR_MTE_TAG_SHIFT, 16, ~env->cp15.gcr_el1); + } + return ret; +} +#define do_prctl_get_tagged_addr_ctrl do_prctl_get_tagged_addr_ctrl + +#endif /* AARCH64_TARGET_PRCTL_H */ diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/targe= t_syscall.h index 76f6c3391d..819f112ab0 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -20,27 +20,4 @@ struct target_pt_regs { #define TARGET_MCL_FUTURE 2 #define TARGET_MCL_ONFAULT 4 =20 -#define TARGET_PR_SVE_SET_VL 50 -#define TARGET_PR_SVE_GET_VL 51 - -#define TARGET_PR_PAC_RESET_KEYS 54 -# define TARGET_PR_PAC_APIAKEY (1 << 0) -# define TARGET_PR_PAC_APIBKEY (1 << 1) -# define TARGET_PR_PAC_APDAKEY (1 << 2) -# define TARGET_PR_PAC_APDBKEY (1 << 3) -# define TARGET_PR_PAC_APGAKEY (1 << 4) - -#define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 -#define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 -# define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) -/* MTE tag check fault modes */ -# define TARGET_PR_MTE_TCF_SHIFT 1 -# define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT) -# define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT) -# define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT) -# define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT) -/* MTE tag inclusion mask */ -# define TARGET_PR_MTE_TAG_SHIFT 3 -# define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIF= T) - #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/linux-user/alpha/target_prctl.h b/linux-user/alpha/target_prct= l.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/alpha/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/arm/target_prctl.h b/linux-user/arm/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/arm/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/cris/target_prctl.h b/linux-user/cris/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/cris/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/hexagon/target_prctl.h b/linux-user/hexagon/target_= prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/hexagon/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/hppa/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/i386/target_prctl.h b/linux-user/i386/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/i386/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/m68k/target_prctl.h b/linux-user/m68k/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/m68k/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/microblaze/target_prctl.h b/linux-user/microblaze/t= arget_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/microblaze/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/mips/target_prctl.h b/linux-user/mips/target_prctl.h new file mode 100644 index 0000000000..e028333db9 --- /dev/null +++ b/linux-user/mips/target_prctl.h @@ -0,0 +1,88 @@ +/* + * MIPS specific prctl functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef MIPS_TARGET_PRCTL_H +#define MIPS_TARGET_PRCTL_H + +static abi_long do_prctl_get_fp_mode(CPUArchState *env) +{ + abi_long ret =3D 0; + + if (env->CP0_Status & (1 << CP0St_FR)) { + ret |=3D PR_FP_MODE_FR; + } + if (env->CP0_Config5 & (1 << CP0C5_FRE)) { + ret |=3D PR_FP_MODE_FRE; + } + return ret; +} +#define do_prctl_get_fp_mode do_prctl_get_fp_mode + +static abi_long do_prctl_set_fp_mode(CPUArchState *env, abi_long arg2) +{ + bool old_fr =3D env->CP0_Status & (1 << CP0St_FR); + bool old_fre =3D env->CP0_Config5 & (1 << CP0C5_FRE); + bool new_fr =3D arg2 & PR_FP_MODE_FR; + bool new_fre =3D arg2 & PR_FP_MODE_FRE; + const unsigned int known_bits =3D PR_FP_MODE_FR | PR_FP_MODE_FRE; + + /* If nothing to change, return right away, successfully. */ + if (old_fr =3D=3D new_fr && old_fre =3D=3D new_fre) { + return 0; + } + /* Check the value is valid */ + if (arg2 & ~known_bits) { + return -TARGET_EOPNOTSUPP; + } + /* Setting FRE without FR is not supported. */ + if (new_fre && !new_fr) { + return -TARGET_EOPNOTSUPP; + } + if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) { + /* FR1 is not supported */ + return -TARGET_EOPNOTSUPP; + } + if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64)) + && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { + /* cannot set FR=3D0 */ + return -TARGET_EOPNOTSUPP; + } + if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) { + /* Cannot set FRE=3D1 */ + return -TARGET_EOPNOTSUPP; + } + + int i; + fpr_t *fpr =3D env->active_fpu.fpr; + for (i =3D 0; i < 32 ; i +=3D 2) { + if (!old_fr && new_fr) { + fpr[i].w[!FP_ENDIAN_IDX] =3D fpr[i + 1].w[FP_ENDIAN_IDX]; + } else if (old_fr && !new_fr) { + fpr[i + 1].w[FP_ENDIAN_IDX] =3D fpr[i].w[!FP_ENDIAN_IDX]; + } + } + + if (new_fr) { + env->CP0_Status |=3D (1 << CP0St_FR); + env->hflags |=3D MIPS_HFLAG_F64; + } else { + env->CP0_Status &=3D ~(1 << CP0St_FR); + env->hflags &=3D ~MIPS_HFLAG_F64; + } + if (new_fre) { + env->CP0_Config5 |=3D (1 << CP0C5_FRE); + if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { + env->hflags |=3D MIPS_HFLAG_FRE; + } + } else { + env->CP0_Config5 &=3D ~(1 << CP0C5_FRE); + env->hflags &=3D ~MIPS_HFLAG_FRE; + } + + return 0; +} +#define do_prctl_set_fp_mode do_prctl_set_fp_mode + +#endif /* MIPS_TARGET_PRCTL_H */ diff --git a/linux-user/mips/target_syscall.h b/linux-user/mips/target_sysc= all.h index f59057493a..1ce0a5bbf4 100644 --- a/linux-user/mips/target_syscall.h +++ b/linux-user/mips/target_syscall.h @@ -36,10 +36,4 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env) return 0x40000; } =20 -/* MIPS-specific prctl() options */ -#define TARGET_PR_SET_FP_MODE 45 -#define TARGET_PR_GET_FP_MODE 46 -#define TARGET_PR_FP_MODE_FR (1 << 0) -#define TARGET_PR_FP_MODE_FRE (1 << 1) - #endif /* MIPS_TARGET_SYSCALL_H */ diff --git a/linux-user/mips64/target_prctl.h b/linux-user/mips64/target_pr= ctl.h new file mode 100644 index 0000000000..18da9ae619 --- /dev/null +++ b/linux-user/mips64/target_prctl.h @@ -0,0 +1 @@ +#include "../mips/target_prctl.h" diff --git a/linux-user/mips64/target_syscall.h b/linux-user/mips64/target_= syscall.h index cd1e1b4969..74f12365bc 100644 --- a/linux-user/mips64/target_syscall.h +++ b/linux-user/mips64/target_syscall.h @@ -33,10 +33,4 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env) return 0x40000; } =20 -/* MIPS-specific prctl() options */ -#define TARGET_PR_SET_FP_MODE 45 -#define TARGET_PR_GET_FP_MODE 46 -#define TARGET_PR_FP_MODE_FR (1 << 0) -#define TARGET_PR_FP_MODE_FRE (1 << 1) - #endif /* MIPS64_TARGET_SYSCALL_H */ diff --git a/linux-user/nios2/target_prctl.h b/linux-user/nios2/target_prct= l.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/nios2/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/openrisc/target_prctl.h b/linux-user/openrisc/targe= t_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/openrisc/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/ppc/target_prctl.h b/linux-user/ppc/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/ppc/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/riscv/target_prctl.h b/linux-user/riscv/target_prct= l.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/riscv/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/s390x/target_prctl.h b/linux-user/s390x/target_prct= l.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/s390x/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/sh4/target_prctl.h b/linux-user/sh4/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/sh4/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/sparc/target_prctl.h b/linux-user/sparc/target_prct= l.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/sparc/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/x86_64/target_prctl.h b/linux-user/x86_64/target_pr= ctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/x86_64/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/xtensa/target_prctl.h b/linux-user/xtensa/target_pr= ctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/xtensa/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 544f5b662f..a417396981 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6291,9 +6291,155 @@ abi_long do_arch_prctl(CPUX86State *env, int code, = abi_ulong addr) return ret; } #endif /* defined(TARGET_ABI32 */ - #endif /* defined(TARGET_I386) */ =20 +/* + * These constants are generic. Supply any that are missing from the host. + */ +#ifndef PR_SET_NAME +# define PR_SET_NAME 15 +# define PR_GET_NAME 16 +#endif +#ifndef PR_SET_FP_MODE +# define PR_SET_FP_MODE 45 +# define PR_GET_FP_MODE 46 +# define PR_FP_MODE_FR (1 << 0) +# define PR_FP_MODE_FRE (1 << 1) +#endif +#ifndef PR_SVE_SET_VL +# define PR_SVE_SET_VL 50 +# define PR_SVE_GET_VL 51 +# define PR_SVE_VL_LEN_MASK 0xffff +# define PR_SVE_VL_INHERIT (1 << 17) +#endif +#ifndef PR_PAC_RESET_KEYS +# define PR_PAC_RESET_KEYS 54 +# define PR_PAC_APIAKEY (1 << 0) +# define PR_PAC_APIBKEY (1 << 1) +# define PR_PAC_APDAKEY (1 << 2) +# define PR_PAC_APDBKEY (1 << 3) +# define PR_PAC_APGAKEY (1 << 4) +#endif +#ifndef PR_SET_TAGGED_ADDR_CTRL +# define PR_SET_TAGGED_ADDR_CTRL 55 +# define PR_GET_TAGGED_ADDR_CTRL 56 +# define PR_TAGGED_ADDR_ENABLE (1UL << 0) +#endif +#ifndef PR_MTE_TCF_SHIFT +# define PR_MTE_TCF_SHIFT 1 +# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TAG_SHIFT 3 +# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) +#endif + +#include "target_prctl.h" + +static abi_long do_prctl_inval0(CPUArchState *env) +{ + return -TARGET_EINVAL; +} + +static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2) +{ + return -TARGET_EINVAL; +} + +#ifndef do_prctl_get_fp_mode +#define do_prctl_get_fp_mode do_prctl_inval0 +#endif +#ifndef do_prctl_set_fp_mode +#define do_prctl_set_fp_mode do_prctl_inval1 +#endif +#ifndef do_prctl_get_vl +#define do_prctl_get_vl do_prctl_inval0 +#endif +#ifndef do_prctl_set_vl +#define do_prctl_set_vl do_prctl_inval1 +#endif +#ifndef do_prctl_reset_keys +#define do_prctl_reset_keys do_prctl_inval1 +#endif +#ifndef do_prctl_set_tagged_addr_ctrl +#define do_prctl_set_tagged_addr_ctrl do_prctl_inval1 +#endif +#ifndef do_prctl_get_tagged_addr_ctrl +#define do_prctl_get_tagged_addr_ctrl do_prctl_inval0 +#endif + +static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, + abi_long arg3, abi_long arg4, abi_long arg5) +{ + abi_long ret; + + switch (option) { + case PR_GET_PDEATHSIG: + { + int deathsig; + ret =3D get_errno(prctl(PR_GET_PDEATHSIG, &deathsig, + arg3, arg4, arg5)); + if (!is_error(ret) && arg2 && put_user_s32(deathsig, arg2)) { + return -TARGET_EFAULT; + } + return ret; + } + case PR_GET_NAME: + { + void *name =3D lock_user(VERIFY_WRITE, arg2, 16, 1); + if (!name) { + return -TARGET_EFAULT; + } + ret =3D get_errno(prctl(PR_GET_NAME, (uintptr_t)name, + arg3, arg4, arg5)); + unlock_user(name, arg2, 16); + return ret; + } + case PR_SET_NAME: + { + void *name =3D lock_user(VERIFY_READ, arg2, 16, 1); + if (!name) { + return -TARGET_EFAULT; + } + ret =3D get_errno(prctl(PR_SET_NAME, (uintptr_t)name, + arg3, arg4, arg5)); + unlock_user(name, arg2, 0); + return ret; + } + case PR_GET_FP_MODE: + return do_prctl_get_fp_mode(env); + case PR_SET_FP_MODE: + return do_prctl_set_fp_mode(env, arg2); + case PR_SVE_GET_VL: + return do_prctl_get_vl(env); + case PR_SVE_SET_VL: + return do_prctl_set_vl(env, arg2); + case PR_PAC_RESET_KEYS: + if (arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_reset_keys(env, arg2); + case PR_SET_TAGGED_ADDR_CTRL: + if (arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_set_tagged_addr_ctrl(env, arg2); + case PR_GET_TAGGED_ADDR_CTRL: + if (arg2 || arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_get_tagged_addr_ctrl(env); + case PR_GET_SECCOMP: + case PR_SET_SECCOMP: + /* Disable seccomp to prevent the target disabling syscalls we nee= d. */ + return -TARGET_EINVAL; + default: + /* Most prctl options have no pointer arguments */ + return get_errno(prctl(option, arg2, arg3, arg4, arg5)); + } +} + #define NEW_STACK_SIZE 0x40000 =20 =20 @@ -10630,290 +10776,7 @@ static abi_long do_syscall1(void *cpu_env, int nu= m, abi_long arg1, return ret; #endif case TARGET_NR_prctl: - switch (arg1) { - case PR_GET_PDEATHSIG: - { - int deathsig; - ret =3D get_errno(prctl(arg1, &deathsig, arg3, arg4, arg5)); - if (!is_error(ret) && arg2 - && put_user_s32(deathsig, arg2)) { - return -TARGET_EFAULT; - } - return ret; - } -#ifdef PR_GET_NAME - case PR_GET_NAME: - { - void *name =3D lock_user(VERIFY_WRITE, arg2, 16, 1); - if (!name) { - return -TARGET_EFAULT; - } - ret =3D get_errno(prctl(arg1, (unsigned long)name, - arg3, arg4, arg5)); - unlock_user(name, arg2, 16); - return ret; - } - case PR_SET_NAME: - { - void *name =3D lock_user(VERIFY_READ, arg2, 16, 1); - if (!name) { - return -TARGET_EFAULT; - } - ret =3D get_errno(prctl(arg1, (unsigned long)name, - arg3, arg4, arg5)); - unlock_user(name, arg2, 0); - return ret; - } -#endif -#ifdef TARGET_MIPS - case TARGET_PR_GET_FP_MODE: - { - CPUMIPSState *env =3D ((CPUMIPSState *)cpu_env); - ret =3D 0; - if (env->CP0_Status & (1 << CP0St_FR)) { - ret |=3D TARGET_PR_FP_MODE_FR; - } - if (env->CP0_Config5 & (1 << CP0C5_FRE)) { - ret |=3D TARGET_PR_FP_MODE_FRE; - } - return ret; - } - case TARGET_PR_SET_FP_MODE: - { - CPUMIPSState *env =3D ((CPUMIPSState *)cpu_env); - bool old_fr =3D env->CP0_Status & (1 << CP0St_FR); - bool old_fre =3D env->CP0_Config5 & (1 << CP0C5_FRE); - bool new_fr =3D arg2 & TARGET_PR_FP_MODE_FR; - bool new_fre =3D arg2 & TARGET_PR_FP_MODE_FRE; - - const unsigned int known_bits =3D TARGET_PR_FP_MODE_FR | - TARGET_PR_FP_MODE_FRE; - - /* If nothing to change, return right away, successfully. */ - if (old_fr =3D=3D new_fr && old_fre =3D=3D new_fre) { - return 0; - } - /* Check the value is valid */ - if (arg2 & ~known_bits) { - return -TARGET_EOPNOTSUPP; - } - /* Setting FRE without FR is not supported. */ - if (new_fre && !new_fr) { - return -TARGET_EOPNOTSUPP; - } - if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) { - /* FR1 is not supported */ - return -TARGET_EOPNOTSUPP; - } - if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64)) - && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { - /* cannot set FR=3D0 */ - return -TARGET_EOPNOTSUPP; - } - if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) { - /* Cannot set FRE=3D1 */ - return -TARGET_EOPNOTSUPP; - } - - int i; - fpr_t *fpr =3D env->active_fpu.fpr; - for (i =3D 0; i < 32 ; i +=3D 2) { - if (!old_fr && new_fr) { - fpr[i].w[!FP_ENDIAN_IDX] =3D fpr[i + 1].w[FP_ENDIAN_ID= X]; - } else if (old_fr && !new_fr) { - fpr[i + 1].w[FP_ENDIAN_IDX] =3D fpr[i].w[!FP_ENDIAN_ID= X]; - } - } - - if (new_fr) { - env->CP0_Status |=3D (1 << CP0St_FR); - env->hflags |=3D MIPS_HFLAG_F64; - } else { - env->CP0_Status &=3D ~(1 << CP0St_FR); - env->hflags &=3D ~MIPS_HFLAG_F64; - } - if (new_fre) { - env->CP0_Config5 |=3D (1 << CP0C5_FRE); - if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { - env->hflags |=3D MIPS_HFLAG_FRE; - } - } else { - env->CP0_Config5 &=3D ~(1 << CP0C5_FRE); - env->hflags &=3D ~MIPS_HFLAG_FRE; - } - - return 0; - } -#endif /* MIPS */ -#ifdef TARGET_AARCH64 - case TARGET_PR_SVE_SET_VL: - /* - * We cannot support either PR_SVE_SET_VL_ONEXEC or - * PR_SVE_VL_INHERIT. Note the kernel definition - * of sve_vl_valid allows for VQ=3D512, i.e. VL=3D8192, - * even though the current architectural maximum is VQ=3D16. - */ - ret =3D -TARGET_EINVAL; - if (cpu_isar_feature(aa64_sve, env_archcpu(cpu_env)) - && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { - CPUARMState *env =3D cpu_env; - ARMCPU *cpu =3D env_archcpu(env); - uint32_t vq, old_vq; - - old_vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; - vq =3D MAX(arg2 / 16, 1); - vq =3D MIN(vq, cpu->sve_max_vq); - - if (vq < old_vq) { - aarch64_sve_narrow_vq(env, vq); - } - env->vfp.zcr_el[1] =3D vq - 1; - arm_rebuild_hflags(env); - ret =3D vq * 16; - } - return ret; - case TARGET_PR_SVE_GET_VL: - ret =3D -TARGET_EINVAL; - { - ARMCPU *cpu =3D env_archcpu(cpu_env); - if (cpu_isar_feature(aa64_sve, cpu)) { - ret =3D ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; - } - } - return ret; - case TARGET_PR_PAC_RESET_KEYS: - { - CPUARMState *env =3D cpu_env; - ARMCPU *cpu =3D env_archcpu(env); - - if (arg3 || arg4 || arg5) { - return -TARGET_EINVAL; - } - if (cpu_isar_feature(aa64_pauth, cpu)) { - int all =3D (TARGET_PR_PAC_APIAKEY | TARGET_PR_PAC_API= BKEY | - TARGET_PR_PAC_APDAKEY | TARGET_PR_PAC_APDBK= EY | - TARGET_PR_PAC_APGAKEY); - int ret =3D 0; - Error *err =3D NULL; - - if (arg2 =3D=3D 0) { - arg2 =3D all; - } else if (arg2 & ~all) { - return -TARGET_EINVAL; - } - if (arg2 & TARGET_PR_PAC_APIAKEY) { - ret |=3D qemu_guest_getrandom(&env->keys.apia, - sizeof(ARMPACKey), &er= r); - } - if (arg2 & TARGET_PR_PAC_APIBKEY) { - ret |=3D qemu_guest_getrandom(&env->keys.apib, - sizeof(ARMPACKey), &er= r); - } - if (arg2 & TARGET_PR_PAC_APDAKEY) { - ret |=3D qemu_guest_getrandom(&env->keys.apda, - sizeof(ARMPACKey), &er= r); - } - if (arg2 & TARGET_PR_PAC_APDBKEY) { - ret |=3D qemu_guest_getrandom(&env->keys.apdb, - sizeof(ARMPACKey), &er= r); - } - if (arg2 & TARGET_PR_PAC_APGAKEY) { - ret |=3D qemu_guest_getrandom(&env->keys.apga, - sizeof(ARMPACKey), &er= r); - } - if (ret !=3D 0) { - /* - * Some unknown failure in the crypto. The best - * we can do is log it and fail the syscall. - * The real syscall cannot fail this way. - */ - qemu_log_mask(LOG_UNIMP, - "PR_PAC_RESET_KEYS: Crypto failure: = %s", - error_get_pretty(err)); - error_free(err); - return -TARGET_EIO; - } - return 0; - } - } - return -TARGET_EINVAL; - case TARGET_PR_SET_TAGGED_ADDR_CTRL: - { - abi_ulong valid_mask =3D TARGET_PR_TAGGED_ADDR_ENABLE; - CPUARMState *env =3D cpu_env; - ARMCPU *cpu =3D env_archcpu(env); - - if (cpu_isar_feature(aa64_mte, cpu)) { - valid_mask |=3D TARGET_PR_MTE_TCF_MASK; - valid_mask |=3D TARGET_PR_MTE_TAG_MASK; - } - - if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) { - return -TARGET_EINVAL; - } - env->tagged_addr_enable =3D arg2 & TARGET_PR_TAGGED_ADDR_E= NABLE; - - if (cpu_isar_feature(aa64_mte, cpu)) { - switch (arg2 & TARGET_PR_MTE_TCF_MASK) { - case TARGET_PR_MTE_TCF_NONE: - case TARGET_PR_MTE_TCF_SYNC: - case TARGET_PR_MTE_TCF_ASYNC: - break; - default: - return -EINVAL; - } - - /* - * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. - * Note that the syscall values are consistent with hw. - */ - env->cp15.sctlr_el[1] =3D - deposit64(env->cp15.sctlr_el[1], 38, 2, - arg2 >> TARGET_PR_MTE_TCF_SHIFT); - - /* - * Write PR_MTE_TAG to GCR_EL1[Exclude]. - * Note that the syscall uses an include mask, - * and hardware uses an exclude mask -- invert. - */ - env->cp15.gcr_el1 =3D - deposit64(env->cp15.gcr_el1, 0, 16, - ~arg2 >> TARGET_PR_MTE_TAG_SHIFT); - arm_rebuild_hflags(env); - } - return 0; - } - case TARGET_PR_GET_TAGGED_ADDR_CTRL: - { - abi_long ret =3D 0; - CPUARMState *env =3D cpu_env; - ARMCPU *cpu =3D env_archcpu(env); - - if (arg2 || arg3 || arg4 || arg5) { - return -TARGET_EINVAL; - } - if (env->tagged_addr_enable) { - ret |=3D TARGET_PR_TAGGED_ADDR_ENABLE; - } - if (cpu_isar_feature(aa64_mte, cpu)) { - /* See above. */ - ret |=3D (extract64(env->cp15.sctlr_el[1], 38, 2) - << TARGET_PR_MTE_TCF_SHIFT); - ret =3D deposit64(ret, TARGET_PR_MTE_TAG_SHIFT, 16, - ~env->cp15.gcr_el1); - } - return ret; - } -#endif /* AARCH64 */ - case PR_GET_SECCOMP: - case PR_SET_SECCOMP: - /* Disable seccomp to prevent the target disabling syscalls we - * need. */ - return -TARGET_EINVAL; - default: - /* Most prctl options have no pointer arguments */ - return get_errno(prctl(arg1, arg2, arg3, arg4, arg5)); - } + return do_prctl(cpu_env, arg1, arg2, arg3, arg4, arg5); break; #ifdef TARGET_NR_arch_prctl case TARGET_NR_arch_prctl: --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635619139778726.3338195934501; Sat, 30 Oct 2021 11:38:59 -0700 (PDT) Received: from localhost ([::1]:34338 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgtFq-00068g-Nk for importer@patchew.org; Sat, 30 Oct 2021 14:38:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58892) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs21-0001gI-Le for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:37 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:38680) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1z-0002JM-3F for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:37 -0400 Received: by mail-pf1-x432.google.com with SMTP id l1so5883533pfu.5 for ; Sat, 30 Oct 2021 10:20:34 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OxMgM7wzD4BcAcUx2qJmodE4BwJ9QwGNSAt09qoFyFU=; b=mDBOvEjWkGkgjoMtShmnNxJDU4RQJedFJFxPCOu0ivToaxhErXKlx0cAQWkRnR8wMw TY6phnyTr7hpmscfJCzpMzruO+e2rN8Lkj7yYf3QnoFX8hME1IjjiJK5NkCts8QVqmN1 U+wL/l3pBgZpIZ1T6BAFnFjpHpojWtd0Euqkrga2GiUpBVb++F5cltsaXw1HQBnbQO6z VbfDKEOgIfOjm0yzVxQxYI40X5/5c5MdTgDd16C64CD32o+fIeqji8KqzH+cn5ZJhYGa EQOImi69+nL+lujFceyJ7SBxWmgMZWAKz5b3i1y+beHwmKo5mg/mRqcccHDLYT2ctBkI xu3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OxMgM7wzD4BcAcUx2qJmodE4BwJ9QwGNSAt09qoFyFU=; b=f/Oe9Q4QyN3WodPvccM9qxk12rlBkKZZxI1OO0bBG0xWSLn/NRX6Ar66NeCz2sFTnR MvF8/gMp+mePfw45gdbO8vgbIUjQk91f/QXO7mgRyiVVVW4jVZKrOCzwrAIeQPbutZhG B5qgvqnn9gB86w4GScrHtlW4LF6gXKJHutwuOMXvksj3acCRim6/uceSsF56eX5Mr44c PhHuz6h+KiK+uoOlLzjvrxLbKH9lJ73LpwZW1FWlJFelEbWh8SoId2Dm5EwrWDV7I+6u Pixy+CjRvwwOso4ErzT6yWqZ6R1tD5C1TRD6Q2AySY/AeqQfM1pz3JYH0RUqG2V+YE3r ycTg== X-Gm-Message-State: AOAM532I8lukv/TVIiu3eYQ5rQIDunCafX5CBf5EGUss0cDuBd2ZveED pQqWzMAU7C5zpdNZlDDn4z38fK9Q3BngpQ== X-Google-Smtp-Source: ABdhPJwWDKaaVloWakpwFSsNM3F5yCh46iUSeSRknyCWkZg5DRZnZKxf49Pra5oeCTuf1UIK0WOxMg== X-Received: by 2002:a63:7c0d:: with SMTP id x13mr13782375pgc.410.1635614433462; Sat, 30 Oct 2021 10:20:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 62/66] linux-user: Disable more prctl subcodes Date: Sat, 30 Oct 2021 10:16:31 -0700 Message-Id: <20211030171635.1689530-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635619140699100001 Content-Type: text/plain; charset="utf-8" Create a list of subcodes that we want to pass on, a list of subcodes that should not be passed on because they would affect the running qemu itself, and a list that probably could be implemented but require extra work. Do not pass on unknown subcodes. Signed-off-by: Richard Henderson --- linux-user/syscall.c | 56 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 52 insertions(+), 4 deletions(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index a417396981..7635c2397a 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6334,6 +6334,13 @@ abi_long do_arch_prctl(CPUX86State *env, int code, a= bi_ulong addr) # define PR_MTE_TAG_SHIFT 3 # define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) #endif +#ifndef PR_SET_IO_FLUSHER +# define PR_SET_IO_FLUSHER 57 +# define PR_GET_IO_FLUSHER 58 +#endif +#ifndef PR_SET_SYSCALL_USER_DISPATCH +# define PR_SET_SYSCALL_USER_DISPATCH 59 +#endif =20 #include "target_prctl.h" =20 @@ -6430,13 +6437,54 @@ static abi_long do_prctl(CPUArchState *env, abi_lon= g option, abi_long arg2, return -TARGET_EINVAL; } return do_prctl_get_tagged_addr_ctrl(env); + + case PR_GET_DUMPABLE: + case PR_SET_DUMPABLE: + case PR_GET_KEEPCAPS: + case PR_SET_KEEPCAPS: + case PR_GET_TIMING: + case PR_SET_TIMING: + case PR_GET_TIMERSLACK: + case PR_SET_TIMERSLACK: + case PR_MCE_KILL: + case PR_MCE_KILL_GET: + case PR_GET_NO_NEW_PRIVS: + case PR_SET_NO_NEW_PRIVS: + case PR_GET_IO_FLUSHER: + case PR_SET_IO_FLUSHER: + /* Some prctl options have no pointer arguments and we can pass on= . */ + return get_errno(prctl(option, arg2, arg3, arg4, arg5)); + + case PR_GET_CHILD_SUBREAPER: + case PR_SET_CHILD_SUBREAPER: + case PR_GET_SPECULATION_CTRL: + case PR_SET_SPECULATION_CTRL: + case PR_GET_TID_ADDRESS: + /* TODO */ + return -TARGET_EINVAL; + + case PR_GET_FPEXC: + case PR_SET_FPEXC: + /* Was used for SPE on PowerPC. */ + return -TARGET_EINVAL; + + case PR_GET_ENDIAN: + case PR_SET_ENDIAN: + case PR_GET_FPEMU: + case PR_SET_FPEMU: + case PR_SET_MM: case PR_GET_SECCOMP: case PR_SET_SECCOMP: - /* Disable seccomp to prevent the target disabling syscalls we nee= d. */ - return -TARGET_EINVAL; + case PR_SET_SYSCALL_USER_DISPATCH: + case PR_GET_THP_DISABLE: + case PR_SET_THP_DISABLE: + case PR_GET_TSC: + case PR_SET_TSC: + case PR_GET_UNALIGN: + case PR_SET_UNALIGN: default: - /* Most prctl options have no pointer arguments */ - return get_errno(prctl(option, arg2, arg3, arg4, arg5)); + /* Disable to prevent the target disabling stuff we need. */ + return -TARGET_EINVAL; } } =20 --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635619335360106.40325514610606; Sat, 30 Oct 2021 11:42:15 -0700 (PDT) Received: from localhost ([::1]:40698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgtIz-00022q-9R for importer@patchew.org; Sat, 30 Oct 2021 14:42:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58900) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs22-0001gQ-0j for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:38 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:40585) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs1z-0002Jg-Uj for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:37 -0400 Received: by mail-pj1-x1032.google.com with SMTP id n36-20020a17090a5aa700b0019fa884ab85so13062685pji.5 for ; Sat, 30 Oct 2021 10:20:35 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c4K4bq+N5IErCjdHSmC7m5HyJJ6X1g8RLx33K/0SW0g=; b=xRnszdL5K6Qc4t8bKFpnXPhdx0itTKql3IpCpji3+ivJ7REI7VZdH/gBxZv72piRsQ +OxFG/rnFN7K+KpmwCCDnlQNQSTSzxbroONbnE+pNURzMeP91sQvGsx2fJML+8eYxg4r 4h9icin+55ypsU6ln69qihSr9sdDQxqluhdHrtaWIESNLQmWFjAIgPkzr6uFG8hTIoYU iWKoVv2M2KEvzbzyjtZnpKODWnzD545KSmgHg0Ns9R12xY6Uz25N85O+ehV2EoetFRYi Fmuw8Cy9I64ZxZVC0J0UYUQSrv9BsAyaj5nMq6HfjPNCYwAL3+RAa+xpsBBpDep9B/Yt MMjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c4K4bq+N5IErCjdHSmC7m5HyJJ6X1g8RLx33K/0SW0g=; b=1hZ/T3ILGemnc7ym0iLnl4TyfptzqhId4cIWTd1IatsfWBfIaZ9zoZvcuX0Fstc7lY JTqIhlaVE/NmHq6ONPKbMVC9/UY0Y3JFI2W3LvP7RPmPRVEDqvAy6OxPDwr76r8NOAXo JlyBgs6qP1OstWwRKwVMPocZZzmwTnXoqd027N9FtBrpZPyax/sOtyTNC13cpRS9bIpd YnxxQvVelAu1ykVZoAysWyYl/bbHIWa+WfnI31ljAoE6fU5KbmApxMMIROjxCkh7pb41 lv2RcRFcLASTb7snvWU9wlB+4f4Q5ZuB6VHAhq9Mp8veLylNwfLDfwbxAmjd3aIITujG J1EQ== X-Gm-Message-State: AOAM533XcaxmbQdlc0g03uUDeH68Vc1v8bmxa4hE8Fv1b99knHUdEtB8 41Gy1ggoSEKqizEy8v+qhcFSeRxL44bftw== X-Google-Smtp-Source: ABdhPJzcXvL0ssvpiNCENsx99fPa8d3V4aqUtxLqaHG3CNBzgzuCS2EHeVU8/DWob9hauXL6bOG0Ng== X-Received: by 2002:a17:90b:1e4a:: with SMTP id pi10mr19226716pjb.142.1635614434568; Sat, 30 Oct 2021 10:20:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 63/66] linux-user: Add code for PR_GET/SET_UNALIGN Date: Sat, 30 Oct 2021 10:16:32 -0700 Message-Id: <20211030171635.1689530-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635619335905100003 Content-Type: text/plain; charset="utf-8" This requires extra work for each target, but adds the common syscall code, and the necessary flag in CPUState. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 3 +++ linux-user/generic/target_prctl_unalign.h | 27 +++++++++++++++++++++++ cpu.c | 20 ++++++++++++----- linux-user/syscall.c | 13 +++++++++-- 4 files changed, 56 insertions(+), 7 deletions(-) create mode 100644 linux-user/generic/target_prctl_unalign.h diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 1a10497af3..6202bbf9c3 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -412,6 +412,9 @@ struct CPUState { =20 bool ignore_memory_transaction_failures; =20 + /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ + bool prctl_unalign_sigbus; + struct hax_vcpu_state *hax_vcpu; =20 struct hvf_vcpu_state *hvf; diff --git a/linux-user/generic/target_prctl_unalign.h b/linux-user/generic= /target_prctl_unalign.h new file mode 100644 index 0000000000..bc3b83af2a --- /dev/null +++ b/linux-user/generic/target_prctl_unalign.h @@ -0,0 +1,27 @@ +/* + * Generic prctl unalign functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef GENERIC_TARGET_PRCTL_UNALIGN_H +#define GENERIC_TARGET_PRCTL_UNALIGN_H + +static abi_long do_prctl_get_unalign(CPUArchState *env, target_long arg2) +{ + CPUState *cs =3D env_cpu(env); + uint32_t res =3D PR_UNALIGN_NOPRINT; + if (cs->prctl_unalign_sigbus) { + res |=3D PR_UNALIGN_SIGBUS; + } + return put_user_u32(res, arg2); +} +#define do_prctl_get_unalign do_prctl_get_unalign + +static abi_long do_prctl_set_unalign(CPUArchState *env, target_long arg2) +{ + env_cpu(env)->prctl_unalign_sigbus =3D arg2 & PR_UNALIGN_SIGBUS; + return 0; +} +#define do_prctl_set_unalign do_prctl_set_unalign + +#endif /* GENERIC_TARGET_PRCTL_UNALIGN_H */ diff --git a/cpu.c b/cpu.c index 9bce67ef55..9e388d9cd3 100644 --- a/cpu.c +++ b/cpu.c @@ -179,13 +179,23 @@ void cpu_exec_unrealizefn(CPUState *cpu) cpu_list_remove(cpu); } =20 +/* + * This can't go in hw/core/cpu.c because that file is compiled only + * once for both user-mode and system builds. + */ static Property cpu_common_props[] =3D { -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY /* - * Create a memory property for softmmu CPU object, - * so users can wire up its memory. (This can't go in hw/core/cpu.c - * because that file is compiled only once for both user-mode - * and system builds.) The default if no link is set up is to use + * Create a property for the user-only object, so users can + * adjust prctl(PR_SET_UNALIGN) from the command-line. + * Has no effect if the target does not support the feature. + */ + DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState, + prctl_unalign_sigbus, false), +#else + /* + * Create a memory property for softmmu CPU object, so users can + * wire up its memory. The default if no link is set up is to use * the system address space. */ DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 7635c2397a..ac3bc8a330 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6375,6 +6375,12 @@ static abi_long do_prctl_inval1(CPUArchState *env, a= bi_long arg2) #ifndef do_prctl_get_tagged_addr_ctrl #define do_prctl_get_tagged_addr_ctrl do_prctl_inval0 #endif +#ifndef do_prctl_get_unalign +#define do_prctl_get_unalign do_prctl_inval1 +#endif +#ifndef do_prctl_set_unalign +#define do_prctl_set_unalign do_prctl_inval1 +#endif =20 static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5) @@ -6438,6 +6444,11 @@ static abi_long do_prctl(CPUArchState *env, abi_long= option, abi_long arg2, } return do_prctl_get_tagged_addr_ctrl(env); =20 + case PR_GET_UNALIGN: + return do_prctl_get_unalign(env, arg2); + case PR_SET_UNALIGN: + return do_prctl_set_unalign(env, arg2); + case PR_GET_DUMPABLE: case PR_SET_DUMPABLE: case PR_GET_KEEPCAPS: @@ -6480,8 +6491,6 @@ static abi_long do_prctl(CPUArchState *env, abi_long = option, abi_long arg2, case PR_SET_THP_DISABLE: case PR_GET_TSC: case PR_SET_TSC: - case PR_GET_UNALIGN: - case PR_SET_UNALIGN: default: /* Disable to prevent the target disabling stuff we need. */ return -TARGET_EINVAL; --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635619892754677.0024031684163; Sat, 30 Oct 2021 11:51:32 -0700 (PDT) Received: from localhost ([::1]:58952 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgtRz-0006H4-Ok for importer@patchew.org; Sat, 30 Oct 2021 14:51:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58922) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs23-0001kV-FI for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:39 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:37652) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs20-0002Jp-Ro for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:39 -0400 Received: by mail-pf1-x432.google.com with SMTP id y20so1550988pfi.4 for ; Sat, 30 Oct 2021 10:20:36 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WQTgDhCLBaZE1Cn7juEE6p/otG9i2OoS7z9LWg/JxZA=; b=Ow0A6drr87MlfffABYSRoEcXRPGOlqdfxWYxo87/DrgCBRgC79aFpWOcX2aVCh9zh4 m+xy7VlQyXrQ7YpDHKoZbN0zV2FXQTKNxWULmlDU/zTEGP/VQrCBNqjmouF2qkGlpu9e 9NbgH0vSLWXe7cQ0C8J6ax9OVv9ASy5/kD/JcdaCpP56ddcy2ItzK6BGAjmhxxVOs5Eo flr/u+HPxCoWiHRicwfGnVhn+NHP0YWUiJws1Yvy2wyqoL0zUWnRnfAviyzSbP4njQCK NH1bimZeylrQxJTVHVimZLKi23FX2FF1XiMxP6fkZYvfeQr5306u8BmAb+2T3XCHqpUf jepQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WQTgDhCLBaZE1Cn7juEE6p/otG9i2OoS7z9LWg/JxZA=; b=JBKd9eG+c0m2PV2sjlCdrlCdjnXVb5RFsiJMnrJRaRGe5P1NkdgPxh56VDP+uKi16x N2sJ2EyLhsjHyAeMVJ79auee4dP7MLzhaHa2owXX0bMF3tx2306uPP1i7EU6WgxxJFvz ncXeDrW3E8DQuxxnxhOVWEuGnh1eTblKY12o1ezDTG0pyIzemHaeUsFnNZTvnZP3yVpD WC9gDB3yDptGDjWD5Zp7QYufup82upYDtIHBhAVpjwQptUgtJKpM1cZ1pEwHc5NODN1+ SgTRcx8M0FFKGKItatanJ+AX18deUYpXij4kQoBa79ycxdvvfw8y0EZe9crDNEIR+Pik S+Uw== X-Gm-Message-State: AOAM533U14MJ/fW6zTTIonzuIx1ymTYk1jJBZ43FRbWN7AOiOi8fLAkO rRemUDiTrP8hwvnE2YOZfI4L96YclbhpeA== X-Google-Smtp-Source: ABdhPJxbQh4rxnvQX01/qj+z5r6QW4cN5yLEV8vBklMYFWEHy4n7jE9/pLUZdU+SfQufk28UxkeHGA== X-Received: by 2002:a63:7c41:: with SMTP id l1mr13549463pgn.372.1635614435600; Sat, 30 Oct 2021 10:20:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 64/66] target/alpha: Implement prctl_unalign_sigbus Date: Sat, 30 Oct 2021 10:16:33 -0700 Message-Id: <20211030171635.1689530-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635619893784100001 Content-Type: text/plain; charset="utf-8" Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson --- linux-user/alpha/target_prctl.h | 2 +- target/alpha/cpu.h | 5 +++++ target/alpha/translate.c | 31 ++++++++++++++++++++++--------- 3 files changed, 28 insertions(+), 10 deletions(-) diff --git a/linux-user/alpha/target_prctl.h b/linux-user/alpha/target_prct= l.h index eb53b31ad5..5629ddbf39 100644 --- a/linux-user/alpha/target_prctl.h +++ b/linux-user/alpha/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index afd975c878..e819211503 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -383,6 +383,8 @@ enum { #define ENV_FLAG_TB_MASK \ (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN) =20 +#define TB_FLAG_UNALIGN (1u << 1) + static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) { int ret =3D env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_= IDX; @@ -470,6 +472,9 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *= env, target_ulong *pc, *pc =3D env->pc; *cs_base =3D 0; *pflags =3D env->flags & ENV_FLAG_TB_MASK; +#ifdef CONFIG_USER_ONLY + *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif } =20 #ifdef CONFIG_USER_ONLY diff --git a/target/alpha/translate.c b/target/alpha/translate.c index a4c3f43e72..208ae5fbd5 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -45,7 +45,9 @@ typedef struct DisasContext DisasContext; struct DisasContext { DisasContextBase base; =20 -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + MemOp unalign; +#else uint64_t palbr; #endif uint32_t tbflags; @@ -68,6 +70,12 @@ struct DisasContext { TCGv sink; }; =20 +#ifdef CONFIG_USER_ONLY +#define UNALIGN(C) (C)->unalign +#else +#define UNALIGN(C) 0 +#endif + /* Target-specific return values from translate_one, indicating the state of the TB. Note that DISAS_NEXT indicates that we are not exiting the TB. */ @@ -270,7 +278,7 @@ static inline DisasJumpType gen_invalid(DisasContext *c= tx) static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_f(dest, tmp32); tcg_temp_free_i32(tmp32); } @@ -278,7 +286,7 @@ static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv = addr) static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv tmp =3D tcg_temp_new(); - tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); gen_helper_memory_to_g(dest, tmp); tcg_temp_free(tmp); } @@ -286,14 +294,14 @@ static void gen_ldg(DisasContext *ctx, TCGv dest, TCG= v addr) static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_s(dest, tmp32); tcg_temp_free_i32(tmp32); } =20 static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr) { - tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); } =20 static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, @@ -324,6 +332,8 @@ static void gen_load_int(DisasContext *ctx, int ra, int= rb, int32_t disp16, tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { tcg_gen_andi_i64(addr, addr, ~0x7); + } else if (!locked) { + op |=3D UNALIGN(ctx); } =20 dest =3D ctx->ir[ra]; @@ -340,7 +350,7 @@ static void gen_stf(DisasContext *ctx, TCGv src, TCGv a= ddr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); gen_helper_f_to_memory(tmp32, addr); - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); tcg_temp_free_i32(tmp32); } =20 @@ -348,7 +358,7 @@ static void gen_stg(DisasContext *ctx, TCGv src, TCGv a= ddr) { TCGv tmp =3D tcg_temp_new(); gen_helper_g_to_memory(tmp, src); - tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); tcg_temp_free(tmp); } =20 @@ -356,13 +366,13 @@ static void gen_sts(DisasContext *ctx, TCGv src, TCGv= addr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); gen_helper_s_to_memory(tmp32, src); - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); tcg_temp_free_i32(tmp32); } =20 static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr) { - tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); } =20 static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, @@ -383,6 +393,8 @@ static void gen_store_int(DisasContext *ctx, int ra, in= t rb, int32_t disp16, tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { tcg_gen_andi_i64(addr, addr, ~0x7); + } else { + op |=3D UNALIGN(ctx); } =20 src =3D load_gpr(ctx, ra); @@ -2942,6 +2954,7 @@ static void alpha_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cpu) =20 #ifdef CONFIG_USER_ONLY ctx->ir =3D cpu_std_ir; + ctx->unalign =3D (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN= ); #else ctx->palbr =3D env->palbr; ctx->ir =3D (ctx->tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_i= r); --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635619452925765.3659971608748; Sat, 30 Oct 2021 11:44:12 -0700 (PDT) Received: from localhost ([::1]:46284 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgtKt-0005nw-TR for importer@patchew.org; Sat, 30 Oct 2021 14:44:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58930) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs23-0001lh-R2 for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:41 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:36694) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs21-0002Ju-MN for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:39 -0400 Received: by mail-pj1-x102c.google.com with SMTP id o10-20020a17090a3d4a00b001a6555878a8so1592883pjf.1 for ; Sat, 30 Oct 2021 10:20:37 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7GFp0BnjNqf+HN7On2kB2ojF6HuQfaO5DIVgtLsXYvY=; b=ilCldCytIC6SbLn39fo3LG5OeVlnSLX0Vshw+dajfX8lZBsoEfRoJAI3lIwP9s9seq eV6hhHRDJMPJs/iWBvKBywz4N0Ux3Qym/tCybYJvsG3etJEwVkV3BsH70WP91pw9l5X5 3Lgo9eBBJPHNpO+yLLAoGeAThYhZ8Itp5d2cwAJZzLV7Yf54wu6BFXveK1TfRV7qRL5W 3RPqea0kDNOrzB4HWUL3GVkZKHcnUoDbsG04fKKCx4jNPAgg+Nq65Bf7jeQBo02HENil AazemyP62bsn33BgxWt5hFsO31SSPmYXVlX6h+glx3oCQrFpj10YkIX6gWM7nkaaj8lF iTpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7GFp0BnjNqf+HN7On2kB2ojF6HuQfaO5DIVgtLsXYvY=; b=QKfJZ080WvpWeWkzOOrE7CI0QRUj1xy4wbTh1UOBVFls2wRa/Fyd6fOfCeobpOaqw8 MwvXMLF5gX0B+ZqM3HHSn2hQoPi16uXe6JdR5SgE7UcxbHSgZ/q5K5KYQJlHfhslc7jb 56/zAgfiwrEWJoklyWDhpy+RGfZMtrakPoYBfjiTEUdnW85ihQPXC2a7NFxOj70fcdES P+chbO/O7l5OA86gs6M/nx1MuE4vTnVM0K7y+ZOsQogNSveVhDDGSZcMwaIfkdx7X8sC wXPBM3WqLsSHxvFS4geo5T0BKXmnFMsyDv1t2CH1+B8ri91WSBocHpQivkUgTowwMlTw HDPw== X-Gm-Message-State: AOAM532nmd5iV3IvPNLen4zBWcmWKPn0YswLFpygyxnoI3P+pzjsZ/R4 vf64MGxCmR6aOz9Ns+QfJ0ORZ+r3vB+MMw== X-Google-Smtp-Source: ABdhPJzdfkfEEjRFJacsX8DSu5ODP47T/7cPSH98v16tT/fS3SzqV35Pft6bqtwoB73EU0v1/pLQTg== X-Received: by 2002:a17:90a:7d11:: with SMTP id g17mr18820712pjl.19.1635614436512; Sat, 30 Oct 2021 10:20:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 65/66] target/hppa: Implement prctl_unalign_sigbus Date: Sat, 30 Oct 2021 10:16:34 -0700 Message-Id: <20211030171635.1689530-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635619453477100001 Content-Type: text/plain; charset="utf-8" Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson --- linux-user/hppa/target_prctl.h | 2 +- target/hppa/cpu.h | 5 ++++- target/hppa/translate.c | 19 +++++++++++++++---- 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h index eb53b31ad5..5629ddbf39 100644 --- a/linux-user/hppa/target_prctl.h +++ b/linux-user/hppa/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 294fd7297f..45fd338b02 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -259,12 +259,14 @@ static inline target_ulong hppa_form_gva(CPUHPPAState= *env, uint64_t spc, return hppa_form_gva_psw(env->psw, spc, off); } =20 -/* Since PSW_{I,CB} will never need to be in tb->flags, reuse them. +/* + * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the * same value. */ #define TB_FLAG_SR_SAME PSW_I #define TB_FLAG_PRIV_SHIFT 8 +#define TB_FLAG_UNALIGN 0x400 =20 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *p= c, target_ulong *cs_base, @@ -279,6 +281,7 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *e= nv, target_ulong *pc, #ifdef CONFIG_USER_ONLY *pc =3D env->iaoq_f & -4; *cs_base =3D env->iaoq_b & -4; + flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; #else /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ flags |=3D env->psw & (PSW_W | PSW_C | PSW_D); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3b9744deb4..f555503024 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -272,8 +272,18 @@ typedef struct DisasContext { int mmu_idx; int privilege; bool psw_n_nonzero; + +#ifdef CONFIG_USER_ONLY + MemOp unalign; +#endif } DisasContext; =20 +#ifdef CONFIG_USER_ONLY +#define UNALIGN(C) (C)->unalign +#else +#define UNALIGN(C) 0 +#endif + /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ static int expand_sm_imm(DisasContext *ctx, int val) { @@ -1473,7 +1483,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 de= st, unsigned rb, =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); - tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1491,7 +1501,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 de= st, unsigned rb, =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); - tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1509,7 +1519,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 s= rc, unsigned rb, =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); - tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1527,7 +1537,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 s= rc, unsigned rb, =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); - tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -4102,6 +4112,7 @@ static void hppa_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->mmu_idx =3D MMU_USER_IDX; ctx->iaoq_f =3D ctx->base.pc_first | MMU_USER_IDX; ctx->iaoq_b =3D ctx->base.tb->cs_base | MMU_USER_IDX; + ctx->unalign =3D (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIG= N); #else ctx->privilege =3D (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; ctx->mmu_idx =3D (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_ID= X); --=20 2.25.1 From nobody Mon Feb 9 17:48:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635617739470717.0701648861974; Sat, 30 Oct 2021 11:15:39 -0700 (PDT) Received: from localhost ([::1]:50520 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgstG-0003FZ-2U for importer@patchew.org; Sat, 30 Oct 2021 14:15:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58946) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgs25-0001mJ-Ff for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:43 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:54101) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgs22-0002K8-Ly for qemu-devel@nongnu.org; Sat, 30 Oct 2021 13:20:41 -0400 Received: by mail-pj1-x102d.google.com with SMTP id iq11so2455608pjb.3 for ; Sat, 30 Oct 2021 10:20:38 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id k14sm9584798pji.45.2021.10.30.10.20.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:20:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5ythuo4u3wTG6v82m8MPeTsA+ifWASlVSxLmACYwOII=; b=loDH8jC8J8rJu3SC39EETsZZaJqgdRv+Bz4DYWO1PFJcW53Po2NZvPaBhNlKI7pAFV dA3dfEx4ZVV7whbW3vCqc61kDip7j4gEmEZJ01csN77jL4hIMHTZM539391kagfxtneG f+Ok7A3CHGlCgG/W0/68SQvwpa04LqYm12rMdXZfoKEzuYMVS+UsQ90yhit7VJBuAf2v 6g+ziyFv6C7VuIa/ZJApWQbmpNymPRySD/nI+SkPENJhbDAUiTy6zVABZKOch41X8FrW xHCkT+zmXaNttw+e8lQT91GkUbKSZZ5lFCC5fUQObNjVKr+G/OwYerUcQOlGakHz1Dsd vttQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5ythuo4u3wTG6v82m8MPeTsA+ifWASlVSxLmACYwOII=; b=vp7oI7i1O1XxadusGS6NB+BRPWBsaJaUIgZ8zirWIRXECre/Bq5VmPcQ1spmK5Knkz J+j4LUqqFY073MjlV2t/EBOj8ndIozCjCPPgiKpiHA/jzn4ekxWfGudX025d+hMH5cJn 4tGIKxypVT2cXx/X/FFTLwTr7zIgn+J4YiOFTAVRF1N3mPXRncqPT4Pird/jy1vpuHbj qmAW95edL0zTKD2orCqCFkfgJZxn5yjlsu1VdOC9UoKrGhUHRPS/5jaz+fPaD0yBSpvT R41Ath4vW3JgU9WNAoX3C7NxpyXADTiSe64wpDEwfpq6WboO+ulRn9YU/MjRIWOM4f7N cC9A== X-Gm-Message-State: AOAM532sO4zURtaHQUbRBmXglN7Injv6djGXS7+pfHTK5IktZdrgd183 Adgdw6InGGui+lSIkvqVo3XYS947994nSA== X-Google-Smtp-Source: ABdhPJz++27hZKkskFLhxiNy48WA8A5njo9uCO7ru5YvyZe4hAj84GCESFSaTTN8vonS/ZAV8PGfsA== X-Received: by 2002:a17:90a:9bc1:: with SMTP id b1mr15242270pjw.49.1635614437319; Sat, 30 Oct 2021 10:20:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 66/66] target/sh4: Implement prctl_unalign_sigbus Date: Sat, 30 Oct 2021 10:16:35 -0700 Message-Id: <20211030171635.1689530-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org> References: <20211030171635.1689530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635617740886100001 Content-Type: text/plain; charset="utf-8" Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. The Linux kernel does not handle all memory operations: no floating-point and no MAC. Signed-off-by: Richard Henderson --- linux-user/sh4/target_prctl.h | 2 +- target/sh4/cpu.h | 4 +++ target/sh4/translate.c | 50 ++++++++++++++++++++++++----------- 3 files changed, 39 insertions(+), 17 deletions(-) diff --git a/linux-user/sh4/target_prctl.h b/linux-user/sh4/target_prctl.h index eb53b31ad5..5629ddbf39 100644 --- a/linux-user/sh4/target_prctl.h +++ b/linux-user/sh4/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 4cfb109f56..fb9dd9db2f 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -83,6 +83,7 @@ #define DELAY_SLOT_RTE (1 << 2) =20 #define TB_FLAG_PENDING_MOVCA (1 << 3) +#define TB_FLAG_UNALIGN (1 << 4) =20 #define GUSA_SHIFT 4 #ifdef CONFIG_USER_ONLY @@ -373,6 +374,9 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *en= v, target_ulong *pc, | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-= 30 */ | (env->sr & (1u << SR_FD)) /* Bit 15 */ | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ +#ifdef CONFIG_USER_ONLY + *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif } =20 #endif /* SH4_CPU_H */ diff --git a/target/sh4/translate.c b/target/sh4/translate.c index ce5d674a52..c959ce1508 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -50,8 +50,10 @@ typedef struct DisasContext { =20 #if defined(CONFIG_USER_ONLY) #define IS_USER(ctx) 1 +#define UNALIGN(C) (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : 0) #else #define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD))) +#define UNALIGN(C) 0 #endif =20 /* Target-specific values for ctx->base.is_jmp. */ @@ -495,7 +497,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -503,7 +506,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -558,19 +562,23 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_UB); return; case 0x2001: /* mov.w Rm,@Rn */ - tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, + MO_TEUW | UNALIGN(ctx)); return; case 0x2002: /* mov.l Rm,@Rn */ - tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, + MO_TEUL | UNALIGN(ctx)); return; case 0x6000: /* mov.b @Rm,Rn */ tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB); return; case 0x6001: /* mov.w @Rm,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESW | UNALIGN(ctx)); return; case 0x6002: /* mov.l @Rm,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESL | UNALIGN(ctx)); return; case 0x2004: /* mov.b Rm,@-Rn */ { @@ -586,7 +594,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 2); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUW | UNALIGN(ctx)); tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); } @@ -595,7 +604,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 4); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUL | UNALIGN(ctx)); tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); } @@ -606,12 +616,14 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1); return; case 0x6005: /* mov.w @Rm+,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESW | UNALIGN(ctx)); if ( B11_8 !=3D B7_4 ) tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); return; case 0x6006: /* mov.l @Rm+,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESL | UNALIGN(ctx)); if ( B11_8 !=3D B7_4 ) tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); return; @@ -627,7 +639,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUW | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -635,7 +648,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -651,7 +665,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESW | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -659,7 +674,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -1253,7 +1269,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); - tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, + MO_TEUW | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -1269,7 +1286,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); - tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, + MO_TESW | UNALIGN(ctx)); tcg_temp_free(addr); } return; --=20 2.25.1