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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id r15sm10003784wru.9.2021.10.30.10.08.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 10:08:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4GsX7ujibAVB1FOlsAotPgTfAySJiSfKMFDwh7bY+6E=; b=fy60szucdv+blTBwDwG+A0O85Ft8AqXWS2b4kWqvmuH6/YBLXItzI5un2W+vhOZ/YG 4rR3UwJ43tN06JWCnHQKHkaOoafrTRGCr8X34JCQgU1Kv4bUk3Ky83aZ1d7nse9dusQt McJU4n+5/O3zT66RjcB9aX65oaZ5HAFPdS+QrZYEcvZFI1UKW5A807CVslTjZ0mK2Rbm z+nPTlQuyMH4i5TcNoWr1YMo8ztXfoz63OdlOWEWg+//Lu09q+WlEdwAhnwoFZOBU4Rl 0HW+gqDZ5AUx4DR5vv3APwcxhOIxN6TJ6RnAmb65yx4nGIgm/Z50TAvZY/wMODLKILhc SaYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=4GsX7ujibAVB1FOlsAotPgTfAySJiSfKMFDwh7bY+6E=; b=IyNDNT1gii3FxyCQ+Y2NfwUimZBJfxSdV2Un28k2POgDIoI5of3ZMLKcA78978ZZui e4bfOi6jaXmIpPxRSGOKaeBjjA6em6jOXGGhJSajPrfjsphAlrrtrCFZz1aI2az4XHcQ 0E5jPB8aa/Lp6Vp2vs4aBNEgkpdB1E4JbtB8m/Iuig5LtYCav847Ma4M59eFOqV2EXnY 9VJf6ACR96t5H+axL5NNQspoAqhzCzYFLv7Cb9eOLHBTiBcoV0Tf41r9j0RUfHyB+ZGO 7X/EREjWj1fz9Vml+7Xn08DGkmj/EtXh2nQfNRApv2/hust1tb1r8+Fe7wnB7xjW9Za8 8Vuw== X-Gm-Message-State: AOAM533BYQqMm3LSit+b5YFrw4gNtTuSgc4DUrWzYUMwy4I84Nlv29Zm VMNAAygTILCPmtzJdR+70GU= X-Google-Smtp-Source: ABdhPJxUZ/hHcaYhwQDE/vBXcYFvBLzltqA5HHV6iYTJqs9sjP+YhGf7k0wI3gA6W6atPfVv+2/YYw== X-Received: by 2002:a05:600c:3581:: with SMTP id p1mr27163472wmq.34.1635613722764; Sat, 30 Oct 2021 10:08:42 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Yoshinori Sato , Magnus Damm , Paolo Bonzini , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 30/30] hw/timer/sh_timer: Remove use of hw_error Date: Sat, 30 Oct 2021 19:06:15 +0200 Message-Id: <20211030170615.2636436-31-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211030170615.2636436-1-f4bug@amsat.org> References: <20211030170615.2636436-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635613724950100001 From: BALATON Zoltan The hw_error function calls abort and is not meant to be used by devices. Use qemu_log_mask instead to log and ignore invalid accesses. Also fix format strings to allow dropping type casts of hwaddr and use __func__ instead of hard coding function name in the message which were wrong in two cases. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/timer/sh_timer.c | 40 +++++++++++++++++++++++++--------------- 1 file changed, 25 insertions(+), 15 deletions(-) diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 587fa9414aa..c72c327bfaf 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -10,7 +10,7 @@ =20 #include "qemu/osdep.h" #include "exec/memory.h" -#include "hw/hw.h" +#include "qemu/log.h" #include "hw/irq.h" #include "hw/sh4/sh.h" #include "hw/timer/tmu012.h" @@ -75,11 +75,10 @@ static uint32_t sh_timer_read(void *opaque, hwaddr offs= et) if (s->feat & TIMER_FEAT_CAPT) { return s->tcpr; } - /* fall through */ - default: - hw_error("sh_timer_read: Bad offset %x\n", (int)offset); - return 0; } + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + return 0; } =20 static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value) @@ -134,7 +133,8 @@ static void sh_timer_write(void *opaque, hwaddr offset,= uint32_t value) } /* fallthrough */ default: - hw_error("sh_timer_write: Reserved TPSC value\n"); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Reserved TPSC value\n", __func__); } switch ((value & TIMER_TCR_CKEG) >> 3) { case 0: @@ -147,7 +147,8 @@ static void sh_timer_write(void *opaque, hwaddr offset,= uint32_t value) } /* fallthrough */ default: - hw_error("sh_timer_write: Reserved CKEG value\n"); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Reserved CKEG value\n", __func__); } switch ((value & TIMER_TCR_ICPE) >> 6) { case 0: @@ -159,7 +160,8 @@ static void sh_timer_write(void *opaque, hwaddr offset,= uint32_t value) } /* fallthrough */ default: - hw_error("sh_timer_write: Reserved ICPE value\n"); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Reserved ICPE value\n", __func__); } if ((value & TIMER_TCR_UNF) =3D=3D 0) { s->int_level =3D 0; @@ -168,13 +170,15 @@ static void sh_timer_write(void *opaque, hwaddr offse= t, uint32_t value) value &=3D ~TIMER_TCR_UNF; =20 if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) { - hw_error("sh_timer_write: Reserved ICPF value\n"); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Reserved ICPF value\n", __func__); } =20 value &=3D ~TIMER_TCR_ICPF; /* capture not supported */ =20 if (value & TIMER_TCR_RESERVED) { - hw_error("sh_timer_write: Reserved TCR bits set\n"); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Reserved TCR bits set\n", __func__); } s->tcr =3D value; ptimer_set_limit(s->timer, s->tcor, 0); @@ -192,7 +196,8 @@ static void sh_timer_write(void *opaque, hwaddr offset,= uint32_t value) } /* fallthrough */ default: - hw_error("sh_timer_write: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, off= set); } sh_timer_update(s); } @@ -262,7 +267,9 @@ static uint64_t tmu012_read(void *opaque, hwaddr offset= , unsigned size) trace_sh_timer_read(offset); if (offset >=3D 0x20) { if (!(s->feat & TMU012_FEAT_3CHAN)) { - hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad channel offset 0x%" HWADDR_PRIx "\n", + __func__, offset); } return sh_timer_read(s->timer[2], offset - 0x20); } @@ -280,7 +287,8 @@ static uint64_t tmu012_read(void *opaque, hwaddr offset= , unsigned size) return s->tocr; } =20 - hw_error("tmu012_write: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); return 0; } =20 @@ -292,7 +300,9 @@ static void tmu012_write(void *opaque, hwaddr offset, trace_sh_timer_write(offset, value); if (offset >=3D 0x20) { if (!(s->feat & TMU012_FEAT_3CHAN)) { - hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad channel offset 0x%" HWADDR_PRIx "\n", + __func__, offset); } sh_timer_write(s->timer[2], offset - 0x20, value); return; @@ -315,7 +325,7 @@ static void tmu012_write(void *opaque, hwaddr offset, sh_timer_start_stop(s->timer[2], value & (1 << 2)); } else { if (value & (1 << 2)) { - hw_error("tmu012_write: Bad channel\n"); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad channel\n", __func= __); } } =20 --=20 2.31.1