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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id f19sm3645911pfc.72.2021.10.30.06.55.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Oct 2021 06:55:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fHWPFSJTbsCE/6vTsngF6JkT4vnK0upjYRXJ+ujZ4fg=; b=bJwfnVROJPtR8n4Ic1AfKVgR3syyXuBhY1eV7maHnIjBiB5s2KT6A6q541WAogUBEj nwhGtScXptijs+wPVJkPm09Cl3KnncuEpc8xHtsaiyhB3XM5mrXTiqqsEXPtUzu4kCb0 V/6JRS7bGPvPOZlfaeVx0FNe6fXMOLQP1SKyxxFzvbspSdtprgC7EtdyLb7Mvm2qZIb4 MbdAKYHlwQZLSqjcKHxFw0N8SsQtOB+Xz6Uh5707JFV8tuQtXdmXe4rPjLqryQ5BV6Vw 2vUbMjY1+cfvWA6QzNaCZ9WYSEwBgt1SPOz4cD0nD3yRV6ZBvT3M7J3nWfUevKNVvFXF 4WHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fHWPFSJTbsCE/6vTsngF6JkT4vnK0upjYRXJ+ujZ4fg=; b=ILo/5179CFXo+cBGGedWv3G3H7lkcT7ZzyDvmgwFyX3OOWXaAdlaHBiCfyrG/TkUy9 keKrQo/t+xBTIH241CZq5wVC7iXIKQxLfoI6+xsZJP5ZG0hGAZIKzJwrZcrlCzWvZXJF mc7laLWtd4PluBQVjPq98olRNV6g0Nis16EKuatnQROr1gEcJ2MX8dWAwsYnWdLqESl5 +EOkEZ5FfVf61tVhhnZsLP/UoguWTx5vezukU8P62bEd4R2RVDVHeq8hyVXkwKqDcXgd 1J1CU5NOJuiSdm5u2tkyzEqZk7Dz02XSBSr3FlNfxcAn6CIc/xTvfShq3TCIZX0R/sIx lPsA== X-Gm-Message-State: AOAM532jUbvV1RIMpIvckh1RQP0VyVpicz6/jelNfukQZgSXIxFi3F8u umoIwvMqKWhIXzkKm/g0g4Hr7Y0NUv0= X-Google-Smtp-Source: ABdhPJyq09KiOmOgZw7CHIyR7Qr3AJwuBpKcz/DmY0NozFYruvGXTeY0xQaB09CBX6OgPqX0qVwivA== X-Received: by 2002:a17:902:d4d0:b0:141:c13d:6c20 with SMTP id o16-20020a170902d4d000b00141c13d6c20mr4352582plg.44.1635602129201; Sat, 30 Oct 2021 06:55:29 -0700 (PDT) From: Bin Meng X-Google-Original-From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 3/7] target/riscv: debug: Implement debug related TCGCPUOps Date: Sat, 30 Oct 2021 21:55:09 +0800 Message-Id: <20211030135513.18517-4-bin.meng@windriver.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211030135513.18517-1-bin.meng@windriver.com> References: <20211030135513.18517-1-bin.meng@windriver.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635602566851100001 Content-Type: text/plain; charset="utf-8" Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint} TCGCPUOps and hook them into riscv_tcg_ops. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: - use 0 instead of GETPC() target/riscv/debug.h | 4 +++ target/riscv/cpu.c | 3 ++ target/riscv/debug.c | 75 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 82 insertions(+) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index cb8a6e0024..fddc103650 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -107,4 +107,8 @@ void tdata_csr_write(CPURISCVState *env, int tdata_inde= x, target_ulong val); =20 void riscv_trigger_init(CPURISCVState *env); =20 +void riscv_cpu_debug_excp_handler(CPUState *cs); +bool riscv_cpu_debug_check_breakpoint(CPUState *cs); +bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); + #endif /* RISCV_DEBUG_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d53125dbc..7061ae05fb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -701,6 +701,9 @@ static const struct TCGCPUOps riscv_tcg_ops =3D { .do_interrupt =3D riscv_cpu_do_interrupt, .do_transaction_failed =3D riscv_cpu_do_transaction_failed, .do_unaligned_access =3D riscv_cpu_do_unaligned_access, + .debug_excp_handler =3D riscv_cpu_debug_excp_handler, + .debug_check_breakpoint =3D riscv_cpu_debug_check_breakpoint, + .debug_check_watchpoint =3D riscv_cpu_debug_check_watchpoint, #endif /* !CONFIG_USER_ONLY */ }; =20 diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 9bcca27b72..9cb2a6d7ba 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -364,3 +364,78 @@ void riscv_trigger_init(CPURISCVState *env) env->trigger_type2[i].wp =3D NULL; } } + +void riscv_cpu_debug_excp_handler(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { + cs->watchpoint_hit =3D NULL; + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); + } + } else { + if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) { + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); + } + } +} + +bool riscv_cpu_debug_check_breakpoint(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + CPUBreakpoint *bp; + target_ulong ctrl; + target_ulong pc; + int i; + + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + for (i =3D 0; i < TRIGGER_TYPE2_NUM; i++) { + ctrl =3D env->trigger_type2[i].mcontrol; + pc =3D env->trigger_type2[i].maddress; + + if ((ctrl & TYPE2_EXEC) && (bp->pc =3D=3D pc)) { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } + } + } + } + + return false; +} + +bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + target_ulong ctrl; + target_ulong addr; + int flags; + int i; + + for (i =3D 0; i < TRIGGER_TYPE2_NUM; i++) { + ctrl =3D env->trigger_type2[i].mcontrol; + addr =3D env->trigger_type2[i].maddress; + flags =3D 0; + + if (ctrl & TYPE2_LOAD) { + flags |=3D BP_MEM_READ; + } + if (ctrl & TYPE2_STORE) { + flags |=3D BP_MEM_WRITE; + } + + if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } + } + } + + return false; +} --=20 2.25.1