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[147.11.176.192]) by smtp.gmail.com with ESMTPSA id q12sm6645790pfk.65.2021.10.29.08.25.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Oct 2021 08:25:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Gfn97GZHLvDblNfl91JEwYWh/I9EfUhpNVYLyXEU1Gc=; b=G7oMa2RFr83nRdrZ9YA9ehh1Du2Wn3vOpufQLQvPQq9YDXYk2SDW4V3GpGnFrQZLVA D93J0eges9iwOFjvIr1aKXPf/w0GgjbKkg6OxScsq+chYemmD3mIkfCbRn2ijm+rHrtx Se0t4U5QGqS4DVDGv84Exy2yNnYfk0CO6WL7W1FmdT5O8q4Nez05+S6u0ux+ZtMSTCWs jOZKPc5yUrMMANyRgmS95f96V5GfFEnTGf9n9iyPXal1Omne5PempXt+EVf0yIqbSBib 24sZmyNwnyK4nNlYTOiJtM0GuyBJsITisHnSfXeH7KZQ36vhJmxedo/1GGeMvGQS0GH7 3fpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Gfn97GZHLvDblNfl91JEwYWh/I9EfUhpNVYLyXEU1Gc=; b=uDl6mz6RTIiuwOz8qijqmNRctkLmGuFLHoIrp8c72QCaC64cCdkhUiTPXlLa2mYg4k u3CZwOHYtoZ5b6THoTb2POpm0fEzrIfQYWH3MfoXiJfL6sQbZbrqg9hkmf0mfe9ig5Lx +70Dhwk8NY+Wl7iwqS76yWITRBXsiKEHeoe3ter05wwZaZa48n6+oHBfeZhB8zrUNtXH X20/PE1YwuPDFdYd3WK6zkVdnCwvoAwSJjp+mWHO0JBKVH/BXbNTUtQyPunKJ9finvOu i3B8xZAf+9nP9DHM7tEhW9Uu/JAgHhRIcQzm41+D6oDxfDw46RDXxFrLwiLAxgZKKnMa X56Q== X-Gm-Message-State: AOAM531g2phCiGvQgjzrCh3zXCqubDsSPX/zwncOq8ipOBg3zlHMLUEf V1zC8weZN4FW/Gd+tAsJcew3ygIPSRU= X-Google-Smtp-Source: ABdhPJx35L0vYRjry+5OdehnwX7PeOqEFntYY1nTSK1I4GNEosbic4diDcxmKi6udkuTKLAAfxDzXQ== X-Received: by 2002:a17:90b:390b:: with SMTP id ob11mr12123610pjb.217.1635521148863; Fri, 29 Oct 2021 08:25:48 -0700 (PDT) From: Bin Meng X-Google-Original-From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 2/5] target/riscv: debug: Implement debug related TCGCPUOps Date: Fri, 29 Oct 2021 23:25:32 +0800 Message-Id: <20211029152535.2055096-3-bin.meng@windriver.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029152535.2055096-1-bin.meng@windriver.com> References: <20211029152535.2055096-1-bin.meng@windriver.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635521275347000001 Content-Type: text/plain; charset="utf-8" Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint} TCGCPUOps and hook them into riscv_tcg_ops. Signed-off-by: Bin Meng --- target/riscv/debug.h | 4 +++ target/riscv/cpu.c | 3 ++ target/riscv/debug.c | 75 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 82 insertions(+) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index cb8a6e0024..fddc103650 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -107,4 +107,8 @@ void tdata_csr_write(CPURISCVState *env, int tdata_inde= x, target_ulong val); =20 void riscv_trigger_init(CPURISCVState *env); =20 +void riscv_cpu_debug_excp_handler(CPUState *cs); +bool riscv_cpu_debug_check_breakpoint(CPUState *cs); +bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); + #endif /* RISCV_DEBUG_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 788fa0b11c..eface73e7d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -688,6 +688,9 @@ static const struct TCGCPUOps riscv_tcg_ops =3D { .do_interrupt =3D riscv_cpu_do_interrupt, .do_transaction_failed =3D riscv_cpu_do_transaction_failed, .do_unaligned_access =3D riscv_cpu_do_unaligned_access, + .debug_excp_handler =3D riscv_cpu_debug_excp_handler, + .debug_check_breakpoint =3D riscv_cpu_debug_check_breakpoint, + .debug_check_watchpoint =3D riscv_cpu_debug_check_watchpoint, #endif /* !CONFIG_USER_ONLY */ }; =20 diff --git a/target/riscv/debug.c b/target/riscv/debug.c index ffb87fd3e8..ed09a255d3 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -362,3 +362,78 @@ void riscv_trigger_init(CPURISCVState *env) env->trigger_type2[i].wp =3D NULL; } } + +void riscv_cpu_debug_excp_handler(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { + cs->watchpoint_hit =3D NULL; + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, GETPC()); + } + } else { + if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) { + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, GETPC()); + } + } +} + +bool riscv_cpu_debug_check_breakpoint(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + CPUBreakpoint *bp; + target_ulong ctrl; + target_ulong pc; + int i; + + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + for (i =3D 0; i < TRIGGER_TYPE2_NUM; i++) { + ctrl =3D env->trigger_type2[i].mcontrol; + pc =3D env->trigger_type2[i].maddress; + + if ((ctrl & TYPE2_EXEC) && (bp->pc =3D=3D pc)) { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } + } + } + } + + return false; +} + +bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + target_ulong ctrl; + target_ulong addr; + int flags; + int i; + + for (i =3D 0; i < TRIGGER_TYPE2_NUM; i++) { + ctrl =3D env->trigger_type2[i].mcontrol; + addr =3D env->trigger_type2[i].maddress; + flags =3D 0; + + if (ctrl & TYPE2_LOAD) { + flags |=3D BP_MEM_READ; + } + if (ctrl & TYPE2_STORE) { + flags |=3D BP_MEM_WRITE; + } + + if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } + } + } + + return false; +} --=20 2.25.1