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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Frank Chang , Bin Meng , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635501435763100001 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- target/riscv/vector_helper.c | 4 ---- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 804f423d5bb..5c0c3d25478 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2652,7 +2652,8 @@ GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check) #define GEN_MM_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_r *a) \ { \ - if (vext_check_isa_ill(s)) { \ + if (require_rvv(s) && \ + vext_check_isa_ill(s)) { \ uint32_t data =3D 0; \ gen_helper_gvec_4_ptr *fn =3D gen_helper_##NAME; \ TCGLabel *over =3D gen_new_label(); \ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 71d7b1e8796..f883fdf4749 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4231,7 +4231,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; \ uint32_t vl =3D env->vl; \ uint32_t i; \ int a, b; \ @@ -4241,9 +4240,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ b =3D vext_elem_mask(vs2, i); \ vext_set_elem_mask(vd, i, OP(b, a)); \ } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, i, 0); \ - } \ } =20 #define DO_NAND(N, M) (!(N & M)) --=20 2.25.1