From nobody Thu Dec 18 17:55:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1635482103; cv=none; d=zohomail.com; s=zohoarc; b=HiU5ClO2y0TK4PZbF4zK8/6SPzgpN6orbewYwnZkvvg7PYLJXaGhOGfwQQNekuzQ8B8x/50yOYWr7UJ4QTdKPvmsV6vU6XDpeaL2F0tv2rRpcjOYwb4jrtp2c0I9fqPgCP/eMg0HR5JOy3+UGk7uu6bTCD11O0tyqBK0lX8bSbg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635482103; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yA37LSgyZgUZ7Jnk9oYQugiaR4/N0x8exHl3zm53CZM=; b=U2yAHSqmR8DNB3TH6Lve1S7n4YF60QxmB3dfhutu0/q+02XNyijw/9GIwli/8VeocMr19E9phcwSITDFudKoXa6ROvUi5NSh+wQnOJuTXvzUFjy7WbOIk+MHOfecLzqdvxKN4MGXBNxBnMRThD9W0mQN178WSIrqgtKCJ5qL5uM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635482103216128.38896937160212; Thu, 28 Oct 2021 21:35:03 -0700 (PDT) Received: from localhost ([::1]:46046 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgJba-0006SV-0B for importer@patchew.org; Fri, 29 Oct 2021 00:35:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51016) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgJaE-0003ZM-AU for qemu-devel@nongnu.org; Fri, 29 Oct 2021 00:33:38 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:42898) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgJaB-0007sq-Ky for qemu-devel@nongnu.org; Fri, 29 Oct 2021 00:33:37 -0400 Received: by mail-pl1-x632.google.com with SMTP id v16so5983343ple.9 for ; Thu, 28 Oct 2021 21:33:35 -0700 (PDT) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id i11sm4120257pgp.18.2021.10.28.21.33.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 21:33:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yA37LSgyZgUZ7Jnk9oYQugiaR4/N0x8exHl3zm53CZM=; b=Ta131xuLNE+cUeWaciQvs6geeDOl3BoVnuAFj10oHfns9M3oLPAtnEY8ktmUk5gLts uZq2cUxo44Tjscr6+X4YJtA9WB+Blf2crTi2PYjltoZwIIfSlB70fMRUdZtCkbfRLUP3 jfg9UPlYMO/FBKaOUzFPf7E5W4dFEJN9iRwJTxVxy0lRe33XIsNQPfYPIn4f/+usy6kr niaiSbtkqOmRr/udcHfhJnsQGQe13tuGXtWb0K6iGg9fFUNn18uLfSWcr/R/MX5NIj4q Dl4FoeaNeFTGYZqL1Q9y0udZtoJbb76fSMFNyRCd2rEDvZa36oF3FDYGKU4fvepT6nL5 GUEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yA37LSgyZgUZ7Jnk9oYQugiaR4/N0x8exHl3zm53CZM=; b=sZJJR6MPHopaqwlNJostkMG+UUQQTIXoZRueOleH7USGJO9ecBklsq9CZzegGegjV1 07kib9rmo2hyxezi3iWj+bH5uo1rOw4tRYpCmlSw5suKOCSNo727648ziiyy37nd8dko L6QXOiYYqPfFyDRauWiqkmr0njpVOHjswhqKTRHQ2sXztPc/rn0ZN3w1yd5M2f9TQ3qx FqKhcnl5hNy4Y5Q4qxsZ8n6qMn6UJ0QVjU+x33Boa3ywvhflIpCmY/v04xUgeXgaHesw obqbKdQcQnK6WyyOyT86sxbRhPxn37oVezxuD+V6L+DTRlF3nXMyyaTq4Xp6b4Ygf2JT HkTw== X-Gm-Message-State: AOAM532W7RStzliEux7JoyyM9/CuGipqTXFg3PPCMmDj+qN2CbZnO8/u K/q62zcvNLj5Gax5dysAQzOu+QcVfMWcXg== X-Google-Smtp-Source: ABdhPJySi7xCPyhi/8kfO9cCtkJeCK5zsaY/XE//SOn3CNzUqMTvx5HK7uSRS1L/fhzIHs8jTgiawA== X-Received: by 2002:a17:90b:4d0b:: with SMTP id mw11mr9001559pjb.135.1635482014210; Thu, 28 Oct 2021 21:33:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL v2 04/60] host-utils: add 128-bit quotient support to divu128/divs128 Date: Thu, 28 Oct 2021 21:32:33 -0700 Message-Id: <20211029043329.1518029-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029043329.1518029-1-richard.henderson@linaro.org> References: <20211029043329.1518029-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luis Pires Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1635482104988100007 Content-Type: text/plain; charset="utf-8" From: Luis Pires These will be used to implement new decimal floating point instructions from Power ISA 3.1. The remainder is now returned directly by divu128/divs128, freeing up phigh to receive the high 64 bits of the quotient. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson Message-Id: <20211025191154.350831-4-luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson --- include/hw/clock.h | 6 +- include/qemu/host-utils.h | 20 ++++-- target/ppc/int_helper.c | 9 +-- util/host-utils.c | 133 +++++++++++++++++++++++++------------- 4 files changed, 108 insertions(+), 60 deletions(-) diff --git a/include/hw/clock.h b/include/hw/clock.h index 7443e6c4ab..5c927cee7f 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -323,11 +323,7 @@ static inline uint64_t clock_ns_to_ticks(const Clock *= clk, uint64_t ns) if (clk->period =3D=3D 0) { return 0; } - /* - * BUG: when CONFIG_INT128 is not defined, the current implementation = of - * divu128 does not return a valid truncated quotient, so the result w= ill - * be wrong. - */ + divu128(&lo, &hi, clk->period); return lo; } diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index 08a17e16e5..a3a7ced78d 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host-utils.h @@ -56,26 +56,32 @@ static inline uint64_t muldiv64(uint64_t a, uint32_t b,= uint32_t c) return (__int128_t)a * b / c; } =20 -static inline void divu128(uint64_t *plow, uint64_t *phigh, uint64_t divis= or) +static inline uint64_t divu128(uint64_t *plow, uint64_t *phigh, + uint64_t divisor) { __uint128_t dividend =3D ((__uint128_t)*phigh << 64) | *plow; __uint128_t result =3D dividend / divisor; + *plow =3D result; - *phigh =3D dividend % divisor; + *phigh =3D result >> 64; + return dividend % divisor; } =20 -static inline void divs128(int64_t *plow, int64_t *phigh, int64_t divisor) +static inline int64_t divs128(uint64_t *plow, int64_t *phigh, + int64_t divisor) { - __int128_t dividend =3D ((__int128_t)*phigh << 64) | (uint64_t)*plow; + __int128_t dividend =3D ((__int128_t)*phigh << 64) | *plow; __int128_t result =3D dividend / divisor; + *plow =3D result; - *phigh =3D dividend % divisor; + *phigh =3D result >> 64; + return dividend % divisor; } #else void muls64(uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b); void mulu64(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b); -void divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor); -void divs128(int64_t *plow, int64_t *phigh, int64_t divisor); +uint64_t divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor); +int64_t divs128(uint64_t *plow, int64_t *phigh, int64_t divisor); =20 static inline uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c) { diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 510faf24cf..eeb7781a9e 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -120,7 +120,7 @@ uint64_t helper_divdeu(CPUPPCState *env, uint64_t ra, u= int64_t rb, uint32_t oe) =20 uint64_t helper_divde(CPUPPCState *env, uint64_t rau, uint64_t rbu, uint32= _t oe) { - int64_t rt =3D 0; + uint64_t rt =3D 0; int64_t ra =3D (int64_t)rau; int64_t rb =3D (int64_t)rbu; int overflow =3D 0; @@ -2506,6 +2506,7 @@ uint32_t helper_bcdcfsq(ppc_avr_t *r, ppc_avr_t *b, u= int32_t ps) int cr; uint64_t lo_value; uint64_t hi_value; + uint64_t rem; ppc_avr_t ret =3D { .u64 =3D { 0, 0 } }; =20 if (b->VsrSD(0) < 0) { @@ -2541,10 +2542,10 @@ uint32_t helper_bcdcfsq(ppc_avr_t *r, ppc_avr_t *b,= uint32_t ps) * In that case, we leave r unchanged. */ } else { - divu128(&lo_value, &hi_value, 1000000000000000ULL); + rem =3D divu128(&lo_value, &hi_value, 1000000000000000ULL); =20 - for (i =3D 1; i < 16; hi_value /=3D 10, i++) { - bcd_put_digit(&ret, hi_value % 10, i); + for (i =3D 1; i < 16; rem /=3D 10, i++) { + bcd_put_digit(&ret, rem % 10, i); } =20 for (; i < 32; lo_value /=3D 10, i++) { diff --git a/util/host-utils.c b/util/host-utils.c index 701a371843..bcc772b8ec 100644 --- a/util/host-utils.c +++ b/util/host-utils.c @@ -87,72 +87,117 @@ void muls64 (uint64_t *plow, uint64_t *phigh, int64_t = a, int64_t b) } =20 /* - * Unsigned 128-by-64 division. Returns quotient via plow and - * remainder via phigh. - * The result must fit in 64 bits (plow) - otherwise, the result - * is undefined. - * This function will cause a division by zero if passed a zero divisor. + * Unsigned 128-by-64 division. + * Returns the remainder. + * Returns quotient via plow and phigh. + * Also returns the remainder via the function return value. */ -void divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor) +uint64_t divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor) { uint64_t dhi =3D *phigh; uint64_t dlo =3D *plow; - unsigned i; - uint64_t carry =3D 0; + uint64_t rem, dhighest; + int sh; =20 if (divisor =3D=3D 0 || dhi =3D=3D 0) { *plow =3D dlo / divisor; - *phigh =3D dlo % divisor; + *phigh =3D 0; + return dlo % divisor; } else { + sh =3D clz64(divisor); =20 - for (i =3D 0; i < 64; i++) { - carry =3D dhi >> 63; - dhi =3D (dhi << 1) | (dlo >> 63); - if (carry || (dhi >=3D divisor)) { - dhi -=3D divisor; - carry =3D 1; - } else { - carry =3D 0; + if (dhi < divisor) { + if (sh !=3D 0) { + /* normalize the divisor, shifting the dividend accordingl= y */ + divisor <<=3D sh; + dhi =3D (dhi << sh) | (dlo >> (64 - sh)); + dlo <<=3D sh; } - dlo =3D (dlo << 1) | carry; + + *phigh =3D 0; + *plow =3D udiv_qrnnd(&rem, dhi, dlo, divisor); + } else { + if (sh !=3D 0) { + /* normalize the divisor, shifting the dividend accordingl= y */ + divisor <<=3D sh; + dhighest =3D dhi >> (64 - sh); + dhi =3D (dhi << sh) | (dlo >> (64 - sh)); + dlo <<=3D sh; + + *phigh =3D udiv_qrnnd(&dhi, dhighest, dhi, divisor); + } else { + /** + * dhi >=3D divisor + * Since the MSB of divisor is set (sh =3D=3D 0), + * (dhi - divisor) < divisor + * + * Thus, the high part of the quotient is 1, and we can + * calculate the low part with a single call to udiv_qrnnd + * after subtracting divisor from dhi + */ + dhi -=3D divisor; + *phigh =3D 1; + } + + *plow =3D udiv_qrnnd(&rem, dhi, dlo, divisor); } =20 - *plow =3D dlo; - *phigh =3D dhi; + /* + * since the dividend/divisor might have been normalized, + * the remainder might also have to be shifted back + */ + return rem >> sh; } } =20 /* - * Signed 128-by-64 division. Returns quotient via plow and - * remainder via phigh. - * The result must fit in 64 bits (plow) - otherwise, the result - * is undefined. - * This function will cause a division by zero if passed a zero divisor. + * Signed 128-by-64 division. + * Returns quotient via plow and phigh. + * Also returns the remainder via the function return value. */ -void divs128(int64_t *plow, int64_t *phigh, int64_t divisor) +int64_t divs128(uint64_t *plow, int64_t *phigh, int64_t divisor) { - int sgn_dvdnd =3D *phigh < 0; - int sgn_divsr =3D divisor < 0; + bool neg_quotient =3D false, neg_remainder =3D false; + uint64_t unsig_hi =3D *phigh, unsig_lo =3D *plow; + uint64_t rem; =20 - if (sgn_dvdnd) { - *plow =3D ~(*plow); - *phigh =3D ~(*phigh); - if (*plow =3D=3D (int64_t)-1) { + if (*phigh < 0) { + neg_quotient =3D !neg_quotient; + neg_remainder =3D !neg_remainder; + + if (unsig_lo =3D=3D 0) { + unsig_hi =3D -unsig_hi; + } else { + unsig_hi =3D ~unsig_hi; + unsig_lo =3D -unsig_lo; + } + } + + if (divisor < 0) { + neg_quotient =3D !neg_quotient; + + divisor =3D -divisor; + } + + rem =3D divu128(&unsig_lo, &unsig_hi, (uint64_t)divisor); + + if (neg_quotient) { + if (unsig_lo =3D=3D 0) { + *phigh =3D -unsig_hi; *plow =3D 0; - (*phigh)++; - } else { - (*plow)++; - } + } else { + *phigh =3D ~unsig_hi; + *plow =3D -unsig_lo; + } + } else { + *phigh =3D unsig_hi; + *plow =3D unsig_lo; } =20 - if (sgn_divsr) { - divisor =3D 0 - divisor; - } - - divu128((uint64_t *)plow, (uint64_t *)phigh, (uint64_t)divisor); - - if (sgn_dvdnd ^ sgn_divsr) { - *plow =3D 0 - *plow; + if (neg_remainder) { + return -rem; + } else { + return rem; } } #endif --=20 2.25.1