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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1635396267; x=1637988268; bh=Jp9UVWaLwVNIzQpBAw cwf23Ysj/NKdZvzmtw/yFvBeM=; b=Y5DQKH4pfgvqzg+5rCD8i41pJFt+1CTTB/ Id9lIjSgCb1VJOxfQc73vb/lv1zf27VRMbhYr+AMJjFktQMC6SMowa0Rlb9upGvQ Ixr81PGatr+fhMdQc14XtCA8ZTJKHL52FKlUlxmqgfOCfCGyLlj35n3yV33xSUBU xcR3oyQglLC9qP/oUrDDEavT/0zPtAwaaMtHFB/x50DATdq2Vr7UA6bRwuUqYh2P AAKjCkSYmJKdnzS+cm0LJH6K48dKe3a4ncsyXBONTKq5f/2k0i6P/y3Uw6n53p0k upUhx9Prree5DnRk5Pvj+QZ85pnR9RlpAxAgdjQBgenkyYY66b+g== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alexey Baturo , Alexey Baturo , Richard Henderson , Alistair Francis , Bin Meng Subject: [PULL 07/18] target/riscv: Add J-extension into RISC-V Date: Thu, 28 Oct 2021 14:43:31 +1000 Message-Id: <20211028044342.3070385-8-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028044342.3070385-1-alistair.francis@opensource.wdc.com> References: <20211028044342.3070385-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=928ee31ee=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1635397036132100001 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 20211025173609.2724490-2-space.monkey.delivers@gmail.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a33dc30be8..1cfc6a53a0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -65,6 +65,7 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') +#define RVJ RV('J') =20 /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there @@ -291,6 +292,7 @@ struct RISCVCPU { bool ext_s; bool ext_u; bool ext_h; + bool ext_j; bool ext_v; bool ext_zba; bool ext_zbb; --=20 2.31.1