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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 06/56] tcg/optimize: Rename "mask" to "z_mask"
Date: Wed, 27 Oct 2021 19:40:41 -0700
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Cc: Luis Pires <luis.pires@eldorado.org.br>,
=?UTF-8?q?Alex=20Benn=C3=A9e?= <alex.bennee@linaro.org>,
=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <f4bug@amsat.org>
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X-ZM-MESSAGEID: 1635390078701100001
Prepare for tracking different masks by renaming this one.
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 142 +++++++++++++++++++++++++------------------------
1 file changed, 72 insertions(+), 70 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index c239c3bd07..148e360fc6 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -41,7 +41,7 @@ typedef struct TempOptInfo {
TCGTemp *prev_copy;
TCGTemp *next_copy;
uint64_t val;
- uint64_t mask;
+ uint64_t z_mask; /* mask bit is 0 if and only if value bit is 0 */
} TempOptInfo;
=20
static inline TempOptInfo *ts_info(TCGTemp *ts)
@@ -81,7 +81,7 @@ static void reset_ts(TCGTemp *ts)
ti->next_copy =3D ts;
ti->prev_copy =3D ts;
ti->is_const =3D false;
- ti->mask =3D -1;
+ ti->z_mask =3D -1;
}
=20
static void reset_temp(TCGArg arg)
@@ -111,14 +111,14 @@ static void init_ts_info(TCGTempSet *temps_used, TCGT=
emp *ts)
if (ts->kind =3D=3D TEMP_CONST) {
ti->is_const =3D true;
ti->val =3D ts->val;
- ti->mask =3D ts->val;
+ ti->z_mask =3D ts->val;
if (TCG_TARGET_REG_BITS > 32 && ts->type =3D=3D TCG_TYPE_I32) {
/* High bits of a 32-bit quantity are garbage. */
- ti->mask |=3D ~0xffffffffull;
+ ti->z_mask |=3D ~0xffffffffull;
}
} else {
ti->is_const =3D false;
- ti->mask =3D -1;
+ ti->z_mask =3D -1;
}
}
=20
@@ -186,7 +186,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, T=
CGArg dst, TCGArg src)
const TCGOpDef *def;
TempOptInfo *di;
TempOptInfo *si;
- uint64_t mask;
+ uint64_t z_mask;
TCGOpcode new_op;
=20
if (ts_are_copies(dst_ts, src_ts)) {
@@ -210,12 +210,12 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op,=
TCGArg dst, TCGArg src)
op->args[0] =3D dst;
op->args[1] =3D src;
=20
- mask =3D si->mask;
+ z_mask =3D si->z_mask;
if (TCG_TARGET_REG_BITS > 32 && new_op =3D=3D INDEX_op_mov_i32) {
/* High bits of the destination are now garbage. */
- mask |=3D ~0xffffffffull;
+ z_mask |=3D ~0xffffffffull;
}
- di->mask =3D mask;
+ di->z_mask =3D z_mask;
=20
if (src_ts->type =3D=3D dst_ts->type) {
TempOptInfo *ni =3D ts_info(si->next_copy);
@@ -621,7 +621,7 @@ void tcg_optimize(TCGContext *s)
}
=20
QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
- uint64_t mask, partmask, affected, tmp;
+ uint64_t z_mask, partmask, affected, tmp;
int nb_oargs, nb_iargs;
TCGOpcode opc =3D op->opc;
const TCGOpDef *def =3D &tcg_op_defs[opc];
@@ -855,170 +855,172 @@ void tcg_optimize(TCGContext *s)
=20
/* Simplify using known-zero bits. Currently only ops with a single
output argument is supported. */
- mask =3D -1;
+ z_mask =3D -1;
affected =3D -1;
switch (opc) {
CASE_OP_32_64(ext8s):
- if ((arg_info(op->args[1])->mask & 0x80) !=3D 0) {
+ if ((arg_info(op->args[1])->z_mask & 0x80) !=3D 0) {
break;
}
QEMU_FALLTHROUGH;
CASE_OP_32_64(ext8u):
- mask =3D 0xff;
+ z_mask =3D 0xff;
goto and_const;
CASE_OP_32_64(ext16s):
- if ((arg_info(op->args[1])->mask & 0x8000) !=3D 0) {
+ if ((arg_info(op->args[1])->z_mask & 0x8000) !=3D 0) {
break;
}
QEMU_FALLTHROUGH;
CASE_OP_32_64(ext16u):
- mask =3D 0xffff;
+ z_mask =3D 0xffff;
goto and_const;
case INDEX_op_ext32s_i64:
- if ((arg_info(op->args[1])->mask & 0x80000000) !=3D 0) {
+ if ((arg_info(op->args[1])->z_mask & 0x80000000) !=3D 0) {
break;
}
QEMU_FALLTHROUGH;
case INDEX_op_ext32u_i64:
- mask =3D 0xffffffffU;
+ z_mask =3D 0xffffffffU;
goto and_const;
=20
CASE_OP_32_64(and):
- mask =3D arg_info(op->args[2])->mask;
+ z_mask =3D arg_info(op->args[2])->z_mask;
if (arg_is_const(op->args[2])) {
and_const:
- affected =3D arg_info(op->args[1])->mask & ~mask;
+ affected =3D arg_info(op->args[1])->z_mask & ~z_mask;
}
- mask =3D arg_info(op->args[1])->mask & mask;
+ z_mask =3D arg_info(op->args[1])->z_mask & z_mask;
break;
=20
case INDEX_op_ext_i32_i64:
- if ((arg_info(op->args[1])->mask & 0x80000000) !=3D 0) {
+ if ((arg_info(op->args[1])->z_mask & 0x80000000) !=3D 0) {
break;
}
QEMU_FALLTHROUGH;
case INDEX_op_extu_i32_i64:
/* We do not compute affected as it is a size changing op. */
- mask =3D (uint32_t)arg_info(op->args[1])->mask;
+ z_mask =3D (uint32_t)arg_info(op->args[1])->z_mask;
break;
=20
CASE_OP_32_64(andc):
/* Known-zeros does not imply known-ones. Therefore unless
op->args[2] is constant, we can't infer anything from it. =
*/
if (arg_is_const(op->args[2])) {
- mask =3D ~arg_info(op->args[2])->mask;
+ z_mask =3D ~arg_info(op->args[2])->z_mask;
goto and_const;
}
/* But we certainly know nothing outside args[1] may be set. */
- mask =3D arg_info(op->args[1])->mask;
+ z_mask =3D arg_info(op->args[1])->z_mask;
break;
=20
case INDEX_op_sar_i32:
if (arg_is_const(op->args[2])) {
tmp =3D arg_info(op->args[2])->val & 31;
- mask =3D (int32_t)arg_info(op->args[1])->mask >> tmp;
+ z_mask =3D (int32_t)arg_info(op->args[1])->z_mask >> tmp;
}
break;
case INDEX_op_sar_i64:
if (arg_is_const(op->args[2])) {
tmp =3D arg_info(op->args[2])->val & 63;
- mask =3D (int64_t)arg_info(op->args[1])->mask >> tmp;
+ z_mask =3D (int64_t)arg_info(op->args[1])->z_mask >> tmp;
}
break;
=20
case INDEX_op_shr_i32:
if (arg_is_const(op->args[2])) {
tmp =3D arg_info(op->args[2])->val & 31;
- mask =3D (uint32_t)arg_info(op->args[1])->mask >> tmp;
+ z_mask =3D (uint32_t)arg_info(op->args[1])->z_mask >> tmp;
}
break;
case INDEX_op_shr_i64:
if (arg_is_const(op->args[2])) {
tmp =3D arg_info(op->args[2])->val & 63;
- mask =3D (uint64_t)arg_info(op->args[1])->mask >> tmp;
+ z_mask =3D (uint64_t)arg_info(op->args[1])->z_mask >> tmp;
}
break;
=20
case INDEX_op_extrl_i64_i32:
- mask =3D (uint32_t)arg_info(op->args[1])->mask;
+ z_mask =3D (uint32_t)arg_info(op->args[1])->z_mask;
break;
case INDEX_op_extrh_i64_i32:
- mask =3D (uint64_t)arg_info(op->args[1])->mask >> 32;
+ z_mask =3D (uint64_t)arg_info(op->args[1])->z_mask >> 32;
break;
=20
CASE_OP_32_64(shl):
if (arg_is_const(op->args[2])) {
tmp =3D arg_info(op->args[2])->val & (TCG_TARGET_REG_BITS =
- 1);
- mask =3D arg_info(op->args[1])->mask << tmp;
+ z_mask =3D arg_info(op->args[1])->z_mask << tmp;
}
break;
=20
CASE_OP_32_64(neg):
/* Set to 1 all bits to the left of the rightmost. */
- mask =3D -(arg_info(op->args[1])->mask
- & -arg_info(op->args[1])->mask);
+ z_mask =3D -(arg_info(op->args[1])->z_mask
+ & -arg_info(op->args[1])->z_mask);
break;
=20
CASE_OP_32_64(deposit):
- mask =3D deposit64(arg_info(op->args[1])->mask,
- op->args[3], op->args[4],
- arg_info(op->args[2])->mask);
+ z_mask =3D deposit64(arg_info(op->args[1])->z_mask,
+ op->args[3], op->args[4],
+ arg_info(op->args[2])->z_mask);
break;
=20
CASE_OP_32_64(extract):
- mask =3D extract64(arg_info(op->args[1])->mask,
- op->args[2], op->args[3]);
+ z_mask =3D extract64(arg_info(op->args[1])->z_mask,
+ op->args[2], op->args[3]);
if (op->args[2] =3D=3D 0) {
- affected =3D arg_info(op->args[1])->mask & ~mask;
+ affected =3D arg_info(op->args[1])->z_mask & ~z_mask;
}
break;
CASE_OP_32_64(sextract):
- mask =3D sextract64(arg_info(op->args[1])->mask,
- op->args[2], op->args[3]);
- if (op->args[2] =3D=3D 0 && (tcg_target_long)mask >=3D 0) {
- affected =3D arg_info(op->args[1])->mask & ~mask;
+ z_mask =3D sextract64(arg_info(op->args[1])->z_mask,
+ op->args[2], op->args[3]);
+ if (op->args[2] =3D=3D 0 && (tcg_target_long)z_mask >=3D 0) {
+ affected =3D arg_info(op->args[1])->z_mask & ~z_mask;
}
break;
=20
CASE_OP_32_64(or):
CASE_OP_32_64(xor):
- mask =3D arg_info(op->args[1])->mask | arg_info(op->args[2])->=
mask;
+ z_mask =3D arg_info(op->args[1])->z_mask
+ | arg_info(op->args[2])->z_mask;
break;
=20
case INDEX_op_clz_i32:
case INDEX_op_ctz_i32:
- mask =3D arg_info(op->args[2])->mask | 31;
+ z_mask =3D arg_info(op->args[2])->z_mask | 31;
break;
=20
case INDEX_op_clz_i64:
case INDEX_op_ctz_i64:
- mask =3D arg_info(op->args[2])->mask | 63;
+ z_mask =3D arg_info(op->args[2])->z_mask | 63;
break;
=20
case INDEX_op_ctpop_i32:
- mask =3D 32 | 31;
+ z_mask =3D 32 | 31;
break;
case INDEX_op_ctpop_i64:
- mask =3D 64 | 63;
+ z_mask =3D 64 | 63;
break;
=20
CASE_OP_32_64(setcond):
case INDEX_op_setcond2_i32:
- mask =3D 1;
+ z_mask =3D 1;
break;
=20
CASE_OP_32_64(movcond):
- mask =3D arg_info(op->args[3])->mask | arg_info(op->args[4])->=
mask;
+ z_mask =3D arg_info(op->args[3])->z_mask
+ | arg_info(op->args[4])->z_mask;
break;
=20
CASE_OP_32_64(ld8u):
- mask =3D 0xff;
+ z_mask =3D 0xff;
break;
CASE_OP_32_64(ld16u):
- mask =3D 0xffff;
+ z_mask =3D 0xffff;
break;
case INDEX_op_ld32u_i64:
- mask =3D 0xffffffffu;
+ z_mask =3D 0xffffffffu;
break;
=20
CASE_OP_32_64(qemu_ld):
@@ -1026,43 +1028,43 @@ void tcg_optimize(TCGContext *s)
MemOpIdx oi =3D op->args[nb_oargs + nb_iargs];
MemOp mop =3D get_memop(oi);
if (!(mop & MO_SIGN)) {
- mask =3D (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
+ z_mask =3D (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
}
}
break;
=20
CASE_OP_32_64(bswap16):
- mask =3D arg_info(op->args[1])->mask;
- if (mask <=3D 0xffff) {
+ z_mask =3D arg_info(op->args[1])->z_mask;
+ if (z_mask <=3D 0xffff) {
op->args[2] |=3D TCG_BSWAP_IZ;
}
- mask =3D bswap16(mask);
+ z_mask =3D bswap16(z_mask);
switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) {
case TCG_BSWAP_OZ:
break;
case TCG_BSWAP_OS:
- mask =3D (int16_t)mask;
+ z_mask =3D (int16_t)z_mask;
break;
default: /* undefined high bits */
- mask |=3D MAKE_64BIT_MASK(16, 48);
+ z_mask |=3D MAKE_64BIT_MASK(16, 48);
break;
}
break;
=20
case INDEX_op_bswap32_i64:
- mask =3D arg_info(op->args[1])->mask;
- if (mask <=3D 0xffffffffu) {
+ z_mask =3D arg_info(op->args[1])->z_mask;
+ if (z_mask <=3D 0xffffffffu) {
op->args[2] |=3D TCG_BSWAP_IZ;
}
- mask =3D bswap32(mask);
+ z_mask =3D bswap32(z_mask);
switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) {
case TCG_BSWAP_OZ:
break;
case TCG_BSWAP_OS:
- mask =3D (int32_t)mask;
+ z_mask =3D (int32_t)z_mask;
break;
default: /* undefined high bits */
- mask |=3D MAKE_64BIT_MASK(32, 32);
+ z_mask |=3D MAKE_64BIT_MASK(32, 32);
break;
}
break;
@@ -1074,9 +1076,9 @@ void tcg_optimize(TCGContext *s)
/* 32-bit ops generate 32-bit results. For the result is zero test
below, we can ignore high bits, but for further optimizations we
need to record that the high bits contain garbage. */
- partmask =3D mask;
+ partmask =3D z_mask;
if (!(def->flags & TCG_OPF_64BIT)) {
- mask |=3D ~(tcg_target_ulong)0xffffffffu;
+ z_mask |=3D ~(tcg_target_ulong)0xffffffffu;
partmask &=3D 0xffffffffu;
affected &=3D 0xffffffffu;
}
@@ -1472,7 +1474,7 @@ void tcg_optimize(TCGContext *s)
vs the high word of the input. */
do_setcond_high:
reset_temp(op->args[0]);
- arg_info(op->args[0])->mask =3D 1;
+ arg_info(op->args[0])->z_mask =3D 1;
op->opc =3D INDEX_op_setcond_i32;
op->args[1] =3D op->args[2];
op->args[2] =3D op->args[4];
@@ -1498,7 +1500,7 @@ void tcg_optimize(TCGContext *s)
}
do_setcond_low:
reset_temp(op->args[0]);
- arg_info(op->args[0])->mask =3D 1;
+ arg_info(op->args[0])->z_mask =3D 1;
op->opc =3D INDEX_op_setcond_i32;
op->args[2] =3D op->args[3];
op->args[3] =3D op->args[5];
@@ -1543,7 +1545,7 @@ void tcg_optimize(TCGContext *s)
/* Default case: we know nothing about operation (or were unab=
le
to compute the operation result) so no propagation is done.
We trash everything if the operation is the end of a basic
- block, otherwise we only trash the output args. "mask" is
+ block, otherwise we only trash the output args. "z_mask" is
the non-zero bits mask for the first output arg. */
if (def->flags & TCG_OPF_BB_END) {
memset(&temps_used, 0, sizeof(temps_used));
@@ -1554,7 +1556,7 @@ void tcg_optimize(TCGContext *s)
/* Save the corresponding known-zero bits mask for the
first output argument (only one supported so far). =
*/
if (i =3D=3D 0) {
- arg_info(op->args[i])->mask =3D mask;
+ arg_info(op->args[i])->z_mask =3D z_mask;
}
}
}
--=20
2.25.1