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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 03/56] host-utils: move udiv_qrnnd() to host-utils
Date: Wed, 27 Oct 2021 19:40:38 -0700
Message-Id: <20211028024131.1492790-4-richard.henderson@linaro.org>
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Cc: Luis Pires <luis.pires@eldorado.org.br>
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From: Luis Pires <luis.pires@eldorado.org.br>
Move udiv_qrnnd() from include/fpu/softfloat-macros.h to host-utils,
so it can be reused by divu128().
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211025191154.350831-3-luis.pires@eldorado.org.br>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/fpu/softfloat-macros.h | 82 ----------------------------------
include/qemu/host-utils.h | 81 +++++++++++++++++++++++++++++++++
2 files changed, 81 insertions(+), 82 deletions(-)
diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h
index 81c3fe8256..f35cdbfa63 100644
--- a/include/fpu/softfloat-macros.h
+++ b/include/fpu/softfloat-macros.h
@@ -8,7 +8,6 @@
* so some portions are provided under:
* the SoftFloat-2a license
* the BSD license
- * GPL-v2-or-later
*
* Any future contributions to this file after December 1st 2014 will be
* taken to be licensed under the Softfloat-2a license unless specifically
@@ -75,10 +74,6 @@ this code that are retained.
* THE POSSIBILITY OF SUCH DAMAGE.
*/
=20
-/* Portions of this work are licensed under the terms of the GNU GPL,
- * version 2 or later. See the COPYING file in the top-level directory.
- */
-
#ifndef FPU_SOFTFLOAT_MACROS_H
#define FPU_SOFTFLOAT_MACROS_H
=20
@@ -585,83 +580,6 @@ static inline uint64_t estimateDiv128To64(uint64_t a0,=
uint64_t a1, uint64_t b)
=20
}
=20
-/* From the GNU Multi Precision Library - longlong.h __udiv_qrnnd
- * (https://gmplib.org/repo/gmp/file/tip/longlong.h)
- *
- * Licensed under the GPLv2/LGPLv3
- */
-static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
- uint64_t n0, uint64_t d)
-{
-#if defined(__x86_64__)
- uint64_t q;
- asm("divq %4" : "=3Da"(q), "=3Dd"(*r) : "0"(n0), "1"(n1), "rm"(d));
- return q;
-#elif defined(__s390x__) && !defined(__clang__)
- /* Need to use a TImode type to get an even register pair for DLGR. */
- unsigned __int128 n =3D (unsigned __int128)n1 << 64 | n0;
- asm("dlgr %0, %1" : "+r"(n) : "r"(d));
- *r =3D n >> 64;
- return n;
-#elif defined(_ARCH_PPC64) && defined(_ARCH_PWR7)
- /* From Power ISA 2.06, programming note for divdeu. */
- uint64_t q1, q2, Q, r1, r2, R;
- asm("divdeu %0,%2,%4; divdu %1,%3,%4"
- : "=3D&r"(q1), "=3Dr"(q2)
- : "r"(n1), "r"(n0), "r"(d));
- r1 =3D -(q1 * d); /* low part of (n1<<64) - (q1 * d) */
- r2 =3D n0 - (q2 * d);
- Q =3D q1 + q2;
- R =3D r1 + r2;
- if (R >=3D d || R < r2) { /* overflow implies R > d */
- Q +=3D 1;
- R -=3D d;
- }
- *r =3D R;
- return Q;
-#else
- uint64_t d0, d1, q0, q1, r1, r0, m;
-
- d0 =3D (uint32_t)d;
- d1 =3D d >> 32;
-
- r1 =3D n1 % d1;
- q1 =3D n1 / d1;
- m =3D q1 * d0;
- r1 =3D (r1 << 32) | (n0 >> 32);
- if (r1 < m) {
- q1 -=3D 1;
- r1 +=3D d;
- if (r1 >=3D d) {
- if (r1 < m) {
- q1 -=3D 1;
- r1 +=3D d;
- }
- }
- }
- r1 -=3D m;
-
- r0 =3D r1 % d1;
- q0 =3D r1 / d1;
- m =3D q0 * d0;
- r0 =3D (r0 << 32) | (uint32_t)n0;
- if (r0 < m) {
- q0 -=3D 1;
- r0 +=3D d;
- if (r0 >=3D d) {
- if (r0 < m) {
- q0 -=3D 1;
- r0 +=3D d;
- }
- }
- }
- r0 -=3D m;
-
- *r =3D r0;
- return (q1 << 32) | q0;
-#endif
-}
-
/*------------------------------------------------------------------------=
----
| Returns an approximation to the square root of the 32-bit significand gi=
ven
| by `a'. Considered as an integer, `a' must be at least 2^31. If bit 0 =
of
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
index e82e6239af..08a17e16e5 100644
--- a/include/qemu/host-utils.h
+++ b/include/qemu/host-utils.h
@@ -23,6 +23,10 @@
* THE SOFTWARE.
*/
=20
+/* Portions of this work are licensed under the terms of the GNU GPL,
+ * version 2 or later. See the COPYING file in the top-level directory.
+ */
+
#ifndef HOST_UTILS_H
#define HOST_UTILS_H
=20
@@ -726,4 +730,81 @@ void urshift(uint64_t *plow, uint64_t *phigh, int32_t =
shift);
*/
void ulshift(uint64_t *plow, uint64_t *phigh, int32_t shift, bool *overflo=
w);
=20
+/* From the GNU Multi Precision Library - longlong.h __udiv_qrnnd
+ * (https://gmplib.org/repo/gmp/file/tip/longlong.h)
+ *
+ * Licensed under the GPLv2/LGPLv3
+ */
+static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
+ uint64_t n0, uint64_t d)
+{
+#if defined(__x86_64__)
+ uint64_t q;
+ asm("divq %4" : "=3Da"(q), "=3Dd"(*r) : "0"(n0), "1"(n1), "rm"(d));
+ return q;
+#elif defined(__s390x__) && !defined(__clang__)
+ /* Need to use a TImode type to get an even register pair for DLGR. */
+ unsigned __int128 n =3D (unsigned __int128)n1 << 64 | n0;
+ asm("dlgr %0, %1" : "+r"(n) : "r"(d));
+ *r =3D n >> 64;
+ return n;
+#elif defined(_ARCH_PPC64) && defined(_ARCH_PWR7)
+ /* From Power ISA 2.06, programming note for divdeu. */
+ uint64_t q1, q2, Q, r1, r2, R;
+ asm("divdeu %0,%2,%4; divdu %1,%3,%4"
+ : "=3D&r"(q1), "=3Dr"(q2)
+ : "r"(n1), "r"(n0), "r"(d));
+ r1 =3D -(q1 * d); /* low part of (n1<<64) - (q1 * d) */
+ r2 =3D n0 - (q2 * d);
+ Q =3D q1 + q2;
+ R =3D r1 + r2;
+ if (R >=3D d || R < r2) { /* overflow implies R > d */
+ Q +=3D 1;
+ R -=3D d;
+ }
+ *r =3D R;
+ return Q;
+#else
+ uint64_t d0, d1, q0, q1, r1, r0, m;
+
+ d0 =3D (uint32_t)d;
+ d1 =3D d >> 32;
+
+ r1 =3D n1 % d1;
+ q1 =3D n1 / d1;
+ m =3D q1 * d0;
+ r1 =3D (r1 << 32) | (n0 >> 32);
+ if (r1 < m) {
+ q1 -=3D 1;
+ r1 +=3D d;
+ if (r1 >=3D d) {
+ if (r1 < m) {
+ q1 -=3D 1;
+ r1 +=3D d;
+ }
+ }
+ }
+ r1 -=3D m;
+
+ r0 =3D r1 % d1;
+ q0 =3D r1 / d1;
+ m =3D q0 * d0;
+ r0 =3D (r0 << 32) | (uint32_t)n0;
+ if (r0 < m) {
+ q0 -=3D 1;
+ r0 +=3D d;
+ if (r0 >=3D d) {
+ if (r0 < m) {
+ q0 -=3D 1;
+ r0 +=3D d;
+ }
+ }
+ }
+ r0 -=3D m;
+
+ *r =3D r0;
+ return (q1 << 32) | q0;
+#endif
+}
+
#endif
--=20
2.25.1