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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id j7sm641617wmq.32.2021.10.27.11.10.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Oct 2021 11:10:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0oONdiURWAN4jI2LxqaDt83lwJJMkpLnHcdzTxz66k4=; b=b5hcHW+waBkdvPTbl30r+TKxH84mZnmcPE3IZOLWPWMsGjfLUnNEcMJpDFZhlrm6CJ 2jBlzrtTLbT5mLKYC//gEB9HL3fsFRTZR7r6iskKXiehzfNvTYNboq9N+WKGrAh5yw5t 7HKVAk6xslTijOuUEstmsSxgTLF2D1c+ORgwnT6EPglmVlKsVTQ7B04TivlIwnc6C1uf IVNvPwYh1fhhSgi9iLGWP0RLZvTpCuX43+Y1Zpe8/kq6Cd8fb9LVQ0r5vKbA7DGPNHhC 0yTG9gxrerQrs+NQsz7IKwdtr5hrELV5E+PPTFgX2eB6v75K38Mny1/sjhul25GX87TQ BoxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=0oONdiURWAN4jI2LxqaDt83lwJJMkpLnHcdzTxz66k4=; b=v4r8cRSIScq+RH5fKCROGIt74jGZ1Qgrd5PIr/HO/Eqo/+kbK6tpe9UqLwgoKcF3kR KTgrY2fskkFx3DQmrWEA5lEyD2cw57mJAD5Ph9XnIZ6nI57+CunWKIwEFiW5XtxMxSrZ qZoedC+8mQdeEXhYYINoOYQc3FlzSjZwYYZjVG+C06Nua6pZlUnTfgdBObukzT0ntGkP ow8R1j+hG5tihtYTHY7BvUFdQDSDA8WBATAEeCPq/IxCQrpH4+Q+ZzJv61RDEK3YSifL YlEb8z/tv/kl9A6bPrd+MyIF7RzjdgyckbAQdC+b06cuv+zDuU2pgg4HxSjYdm7gMPJ6 fDBA== X-Gm-Message-State: AOAM530PQbrQUj3ZaA+FYhdAnaa097J9yo/kOAurq0CM3BrGsDP8pRLm i/DfuNfY0eJgRiOT3Pvj2eM= X-Google-Smtp-Source: ABdhPJywWsLD0zcGBmlzNoRVpz2ufzxaMUeMrhjy8xZwBCaBiR4vg83SPukRngUbc12UUfCXm3wLDA== X-Received: by 2002:a5d:6acc:: with SMTP id u12mr32452187wrw.256.1635358202541; Wed, 27 Oct 2021 11:10:02 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Richard Henderson Subject: [PATCH v2 32/32] target/mips: Adjust style in msa_translate_init() Date: Wed, 27 Oct 2021 20:07:30 +0200 Message-Id: <20211027180730.1551932-33-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211027180730.1551932-1-f4bug@amsat.org> References: <20211027180730.1551932-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635358206416100001 While the first 'off' variable assignment is unused, it helps to better understand the code logic. Move the assignation where it would have been used so it is easier to compare the MSA registers based on FPU ones versus the MSA specific registers. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/msa_translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index ef0e00772a6..f6d4f32248c 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -122,13 +122,15 @@ void msa_translate_init(void) int i; =20 for (i =3D 0; i < 32; i++) { - int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + int off; =20 /* * The MSA vector registers are mapped on the * scalar floating-point unit (FPU) registers. */ + off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); msa_wr_d[i * 2] =3D fpu_f64[i]; + off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); msa_wr_d[i * 2 + 1] =3D tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); --=20 2.31.1