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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id o10sm437185wmr.31.2021.10.27.11.08.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Oct 2021 11:08:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0KChW80UPK11TbqXro4f3rmub/3y5xDcJ38gnGehEW0=; b=dyW9XiC5FUO/yjxjrPxwfAiY7cDGN3DBRAK+STZyQGJzuv1tlG71MeBFlcqDil67zZ YIARgudkeFZCTDZigDNjNGEae3XutXh4G4IgPn92HzZLr6gKkaivAq2zX+jRn/1VRUEy 4Ui8+2jjA1XK1K3h5RDgTHYJDIcOnWui9Gq9/d4w1oil4HiFXMxlsY2iH0Pf3B2F0lpT UR3MWAwet5VnAcLJCnVMB2gFp5V1S+jwAuYnITU2F9IZWsvQb4eeeIUZvBW7JRExrsDu Da7TzXJ9G6mCJxRKZ0DowspQLf+iv+/sWq3hjjW8Vf4H4LQ1yJsMTBXEVBlTVletlgV1 gb7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=0KChW80UPK11TbqXro4f3rmub/3y5xDcJ38gnGehEW0=; b=0ARYsYealbTzK2XB75rDDGaTWvbrU5sJOLmIKJx0i7TTdqBtsP01WHSCQs9hM7mnT1 ruwx9EAbz+nTMvb6SJc3ZY0a+x4/vFqVS8g28enJe5IEKB24uid6YJhZECArCiFeiaJQ BA0klqBgw/hugmCMJBx6h8bmsvrYA1g6HAYBlZPTIYQmz9bW8iwBat7ckswM8a6eFZE3 0gPCZDNkegfqg8WWxuEcGR79nHHFQB5oQpSjKReueP8jghGLrMYpC3f5bAbRTEfV2tfZ fPCOovq5M7V9eeGsZu74vivarztGWeL+cZz/XbgU2AATCSI8RExTvZfTwKBEEVOvlosd dZ6w== X-Gm-Message-State: AOAM531DhFfAxdT7LrN3zUo4zV3dTsKqmud3jcCnta4wcmZAfc4dwItR yqlN89c9x8y8dTR8KEGFoFo= X-Google-Smtp-Source: ABdhPJzITySOTenMoQrNUQnl9/XsljoSEOKEO1R5pXVuE6GoOsUq+EvGpG8q8f0exOwKXlx9O8e6iA== X-Received: by 2002:a5d:64ec:: with SMTP id g12mr42207134wri.140.1635358137110; Wed, 27 Oct 2021 11:08:57 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang Subject: [PATCH v2 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Date: Wed, 27 Oct 2021 20:07:16 +0200 Message-Id: <20211027180730.1551932-19-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211027180730.1551932-1-f4bug@amsat.org> References: <20211027180730.1551932-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635358140625100001 Convert 3-register floating-point or fixed-point operations to decodetree. Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/msa.decode | 8 +++++ target/mips/tcg/msa_translate.c | 64 +++++++++++++-------------------- 2 files changed, 33 insertions(+), 39 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index c9cc1529c8e..ace07f2f298 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -31,6 +31,7 @@ @vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=3D0 @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=3D0 @2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=3D0 +@3rf ...... .... df:1 wt:5 ws:5 wd:5 ...... &msa_r @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i5 @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i5 @i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i8 @@ -85,6 +86,13 @@ BNZ 010001 111 .. ..... ................= @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit =20 + MUL_Q 011110 0100 . ..... ..... ..... 011100 @3rf + MADD_Q 011110 0101 . ..... ..... ..... 011100 @3rf + MSUB_Q 011110 0110 . ..... ..... ..... 011100 @3rf + MULR_Q 011110 1100 . ..... ..... ..... 011100 @3rf + MADDR_Q 011110 1101 . ..... ..... ..... 011100 @3rf + MSUBR_Q 011110 1110 . ..... ..... ..... 011100 @3rf + AND_V 011110 00000 ..... ..... ..... 011110 @vec OR_V 011110 00001 ..... ..... ..... 011110 @vec NOR_V 011110 00010 ..... ..... ..... 011110 @vec diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index c7168608d42..4e0ad24543e 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -133,12 +133,9 @@ enum { OPC_FCNE_df =3D (0x3 << 22) | OPC_MSA_3RF_1C, OPC_FCLT_df =3D (0x4 << 22) | OPC_MSA_3RF_1A, OPC_FMADD_df =3D (0x4 << 22) | OPC_MSA_3RF_1B, - OPC_MUL_Q_df =3D (0x4 << 22) | OPC_MSA_3RF_1C, OPC_FCULT_df =3D (0x5 << 22) | OPC_MSA_3RF_1A, OPC_FMSUB_df =3D (0x5 << 22) | OPC_MSA_3RF_1B, - OPC_MADD_Q_df =3D (0x5 << 22) | OPC_MSA_3RF_1C, OPC_FCLE_df =3D (0x6 << 22) | OPC_MSA_3RF_1A, - OPC_MSUB_Q_df =3D (0x6 << 22) | OPC_MSA_3RF_1C, OPC_FCULE_df =3D (0x7 << 22) | OPC_MSA_3RF_1A, OPC_FEXP2_df =3D (0x7 << 22) | OPC_MSA_3RF_1B, OPC_FSAF_df =3D (0x8 << 22) | OPC_MSA_3RF_1A, @@ -152,13 +149,10 @@ enum { OPC_FSNE_df =3D (0xB << 22) | OPC_MSA_3RF_1C, OPC_FSLT_df =3D (0xC << 22) | OPC_MSA_3RF_1A, OPC_FMIN_df =3D (0xC << 22) | OPC_MSA_3RF_1B, - OPC_MULR_Q_df =3D (0xC << 22) | OPC_MSA_3RF_1C, OPC_FSULT_df =3D (0xD << 22) | OPC_MSA_3RF_1A, OPC_FMIN_A_df =3D (0xD << 22) | OPC_MSA_3RF_1B, - OPC_MADDR_Q_df =3D (0xD << 22) | OPC_MSA_3RF_1C, OPC_FSLE_df =3D (0xE << 22) | OPC_MSA_3RF_1A, OPC_FMAX_df =3D (0xE << 22) | OPC_MSA_3RF_1B, - OPC_MSUBR_Q_df =3D (0xE << 22) | OPC_MSA_3RF_1C, OPC_FSULE_df =3D (0xF << 22) | OPC_MSA_3RF_1A, OPC_FMAX_A_df =3D (0xF << 22) | OPC_MSA_3RF_1B, }; @@ -1655,6 +1649,30 @@ static void gen_msa_elm(DisasContext *ctx) gen_msa_elm_df(ctx, df, n); } =20 +static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a, + enum CPUMIPSMSADataFormat df_base, + gen_helper_piiii *gen_msa_3rf) +{ + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_msa_3rf(cpu_env, + tcg_constant_i32(a->df + df_base), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->wt)); + + return true; +} + +TRANS(MUL_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_mul_q_df); +TRANS(MADD_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_madd_q_df); +TRANS(MSUB_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_msub_q_df); +TRANS(MULR_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_mulr_q_df); +TRANS(MADDR_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_maddr_q_df); +TRANS(MSUBR_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_msubr_q_df); + static void gen_msa_3rf(DisasContext *ctx) { #define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) @@ -1666,22 +1684,8 @@ static void gen_msa_3rf(DisasContext *ctx) TCGv_i32 twd =3D tcg_const_i32(wd); TCGv_i32 tws =3D tcg_const_i32(ws); TCGv_i32 twt =3D tcg_const_i32(wt); - TCGv_i32 tdf; - /* adjust df value for floating-point instruction */ - switch (MASK_MSA_3RF(ctx->opcode)) { - case OPC_MUL_Q_df: - case OPC_MADD_Q_df: - case OPC_MSUB_Q_df: - case OPC_MULR_Q_df: - case OPC_MADDR_Q_df: - case OPC_MSUBR_Q_df: - tdf =3D tcg_constant_i32(DF_HALF + df); - break; - default: - tdf =3D tcg_constant_i32(DF_WORD + df); - break; - } + TCGv_i32 tdf =3D tcg_constant_i32(DF_WORD + df); =20 switch (MASK_MSA_3RF(ctx->opcode)) { case OPC_FCAF_df: @@ -1723,24 +1727,15 @@ static void gen_msa_3rf(DisasContext *ctx) case OPC_FMADD_df: gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MUL_Q_df: - gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FCULT_df: gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt); break; case OPC_FMSUB_df: gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MADD_Q_df: - gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FCLE_df: gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MSUB_Q_df: - gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FCULE_df: gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt); break; @@ -1780,27 +1775,18 @@ static void gen_msa_3rf(DisasContext *ctx) case OPC_FMIN_df: gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MULR_Q_df: - gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FSULT_df: gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt); break; case OPC_FMIN_A_df: gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MADDR_Q_df: - gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FSLE_df: gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt); break; case OPC_FMAX_df: gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MSUBR_Q_df: - gen_helper_msa_msubr_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FSULE_df: gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.31.1