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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id q14sm565035wrv.55.2021.10.27.11.08.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Oct 2021 11:08:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xAIPlMylYJ3Gy0H1MVl3gxJpMTP4ALLpwFtXCjc+06Q=; b=Ch49NJNpgGIrAj2MTu0h1aC7gKNjPGg5Ge30Q+3toYJzzaAy78/sxR5vDK/RoEt7s0 PXya7H1wGoqEVJFHLXnfTVZv17IwiMk/old7QnsUAuqdvsqUpSz0q2EmOjZJe9o7C7Rs E8G/NdNtFZ65mQIq/nSuhgM07Z63XWbegZKnumlBc21CrXORoM1RP+hzF9iVFDfG8Fhg FBj1V839BRzu5QICpvhWmQQNXRyn/NeGHuJO0/+TDMjf2IerpFR+0/zwtVe9qvMHboic 7pmCIAyloQDbkl5RxTDtS88dBvN/fP2l6JaKY3Sx49tFlzgk06XksCdmlAU2TlEWYGCv p2vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=xAIPlMylYJ3Gy0H1MVl3gxJpMTP4ALLpwFtXCjc+06Q=; b=3rX0WUuI9J5O6vmOb2/wnTo6yaiqIeyGQ0MHfyxgCJ/kbEH0vaxYcXoG30Kt+uRyKU iiCLV/vEhNYYU6khUtd8FTRmu072lRC4D+cripVLyO/zshvjHi6pr+FH15NfHUVwR9Bk xtwmozYTbYcgGot3OWrRYRm8XkXEwbA7/M/ZaY2CQZoFNGDy8NM3+x9sa5dhFWfiA2gq 9KoxnRlebwt3jnRp7XwfG/SutvzTVSJ+m8naidwG1+xFbxf0Ld/jA6Drd4Ua/pLk/Qor YfJ1r8uvmHeUS5iJti5pX2+OT4FXAa6sQf0hdXJjYX7kLKAWtN6oGrznZqRUvP3OEqg6 B8mg== X-Gm-Message-State: AOAM533N7lRRR0V+jUvZd1tPI/Iotm4G1DyQoavJIxtUKyeN96gmUtT2 nF5dgvXEB7giQbIFqJVJWB5GsaHQ1Zk= X-Google-Smtp-Source: ABdhPJxSTLBLj6/CABJX7P4yMHaX2cfD4HWjnsxG8M5ks9CsRNQvUL/MTz6KtGfd9zl1EnqaPVa9ow== X-Received: by 2002:adf:fccc:: with SMTP id f12mr10539949wrs.64.1635358118490; Wed, 27 Oct 2021 11:08:38 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Richard Henderson Subject: [PATCH v2 14/32] target/mips: Convert MSA 2RF instruction format to decodetree Date: Wed, 27 Oct 2021 20:07:12 +0200 Message-Id: <20211027180730.1551932-15-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211027180730.1551932-1-f4bug@amsat.org> References: <20211027180730.1551932-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635358122249100001 Convert 2-register floating-point operations to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/msa.decode | 19 ++++++ target/mips/tcg/msa_translate.c | 111 +++++++------------------------- 2 files changed, 44 insertions(+), 86 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index ca25d79bda4..395a2cbafeb 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -13,6 +13,7 @@ =20 &r rs rt rd sa =20 +&msa_r df wd ws wt &msa_bz df wt sa &msa_ldi df wd sa &msa_i5 df wd ws sa @@ -27,6 +28,7 @@ @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_ldst @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3D3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=3D0 @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i5 @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i5 @i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i8 @@ -81,6 +83,23 @@ BNZ 010001 111 .. ..... ................= @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit =20 + FCLASS 011110 110010000 . ..... ..... 011110 @2rf + FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf + FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf + FSQRT 011110 110010011 . ..... ..... 011110 @2rf + FRSQRT 011110 110010100 . ..... ..... 011110 @2rf + FRCP 011110 110010101 . ..... ..... 011110 @2rf + FRINT 011110 110010110 . ..... ..... 011110 @2rf + FLOG2 011110 110010111 . ..... ..... 011110 @2rf + FEXUPL 011110 110011000 . ..... ..... 011110 @2rf + FEXUPR 011110 110011001 . ..... ..... 011110 @2rf + FFQL 011110 110011010 . ..... ..... 011110 @2rf + FFQR 011110 110011011 . ..... ..... 011110 @2rf + FTINT_S 011110 110011100 . ..... ..... 011110 @2rf + FTINT_U 011110 110011101 . ..... ..... 011110 @2rf + FFINT_S 011110 110011110 . ..... ..... 011110 @2rf + FFINT_U 011110 110011111 . ..... ..... 011110 @2rf + LD 011110 .......... ..... ..... 1000 .. @ldst ST 011110 .......... ..... ..... 1001 .. @ldst =20 diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index afb9124501e..a61ba9a4db8 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -44,7 +44,7 @@ enum { }; =20 enum { - /* VEC/2R/2RF instruction */ + /* VEC/2R instruction */ OPC_AND_V =3D (0x00 << 21) | OPC_MSA_VEC, OPC_OR_V =3D (0x01 << 21) | OPC_MSA_VEC, OPC_NOR_V =3D (0x02 << 21) | OPC_MSA_VEC, @@ -54,7 +54,6 @@ enum { OPC_BSEL_V =3D (0x06 << 21) | OPC_MSA_VEC, =20 OPC_MSA_2R =3D (0x18 << 21) | OPC_MSA_VEC, - OPC_MSA_2RF =3D (0x19 << 21) | OPC_MSA_VEC, =20 /* 2R instruction df(bits 17..16) =3D _b, _h, _w, _d */ OPC_FILL_df =3D (0x00 << 18) | OPC_MSA_2R, @@ -62,24 +61,6 @@ enum { OPC_NLOC_df =3D (0x02 << 18) | OPC_MSA_2R, OPC_NLZC_df =3D (0x03 << 18) | OPC_MSA_2R, =20 - /* 2RF instruction df(bit 16) =3D _w, _d */ - OPC_FCLASS_df =3D (0x00 << 17) | OPC_MSA_2RF, - OPC_FTRUNC_S_df =3D (0x01 << 17) | OPC_MSA_2RF, - OPC_FTRUNC_U_df =3D (0x02 << 17) | OPC_MSA_2RF, - OPC_FSQRT_df =3D (0x03 << 17) | OPC_MSA_2RF, - OPC_FRSQRT_df =3D (0x04 << 17) | OPC_MSA_2RF, - OPC_FRCP_df =3D (0x05 << 17) | OPC_MSA_2RF, - OPC_FRINT_df =3D (0x06 << 17) | OPC_MSA_2RF, - OPC_FLOG2_df =3D (0x07 << 17) | OPC_MSA_2RF, - OPC_FEXUPL_df =3D (0x08 << 17) | OPC_MSA_2RF, - OPC_FEXUPR_df =3D (0x09 << 17) | OPC_MSA_2RF, - OPC_FFQL_df =3D (0x0A << 17) | OPC_MSA_2RF, - OPC_FFQR_df =3D (0x0B << 17) | OPC_MSA_2RF, - OPC_FTINT_S_df =3D (0x0C << 17) | OPC_MSA_2RF, - OPC_FTINT_U_df =3D (0x0D << 17) | OPC_MSA_2RF, - OPC_FFINT_S_df =3D (0x0E << 17) | OPC_MSA_2RF, - OPC_FFINT_U_df =3D (0x0F << 17) | OPC_MSA_2RF, - /* 3R instruction df(bits 22..21) =3D _b, _h, _w, d */ OPC_SLL_df =3D (0x0 << 23) | OPC_MSA_3R_0D, OPC_ADDV_df =3D (0x0 << 23) | OPC_MSA_3R_0E, @@ -1931,73 +1912,34 @@ static void gen_msa_2r(DisasContext *ctx) tcg_temp_free_i32(tws); } =20 -static void gen_msa_2rf(DisasContext *ctx) +static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a, + gen_helper_piii *gen_msa_2rf) { -#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ - (op & (0xf << 17))) - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - uint8_t df =3D (ctx->opcode >> 16) & 0x1; - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - /* adjust df value for floating-point instruction */ - TCGv_i32 tdf =3D tcg_constant_i32(DF_WORD + df); + gen_msa_2rf(cpu_env, + tcg_constant_i32(DF_WORD + a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws)); =20 - switch (MASK_MSA_2RF(ctx->opcode)) { - case OPC_FCLASS_df: - gen_helper_msa_fclass_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTRUNC_S_df: - gen_helper_msa_ftrunc_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTRUNC_U_df: - gen_helper_msa_ftrunc_u_df(cpu_env, tdf, twd, tws); - break; - case OPC_FSQRT_df: - gen_helper_msa_fsqrt_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRSQRT_df: - gen_helper_msa_frsqrt_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRCP_df: - gen_helper_msa_frcp_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRINT_df: - gen_helper_msa_frint_df(cpu_env, tdf, twd, tws); - break; - case OPC_FLOG2_df: - gen_helper_msa_flog2_df(cpu_env, tdf, twd, tws); - break; - case OPC_FEXUPL_df: - gen_helper_msa_fexupl_df(cpu_env, tdf, twd, tws); - break; - case OPC_FEXUPR_df: - gen_helper_msa_fexupr_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFQL_df: - gen_helper_msa_ffql_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFQR_df: - gen_helper_msa_ffqr_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTINT_S_df: - gen_helper_msa_ftint_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTINT_U_df: - gen_helper_msa_ftint_u_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFINT_S_df: - gen_helper_msa_ffint_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFINT_U_df: - gen_helper_msa_ffint_u_df(cpu_env, tdf, twd, tws); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); + return true; } =20 +TRANS_MSA(FCLASS, trans_msa_2rf, gen_helper_msa_fclass_df); +TRANS_MSA(FTRUNC_S, trans_msa_2rf, gen_helper_msa_fclass_df); +TRANS_MSA(FTRUNC_U, trans_msa_2rf, gen_helper_msa_ftrunc_s_df); +TRANS_MSA(FSQRT, trans_msa_2rf, gen_helper_msa_fsqrt_df); +TRANS_MSA(FRSQRT, trans_msa_2rf, gen_helper_msa_frsqrt_df); +TRANS_MSA(FRCP, trans_msa_2rf, gen_helper_msa_frcp_df); +TRANS_MSA(FRINT, trans_msa_2rf, gen_helper_msa_frint_df); +TRANS_MSA(FLOG2, trans_msa_2rf, gen_helper_msa_flog2_df); +TRANS_MSA(FEXUPL, trans_msa_2rf, gen_helper_msa_fexupl_df); +TRANS_MSA(FEXUPR, trans_msa_2rf, gen_helper_msa_fexupr_df); +TRANS_MSA(FFQL, trans_msa_2rf, gen_helper_msa_ffql_df); +TRANS_MSA(FFQR, trans_msa_2rf, gen_helper_msa_ffqr_df); +TRANS_MSA(FTINT_S, trans_msa_2rf, gen_helper_msa_ftint_s_df); +TRANS_MSA(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df); +TRANS_MSA(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df); +TRANS_MSA(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df); + static void gen_msa_vec_v(DisasContext *ctx) { #define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21))) @@ -2056,9 +1998,6 @@ static void gen_msa_vec(DisasContext *ctx) case OPC_MSA_2R: gen_msa_2r(ctx); break; - case OPC_MSA_2RF: - gen_msa_2rf(ctx); - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); --=20 2.31.1